490
500
* we use memory mapped registers.
493
#if !defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
503
#ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
494
504
/* Support PCI only */
495
static inline u32 uhci_readl(struct uhci_hcd *uhci, int reg)
505
static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
497
507
return inl(uhci->io_addr + reg);
500
static inline void uhci_writel(struct uhci_hcd *uhci, u32 val, int reg)
510
static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
502
512
outl(val, uhci->io_addr + reg);
505
static inline u16 uhci_readw(struct uhci_hcd *uhci, int reg)
515
static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
507
517
return inw(uhci->io_addr + reg);
510
static inline void uhci_writew(struct uhci_hcd *uhci, u16 val, int reg)
520
static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
512
522
outw(val, uhci->io_addr + reg);
515
static inline u8 uhci_readb(struct uhci_hcd *uhci, int reg)
525
static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
517
527
return inb(uhci->io_addr + reg);
520
static inline void uhci_writeb(struct uhci_hcd *uhci, u8 val, int reg)
530
static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
522
532
outb(val, uhci->io_addr + reg);
536
/* Support non-PCI host controllers */
526
538
/* Support PCI and non-PCI host controllers */
528
539
#define uhci_has_pci_registers(u) ((u)->io_addr != 0)
530
static inline u32 uhci_readl(struct uhci_hcd *uhci, int reg)
541
/* Support non-PCI host controllers only */
542
#define uhci_has_pci_registers(u) 0
545
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
546
/* Support (non-PCI) big endian host controllers */
547
#define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
549
#define uhci_big_endian_mmio(u) 0
552
static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
532
554
if (uhci_has_pci_registers(uhci))
533
555
return inl(uhci->io_addr + reg);
556
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
557
else if (uhci_big_endian_mmio(uhci))
558
return readl_be(uhci->regs + reg);
535
561
return readl(uhci->regs + reg);
538
static inline void uhci_writel(struct uhci_hcd *uhci, u32 val, int reg)
564
static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
540
566
if (uhci_has_pci_registers(uhci))
541
567
outl(val, uhci->io_addr + reg);
568
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
569
else if (uhci_big_endian_mmio(uhci))
570
writel_be(val, uhci->regs + reg);
543
573
writel(val, uhci->regs + reg);
546
static inline u16 uhci_readw(struct uhci_hcd *uhci, int reg)
576
static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
548
578
if (uhci_has_pci_registers(uhci))
549
579
return inw(uhci->io_addr + reg);
580
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
581
else if (uhci_big_endian_mmio(uhci))
582
return readw_be(uhci->regs + reg);
551
585
return readw(uhci->regs + reg);
554
static inline void uhci_writew(struct uhci_hcd *uhci, u16 val, int reg)
588
static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
556
590
if (uhci_has_pci_registers(uhci))
557
591
outw(val, uhci->io_addr + reg);
592
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
593
else if (uhci_big_endian_mmio(uhci))
594
writew_be(val, uhci->regs + reg);
559
597
writew(val, uhci->regs + reg);
562
static inline u8 uhci_readb(struct uhci_hcd *uhci, int reg)
600
static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
564
602
if (uhci_has_pci_registers(uhci))
565
603
return inb(uhci->io_addr + reg);
604
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
605
else if (uhci_big_endian_mmio(uhci))
606
return readb_be(uhci->regs + reg);
567
609
return readb(uhci->regs + reg);
570
static inline void uhci_writeb(struct uhci_hcd *uhci, u8 val, int reg)
612
static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
572
614
if (uhci_has_pci_registers(uhci))
573
615
outb(val, uhci->io_addr + reg);
616
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
617
else if (uhci_big_endian_mmio(uhci))
618
writeb_be(val, uhci->regs + reg);
575
621
writeb(val, uhci->regs + reg);
577
#endif /* !defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) */
623
#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
626
* The GRLIB GRUSBHC controller can use big endian format for its descriptors.
628
* UHCI controllers accessed through PCI work normally (little-endian
629
* everywhere), so we don't bother supporting a BE-only mode.
631
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
632
#define uhci_big_endian_desc(u) ((u)->big_endian_desc)
635
static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
637
return uhci_big_endian_desc(uhci)
638
? (__force __hc32)cpu_to_be32(x)
639
: (__force __hc32)cpu_to_le32(x);
643
static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
645
return uhci_big_endian_desc(uhci)
646
? be32_to_cpu((__force __be32)x)
647
: le32_to_cpu((__force __le32)x);
652
static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
654
return cpu_to_le32(x);
658
static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
660
return le32_to_cpu(x);