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Viewing changes to drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-57i0gl3v99b3lkfg
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

Show diffs side-by-side

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Lines of Context:
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
1
1
/*
2
 
 * Copyright (c) 2010 Atheros Communications Inc.
 
2
 * Copyright (c) 2010-2011 Atheros Communications Inc.
3
3
 *
4
4
 * Permission to use, copy, modify, and/or distribute this software for any
5
5
 * purpose with or without fee is hereby granted, provided that the above
306
306
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
307
307
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
308
308
 
309
 
                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 
309
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
310
310
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
311
311
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
312
312
 
883
883
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
884
884
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
885
885
 
886
 
                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 
886
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
887
887
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
888
888
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
889
889
 
2039
2039
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2040
2040
                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2041
2041
 
2042
 
                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 
2042
                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2043
2043
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2044
2044
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045
2045
 
3217
3217
                                    u8 *word, int length, int mdata_size)
3218
3218
{
3219
3219
        struct ath_common *common = ath9k_hw_common(ah);
3220
 
        u8 *dptr;
3221
3220
        const struct ar9300_eeprom *eep = NULL;
3222
3221
 
3223
3222
        switch (code) {
3235
3234
                break;
3236
3235
        case _CompressBlock:
3237
3236
                if (reference == 0) {
3238
 
                        dptr = mptr;
3239
3237
                } else {
3240
3238
                        eep = ar9003_eeprom_struct_find_by_id(reference);
3241
3239
                        if (eep == NULL) {
3329
3327
        else
3330
3328
                cptr = AR9300_BASE_ADDR;
3331
3329
        ath_dbg(common, ATH_DBG_EEPROM,
3332
 
                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
 
3330
                "Trying EEPROM access at Address 0x%04x\n", cptr);
3333
3331
        if (ar9300_check_eeprom_header(ah, read, cptr))
3334
3332
                goto found;
3335
3333
 
3336
3334
        cptr = AR9300_BASE_ADDR_512;
3337
3335
        ath_dbg(common, ATH_DBG_EEPROM,
3338
 
                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
 
3336
                "Trying EEPROM access at Address 0x%04x\n", cptr);
3339
3337
        if (ar9300_check_eeprom_header(ah, read, cptr))
3340
3338
                goto found;
3341
3339
 
3342
3340
        read = ar9300_read_otp;
3343
3341
        cptr = AR9300_BASE_ADDR;
3344
3342
        ath_dbg(common, ATH_DBG_EEPROM,
3345
 
                "Trying OTP accesss at Address 0x%04x\n", cptr);
 
3343
                "Trying OTP access at Address 0x%04x\n", cptr);
3346
3344
        if (ar9300_check_eeprom_header(ah, read, cptr))
3347
3345
                goto found;
3348
3346
 
3349
3347
        cptr = AR9300_BASE_ADDR_512;
3350
3348
        ath_dbg(common, ATH_DBG_EEPROM,
3351
 
                "Trying OTP accesss at Address 0x%04x\n", cptr);
 
3349
                "Trying OTP access at Address 0x%04x\n", cptr);
3352
3350
        if (ar9300_check_eeprom_header(ah, read, cptr))
3353
3351
                goto found;
3354
3352
 
3444
3442
{
3445
3443
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3446
3444
 
3447
 
        if (AR_SREV_9485(ah))
 
3445
        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3448
3446
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3449
3447
        else {
3450
3448
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3451
 
                REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
3452
 
                              bias >> 2);
3453
 
                REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
 
3449
                REG_RMW_FIELD(ah, AR_CH0_THERM,
 
3450
                                AR_CH0_THERM_XPABIASLVL_MSB,
 
3451
                                bias >> 2);
 
3452
                REG_RMW_FIELD(ah, AR_CH0_THERM,
 
3453
                                AR_CH0_THERM_XPASHORT2GND, 1);
3454
3454
        }
3455
3455
}
3456
3456
 
3497
3497
 
3498
3498
static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3499
3499
{
 
3500
        int chain;
 
3501
        u32 regval;
 
3502
        u32 ant_div_ctl1;
 
3503
        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
 
3504
                        AR_PHY_SWITCH_CHAIN_0,
 
3505
                        AR_PHY_SWITCH_CHAIN_1,
 
3506
                        AR_PHY_SWITCH_CHAIN_2,
 
3507
        };
 
3508
 
3500
3509
        u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
 
3510
 
3501
3511
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3502
3512
 
3503
3513
        value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3504
3514
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3505
3515
 
3506
 
        value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3507
 
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3508
 
 
3509
 
        if (!AR_SREV_9485(ah)) {
3510
 
                value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3511
 
                REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
3512
 
                              value);
3513
 
 
3514
 
                value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3515
 
                REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
3516
 
                              value);
 
3516
        for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
 
3517
                if ((ah->rxchainmask & BIT(chain)) ||
 
3518
                    (ah->txchainmask & BIT(chain))) {
 
3519
                        value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
 
3520
                                                             is2ghz);
 
3521
                        REG_RMW_FIELD(ah, switch_chain_reg[chain],
 
3522
                                      AR_SWITCH_TABLE_ALL, value);
 
3523
                }
3517
3524
        }
3518
3525
 
3519
3526
        if (AR_SREV_9485(ah)) {
3520
3527
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3521
 
                REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3522
 
                              value);
3523
 
                REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3524
 
                              value >> 6);
3525
 
                REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3526
 
                              value >> 7);
 
3528
                /*
 
3529
                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
 
3530
                 * are the fields present
 
3531
                 */
 
3532
                regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
 
3533
                regval &= (~AR_ANT_DIV_CTRL_ALL);
 
3534
                regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
 
3535
                /* enable_lnadiv */
 
3536
                regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
 
3537
                regval |= ((value >> 6) & 0x1) <<
 
3538
                                AR_PHY_9485_ANT_DIV_LNADIV_S;
 
3539
                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 
3540
 
 
3541
                /*enable fast_div */
 
3542
                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
 
3543
                regval &= (~AR_FAST_DIV_ENABLE);
 
3544
                regval |= ((value >> 7) & 0x1) <<
 
3545
                                AR_FAST_DIV_ENABLE_S;
 
3546
                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
 
3547
                ant_div_ctl1 =
 
3548
                        ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
 
3549
                /* check whether antenna diversity is enabled */
 
3550
                if ((ant_div_ctl1 >> 0x6) == 0x3) {
 
3551
                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
 
3552
                        /*
 
3553
                         * clear bits 25-30 main_lnaconf, alt_lnaconf,
 
3554
                         * main_tb, alt_tb
 
3555
                         */
 
3556
                        regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
 
3557
                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF |
 
3558
                                        AR_PHY_9485_ANT_DIV_ALT_GAINTB |
 
3559
                                        AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
 
3560
                        /* by default use LNA1 for the main antenna */
 
3561
                        regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
 
3562
                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
 
3563
                        regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
 
3564
                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
 
3565
                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 
3566
                }
 
3567
 
 
3568
 
3527
3569
        }
 
3570
 
3528
3571
}
3529
3572
 
3530
3573
static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3634
3677
 
3635
3678
        /* Test value. if 0 then attenuation is unused. Don't load anything. */
3636
3679
        for (i = 0; i < 3; i++) {
3637
 
                value = ar9003_hw_atten_chain_get(ah, i, chan);
3638
 
                REG_RMW_FIELD(ah, ext_atten_reg[i],
3639
 
                              AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
 
3680
                if (ah->txchainmask & BIT(i)) {
 
3681
                        value = ar9003_hw_atten_chain_get(ah, i, chan);
 
3682
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
 
3683
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3640
3684
 
3641
 
                value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3642
 
                REG_RMW_FIELD(ah, ext_atten_reg[i],
3643
 
                              AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
 
3685
                        value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
 
3686
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
 
3687
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
 
3688
                                      value);
 
3689
                }
3644
3690
        }
3645
3691
}
3646
3692
 
3749
3795
        ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3750
3796
        ar9003_hw_drive_strength_apply(ah);
3751
3797
        ar9003_hw_atten_apply(ah, chan);
3752
 
        ar9003_hw_internal_regulator_apply(ah);
3753
 
        if (AR_SREV_9485(ah))
 
3798
        if (!AR_SREV_9340(ah))
 
3799
                ar9003_hw_internal_regulator_apply(ah);
 
3800
        if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3754
3801
                ar9003_hw_apply_tuning_caps(ah);
3755
3802
}
3756
3803
 
4598
4645
        case 1:
4599
4646
                break;
4600
4647
        case 2:
4601
 
                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 
4648
                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
 
4649
                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 
4650
                else
 
4651
                        scaledPower = 0;
4602
4652
                break;
4603
4653
        case 3:
4604
 
                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 
4654
                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
 
4655
                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 
4656
                else
 
4657
                        scaledPower = 0;
4605
4658
                break;
4606
4659
        }
4607
4660