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* Copyright (c) 2010 qiaochong@loongson.cn
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* Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
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* Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
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* Copyright (c) 2010 Alexander Graf <agraf@suse.de>
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#define AHCI_PCI_BAR 5
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_SG 168 /* hardware max is 64K */
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#define AHCI_DMA_BOUNDARY 0xffffffff
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#define AHCI_USE_CLUSTERING 0
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#define AHCI_MAX_CMDS 32
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#define AHCI_CMD_SZ 32
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#define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
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#define AHCI_RX_FIS_SZ 256
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#define AHCI_CMD_TBL_CDB 0x40
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#define AHCI_CMD_TBL_HDR_SZ 0x80
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#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
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#define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
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#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
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#define AHCI_IRQ_ON_SG (1 << 31)
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#define AHCI_CMD_ATAPI (1 << 5)
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#define AHCI_CMD_WRITE (1 << 6)
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#define AHCI_CMD_PREFETCH (1 << 7)
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#define AHCI_CMD_RESET (1 << 8)
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#define AHCI_CMD_CLR_BUSY (1 << 10)
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#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
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#define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
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#define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
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/* global controller registers */
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#define HOST_CAP 0x00 /* host capabilities */
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#define HOST_CTL 0x04 /* global host control */
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#define HOST_IRQ_STAT 0x08 /* interrupt status */
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#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
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#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
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#define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
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#define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
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#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
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#define HOST_CAP_SSC (1 << 14) /* Slumber capable */
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#define HOST_CAP_AHCI (1 << 18) /* AHCI only */
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#define HOST_CAP_CLO (1 << 24) /* Command List Override support */
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#define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
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#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
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#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
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/* registers for each SATA port */
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#define PORT_LST_ADDR 0x00 /* command list DMA addr */
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#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
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#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
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#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
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#define PORT_IRQ_STAT 0x10 /* interrupt status */
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#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
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#define PORT_CMD 0x18 /* port command */
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#define PORT_TFDATA 0x20 /* taskfile data */
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#define PORT_SIG 0x24 /* device TF signature */
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#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
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#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
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#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
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#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
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#define PORT_CMD_ISSUE 0x38 /* command issue */
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#define PORT_RESERVED 0x3c /* reserved */
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/* PORT_IRQ_{STAT,MASK} bits */
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#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
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#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
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#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
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#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
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#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
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#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
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#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
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#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
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#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
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#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
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#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
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#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
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#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
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#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
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#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
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#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
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#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
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#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
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PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
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#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
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PORT_IRQ_HBUS_DATA_ERR)
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#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
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PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
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PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
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#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
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#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
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#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
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#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
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#define PORT_CMD_CLO (1 << 3) /* Command list override */
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#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
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#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
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#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
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#define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
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#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
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#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
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#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */
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#define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */
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#define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */
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#define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */
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#define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */
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#define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */
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#define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */
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#define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence
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#define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */
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#define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier
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#define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */
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#define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error
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#define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */
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#define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
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#define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
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#define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
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#define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
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#define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */
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#define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */
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#define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */
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#define ATA_SRST (1 << 2) /* software reset */
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#define STATE_RESET 1
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#define SATA_SCR_SSTATUS_DET_NODEV 0x0
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#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
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#define SATA_SCR_SSTATUS_SPD_NODEV 0x00
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#define SATA_SCR_SSTATUS_SPD_GEN1 0x10
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#define SATA_SCR_SSTATUS_IPM_NODEV 0x000
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#define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
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#define AHCI_SCR_SCTL_DET 0xf
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#define SATA_FIS_TYPE_REGISTER_H2D 0x27
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#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
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#define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
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#define AHCI_CMD_HDR_PRDT_LEN 16
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#define SATA_SIGNATURE_CDROM 0xeb140000
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#define SATA_SIGNATURE_DISK 0x00000101
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#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
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/* Shouldn't this be 0x2c? */
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#define AHCI_PORT_REGS_START_ADDR 0x100
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#define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
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#define AHCI_PORT_ADDR_OFFSET_LEN 0x80
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#define AHCI_NUM_COMMAND_SLOTS 31
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#define AHCI_SUPPORTED_SPEED 20
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#define AHCI_SUPPORTED_SPEED_GEN1 1
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#define AHCI_VERSION_1_0 0x10000
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#define AHCI_PROGMODE_MAJOR_REV_1 1
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#define AHCI_COMMAND_TABLE_ACMD 0x40
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#define IDE_FEATURE_DMA 1
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#define READ_FPDMA_QUEUED 0x60
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#define WRITE_FPDMA_QUEUED 0x61
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#define RES_FIS_DSFIS 0x00
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#define RES_FIS_PSFIS 0x20
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#define RES_FIS_RFIS 0x40
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#define RES_FIS_SDBFIS 0x58
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#define RES_FIS_UFIS 0x60
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typedef struct AHCIControlRegs {
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typedef struct AHCIPortRegs {
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uint32_t lst_addr_hi;
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uint32_t fis_addr_hi;
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typedef struct AHCICmdHdr {
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uint32_t reserved[4];
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} __attribute__ ((packed)) AHCICmdHdr;
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typedef struct AHCI_SG {
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} __attribute__ ((packed)) AHCI_SG;
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typedef struct AHCIDevice AHCIDevice;
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typedef struct NCQTransferState {
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BlockDriverAIOCB *aiocb;
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uint16_t sector_count;
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AHCIPortRegs port_regs;
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struct AHCIState *hba;
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int done_atapi_packet;
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BlockDriverCompletionFunc *dma_cb;
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NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
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typedef struct AHCIState {
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AHCIControlRegs control_regs;
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typedef struct AHCIPCIState {
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typedef struct NCQFrame {
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uint8_t sector_count_low;
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uint8_t sector_count_high;
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} __attribute__ ((packed)) NCQFrame;
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void ahci_init(AHCIState *s, DeviceState *qdev, int ports);
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void ahci_uninit(AHCIState *s);
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void ahci_reset(void *opaque);
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#endif /* HW_IDE_AHCI_H */
added
removed
hw/ide/ahci.h
