2
* Xilinx MicroBlaze emulation for qemu: main translation routines.
4
* Copyright (c) 2009 Edgar E. Iglesias.
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
8
* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
12
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14
* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
31
#include "microblaze-decode.h"
32
#include "qemu-common.h"
40
#if DISAS_MB && !SIM_COMPAT
41
# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43
# define LOG_DIS(...) do { } while (0)
48
#define EXTRACT_FIELD(src, start, end) \
49
(((src) >> start) & ((1 << (end - start + 1)) - 1))
51
static TCGv env_debug;
52
static TCGv_ptr cpu_env;
53
static TCGv cpu_R[32];
54
static TCGv cpu_SR[18];
56
static TCGv env_btaken;
57
static TCGv env_btarget;
58
static TCGv env_iflags;
60
#include "gen-icount.h"
62
/* This is the state at translation time. */
63
typedef struct DisasContext {
74
unsigned int cpustate_changed;
75
unsigned int delayed_branch;
76
unsigned int tb_flags, synced_flags; /* tb dependent flags. */
77
unsigned int clear_imm;
82
#define JMP_DIRECT_CC 2
83
#define JMP_INDIRECT 3
87
int abort_at_next_insn;
89
struct TranslationBlock *tb;
90
int singlestep_enabled;
93
static const char *regnames[] =
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
101
static const char *special_regnames[] =
103
"rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
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"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
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"sr16", "sr17", "sr18"
108
/* Sign extend at translation time. */
109
static inline int sign_extend(unsigned int val, unsigned int width)
121
static inline void t_sync_flags(DisasContext *dc)
123
/* Synch the tb dependant flags between translator and runtime. */
124
if (dc->tb_flags != dc->synced_flags) {
125
tcg_gen_movi_tl(env_iflags, dc->tb_flags);
126
dc->synced_flags = dc->tb_flags;
130
static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132
TCGv_i32 tmp = tcg_const_i32(index);
135
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
136
gen_helper_raise_exception(tmp);
137
tcg_temp_free_i32(tmp);
138
dc->is_jmp = DISAS_UPDATE;
141
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143
TranslationBlock *tb;
145
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147
tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
148
tcg_gen_exit_tb((tcg_target_long)tb + n);
150
tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
155
static void read_carry(DisasContext *dc, TCGv d)
157
tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
160
static void write_carry(DisasContext *dc, TCGv v)
162
TCGv t0 = tcg_temp_new();
163
tcg_gen_shli_tl(t0, v, 31);
164
tcg_gen_sari_tl(t0, t0, 31);
165
tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
166
tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
168
tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
172
/* True if ALU operand b is a small immediate that may deserve
174
static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176
/* Immediate insn without the imm prefix ? */
177
return dc->type_b && !(dc->tb_flags & IMM_FLAG);
180
static inline TCGv *dec_alu_op_b(DisasContext *dc)
183
if (dc->tb_flags & IMM_FLAG)
184
tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186
tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
189
return &cpu_R[dc->rb];
192
static void dec_add(DisasContext *dc)
200
LOG_DIS("add%s%s%s r%d r%d r%d\n",
201
dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
202
dc->rd, dc->ra, dc->rb);
204
/* Take care of the easy cases first. */
206
/* k - keep carry, no need to update MSR. */
207
/* If rd == r0, it's a nop. */
209
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
212
/* c - Add carry into the result. */
216
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
223
/* From now on, we can assume k is zero. So we need to update MSR. */
229
tcg_gen_movi_tl(cf, 0);
233
TCGv ncf = tcg_temp_new();
234
gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
235
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
236
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
237
write_carry(dc, ncf);
240
gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
246
static void dec_sub(DisasContext *dc)
248
unsigned int u, cmp, k, c;
254
cmp = (dc->imm & 1) && (!dc->type_b) && k;
257
LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
260
gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
262
gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
267
LOG_DIS("sub%s%s r%d, r%d r%d\n",
268
k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
270
/* Take care of the easy cases first. */
272
/* k - keep carry, no need to update MSR. */
273
/* If rd == r0, it's a nop. */
275
tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
278
/* c - Add carry into the result. */
282
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
289
/* From now on, we can assume k is zero. So we need to update MSR. */
290
/* Extract carry. And complement a into na. */
296
tcg_gen_movi_tl(cf, 1);
299
/* d = b + ~a + c. carry defaults to 1. */
300
tcg_gen_not_tl(na, cpu_R[dc->ra]);
303
TCGv ncf = tcg_temp_new();
304
gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
305
tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
306
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
307
write_carry(dc, ncf);
310
gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
317
static void dec_pattern(DisasContext *dc)
322
if ((dc->tb_flags & MSR_EE_FLAG)
323
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
324
&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
325
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
326
t_gen_raise_exception(dc, EXCP_HW_EXCP);
329
mode = dc->opcode & 3;
333
LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
335
gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
338
LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
340
TCGv t0 = tcg_temp_local_new();
341
l1 = gen_new_label();
342
tcg_gen_movi_tl(t0, 1);
343
tcg_gen_brcond_tl(TCG_COND_EQ,
344
cpu_R[dc->ra], cpu_R[dc->rb], l1);
345
tcg_gen_movi_tl(t0, 0);
347
tcg_gen_mov_tl(cpu_R[dc->rd], t0);
352
LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
353
l1 = gen_new_label();
355
TCGv t0 = tcg_temp_local_new();
356
tcg_gen_movi_tl(t0, 1);
357
tcg_gen_brcond_tl(TCG_COND_NE,
358
cpu_R[dc->ra], cpu_R[dc->rb], l1);
359
tcg_gen_movi_tl(t0, 0);
361
tcg_gen_mov_tl(cpu_R[dc->rd], t0);
367
"unsupported pattern insn opcode=%x\n", dc->opcode);
372
static void dec_and(DisasContext *dc)
376
if (!dc->type_b && (dc->imm & (1 << 10))) {
381
not = dc->opcode & (1 << 1);
382
LOG_DIS("and%s\n", not ? "n" : "");
388
TCGv t = tcg_temp_new();
389
tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
390
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
393
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
396
static void dec_or(DisasContext *dc)
398
if (!dc->type_b && (dc->imm & (1 << 10))) {
403
LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
405
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
408
static void dec_xor(DisasContext *dc)
410
if (!dc->type_b && (dc->imm & (1 << 10))) {
415
LOG_DIS("xor r%d\n", dc->rd);
417
tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
420
static inline void msr_read(DisasContext *dc, TCGv d)
422
tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
425
static inline void msr_write(DisasContext *dc, TCGv v)
427
dc->cpustate_changed = 1;
428
tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
429
/* PVR, we have a processor version register. */
430
tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
433
static void dec_msr(DisasContext *dc)
436
unsigned int sr, to, rn;
437
int mem_index = cpu_mmu_index(dc->env);
439
sr = dc->imm & ((1 << 14) - 1);
440
to = dc->imm & (1 << 14);
443
dc->cpustate_changed = 1;
445
/* msrclr and msrset. */
446
if (!(dc->imm & (1 << 15))) {
447
unsigned int clr = dc->ir & (1 << 16);
449
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
452
if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
457
if ((dc->tb_flags & MSR_EE_FLAG)
458
&& mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
459
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
460
t_gen_raise_exception(dc, EXCP_HW_EXCP);
465
msr_read(dc, cpu_R[dc->rd]);
470
tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
473
tcg_gen_not_tl(t1, t1);
474
tcg_gen_and_tl(t0, t0, t1);
476
tcg_gen_or_tl(t0, t0, t1);
480
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
481
dc->is_jmp = DISAS_UPDATE;
486
if ((dc->tb_flags & MSR_EE_FLAG)
487
&& mem_index == MMU_USER_IDX) {
488
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
489
t_gen_raise_exception(dc, EXCP_HW_EXCP);
494
#if !defined(CONFIG_USER_ONLY)
495
/* Catch read/writes to the mmu block. */
496
if ((sr & ~0xff) == 0x1000) {
498
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
500
gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
502
gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
508
LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
513
msr_write(dc, cpu_R[dc->ra]);
516
tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
519
tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
522
tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
525
cpu_abort(dc->env, "unknown mts reg %x\n", sr);
529
LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
533
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
536
msr_read(dc, cpu_R[dc->rd]);
539
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
542
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
545
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
548
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
564
tcg_gen_ld_tl(cpu_R[dc->rd],
565
cpu_env, offsetof(CPUState, pvr.regs[rn]));
568
cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
574
tcg_gen_movi_tl(cpu_R[0], 0);
578
/* 64-bit signed mul, lower result in d and upper in d2. */
579
static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
583
t0 = tcg_temp_new_i64();
584
t1 = tcg_temp_new_i64();
586
tcg_gen_ext_i32_i64(t0, a);
587
tcg_gen_ext_i32_i64(t1, b);
588
tcg_gen_mul_i64(t0, t0, t1);
590
tcg_gen_trunc_i64_i32(d, t0);
591
tcg_gen_shri_i64(t0, t0, 32);
592
tcg_gen_trunc_i64_i32(d2, t0);
594
tcg_temp_free_i64(t0);
595
tcg_temp_free_i64(t1);
598
/* 64-bit unsigned muls, lower result in d and upper in d2. */
599
static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
603
t0 = tcg_temp_new_i64();
604
t1 = tcg_temp_new_i64();
606
tcg_gen_extu_i32_i64(t0, a);
607
tcg_gen_extu_i32_i64(t1, b);
608
tcg_gen_mul_i64(t0, t0, t1);
610
tcg_gen_trunc_i64_i32(d, t0);
611
tcg_gen_shri_i64(t0, t0, 32);
612
tcg_gen_trunc_i64_i32(d2, t0);
614
tcg_temp_free_i64(t0);
615
tcg_temp_free_i64(t1);
618
/* Multiplier unit. */
619
static void dec_mul(DisasContext *dc)
622
unsigned int subcode;
624
if ((dc->tb_flags & MSR_EE_FLAG)
625
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
626
&& !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
627
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
628
t_gen_raise_exception(dc, EXCP_HW_EXCP);
632
subcode = dc->imm & 3;
633
d[0] = tcg_temp_new();
634
d[1] = tcg_temp_new();
637
LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
638
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
642
/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
643
if (subcode >= 1 && subcode <= 3
644
&& !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
650
LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
651
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
654
LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
655
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
658
LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
659
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
662
LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
663
t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
666
cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
675
static void dec_div(DisasContext *dc)
682
if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
683
&& !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
684
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
685
t_gen_raise_exception(dc, EXCP_HW_EXCP);
689
gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
691
gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
693
tcg_gen_movi_tl(cpu_R[dc->rd], 0);
696
static void dec_barrel(DisasContext *dc)
701
if ((dc->tb_flags & MSR_EE_FLAG)
702
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
703
&& !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
704
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
705
t_gen_raise_exception(dc, EXCP_HW_EXCP);
709
s = dc->imm & (1 << 10);
710
t = dc->imm & (1 << 9);
712
LOG_DIS("bs%s%s r%d r%d r%d\n",
713
s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
717
tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
718
tcg_gen_andi_tl(t0, t0, 31);
721
tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
724
tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
726
tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
730
static void dec_bit(DisasContext *dc)
734
int mem_index = cpu_mmu_index(dc->env);
736
op = dc->ir & ((1 << 8) - 1);
742
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
743
tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
747
tcg_gen_shli_tl(t1, t1, 31);
749
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
750
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
763
LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
766
tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
771
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
773
tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
777
LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
778
tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
781
LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
782
tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
789
LOG_DIS("wdc r%d\n", dc->ra);
790
if ((dc->tb_flags & MSR_EE_FLAG)
791
&& mem_index == MMU_USER_IDX) {
792
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
793
t_gen_raise_exception(dc, EXCP_HW_EXCP);
799
LOG_DIS("wic r%d\n", dc->ra);
800
if ((dc->tb_flags & MSR_EE_FLAG)
801
&& mem_index == MMU_USER_IDX) {
802
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
803
t_gen_raise_exception(dc, EXCP_HW_EXCP);
808
cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
809
dc->pc, op, dc->rd, dc->ra, dc->rb);
814
static inline void sync_jmpstate(DisasContext *dc)
816
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
817
if (dc->jmp == JMP_DIRECT) {
818
tcg_gen_movi_tl(env_btaken, 1);
820
dc->jmp = JMP_INDIRECT;
821
tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
825
static void dec_imm(DisasContext *dc)
827
LOG_DIS("imm %x\n", dc->imm << 16);
828
tcg_gen_movi_tl(env_imm, (dc->imm << 16));
829
dc->tb_flags |= IMM_FLAG;
833
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
836
int mem_index = cpu_mmu_index(dc->env);
839
tcg_gen_qemu_ld8u(dst, addr, mem_index);
840
} else if (size == 2) {
841
tcg_gen_qemu_ld16u(dst, addr, mem_index);
842
} else if (size == 4) {
843
tcg_gen_qemu_ld32u(dst, addr, mem_index);
845
cpu_abort(dc->env, "Incorrect load size %d\n", size);
848
static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
850
unsigned int extimm = dc->tb_flags & IMM_FLAG;
852
/* Treat the common cases first. */
854
/* If any of the regs is r0, return a ptr to the other. */
856
return &cpu_R[dc->rb];
857
} else if (dc->rb == 0) {
858
return &cpu_R[dc->ra];
862
tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
868
return &cpu_R[dc->ra];
871
tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
872
tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
875
tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
881
static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
884
tcg_gen_bswap32_tl(dst, src);
885
} else if (size == 2) {
886
TCGv t = tcg_temp_new();
888
/* bswap16 assumes the high bits are zero. */
889
tcg_gen_andi_tl(t, src, 0xffff);
890
tcg_gen_bswap16_tl(dst, t);
894
cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
899
static void dec_load(DisasContext *dc)
902
unsigned int size, rev = 0;
904
size = 1 << (dc->opcode & 3);
907
rev = (dc->ir >> 9) & 1;
910
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
911
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
912
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
913
t_gen_raise_exception(dc, EXCP_HW_EXCP);
917
LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
920
addr = compute_ldst_addr(dc, &t);
923
* When doing reverse accesses we need to do two things.
925
* 1. Reverse the address wrt endianness.
926
* 2. Byteswap the data lanes on the way back into the CPU core.
928
if (rev && size != 4) {
929
/* Endian reverse the address. t is addr. */
937
TCGv low = tcg_temp_new();
939
/* Force addr into the temp. */
942
tcg_gen_mov_tl(t, *addr);
946
tcg_gen_andi_tl(low, t, 3);
947
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
948
tcg_gen_andi_tl(t, t, ~3);
949
tcg_gen_or_tl(t, t, low);
950
tcg_gen_mov_tl(env_imm, t);
958
/* Force addr into the temp. */
961
tcg_gen_xori_tl(t, *addr, 2);
964
tcg_gen_xori_tl(t, t, 2);
968
cpu_abort(dc->env, "Invalid reverse size\n");
973
/* If we get a fault on a dslot, the jmpstate better be in sync. */
976
/* Verify alignment if needed. */
977
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
978
TCGv v = tcg_temp_new();
981
* Microblaze gives MMU faults priority over faults due to
982
* unaligned addresses. That's why we speculatively do the load
983
* into v. If the load succeeds, we verify alignment of the
984
* address and if that succeeds we write into the destination reg.
986
gen_load(dc, v, *addr, size);
988
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
989
gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
990
tcg_const_tl(0), tcg_const_tl(size - 1));
993
dec_byteswap(dc, cpu_R[dc->rd], v, size);
995
tcg_gen_mov_tl(cpu_R[dc->rd], v);
1001
gen_load(dc, cpu_R[dc->rd], *addr, size);
1003
dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1006
/* We are loading into r0, no need to reverse. */
1007
gen_load(dc, env_imm, *addr, size);
1015
static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1018
int mem_index = cpu_mmu_index(dc->env);
1021
tcg_gen_qemu_st8(val, addr, mem_index);
1022
else if (size == 2) {
1023
tcg_gen_qemu_st16(val, addr, mem_index);
1024
} else if (size == 4) {
1025
tcg_gen_qemu_st32(val, addr, mem_index);
1027
cpu_abort(dc->env, "Incorrect store size %d\n", size);
1030
static void dec_store(DisasContext *dc)
1033
unsigned int size, rev = 0;
1035
size = 1 << (dc->opcode & 3);
1037
rev = (dc->ir >> 9) & 1;
1040
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
1041
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1042
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1043
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1047
LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
1049
/* If we get a fault on a dslot, the jmpstate better be in sync. */
1051
addr = compute_ldst_addr(dc, &t);
1053
if (rev && size != 4) {
1054
/* Endian reverse the address. t is addr. */
1062
TCGv low = tcg_temp_new();
1064
/* Force addr into the temp. */
1067
tcg_gen_mov_tl(t, *addr);
1071
tcg_gen_andi_tl(low, t, 3);
1072
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1073
tcg_gen_andi_tl(t, t, ~3);
1074
tcg_gen_or_tl(t, t, low);
1075
tcg_gen_mov_tl(env_imm, t);
1083
/* Force addr into the temp. */
1086
tcg_gen_xori_tl(t, *addr, 2);
1089
tcg_gen_xori_tl(t, t, 2);
1093
cpu_abort(dc->env, "Invalid reverse size\n");
1098
TCGv bs_data = tcg_temp_new();
1099
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1100
gen_store(dc, *addr, bs_data, size);
1101
tcg_temp_free(bs_data);
1103
gen_store(dc, *addr, cpu_R[dc->rd], size);
1107
TCGv bs_data = tcg_temp_new();
1108
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1109
gen_store(dc, *addr, bs_data, size);
1110
tcg_temp_free(bs_data);
1112
gen_store(dc, *addr, cpu_R[dc->rd], size);
1116
/* Verify alignment if needed. */
1117
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1118
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1119
/* FIXME: if the alignment is wrong, we should restore the value
1120
* in memory. One possible way to acheive this is to probe
1121
* the MMU prior to the memaccess, thay way we could put
1122
* the alignment checks in between the probe and the mem
1125
gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
1126
tcg_const_tl(1), tcg_const_tl(size - 1));
1133
static inline void eval_cc(DisasContext *dc, unsigned int cc,
1134
TCGv d, TCGv a, TCGv b)
1138
tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1141
tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1144
tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1147
tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1150
tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1153
tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1156
cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1161
static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1165
l1 = gen_new_label();
1166
/* Conditional jmp. */
1167
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1168
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1169
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1173
static void dec_bcc(DisasContext *dc)
1178
cc = EXTRACT_FIELD(dc->ir, 21, 23);
1179
dslot = dc->ir & (1 << 25);
1180
LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1182
dc->delayed_branch = 1;
1184
dc->delayed_branch = 2;
1185
dc->tb_flags |= D_FLAG;
1186
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1187
cpu_env, offsetof(CPUState, bimm));
1190
if (dec_alu_op_b_is_small_imm(dc)) {
1191
int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1193
tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1194
dc->jmp = JMP_DIRECT_CC;
1195
dc->jmp_pc = dc->pc + offset;
1197
dc->jmp = JMP_INDIRECT;
1198
tcg_gen_movi_tl(env_btarget, dc->pc);
1199
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1201
eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1204
static void dec_br(DisasContext *dc)
1206
unsigned int dslot, link, abs;
1207
int mem_index = cpu_mmu_index(dc->env);
1209
dslot = dc->ir & (1 << 20);
1210
abs = dc->ir & (1 << 19);
1211
link = dc->ir & (1 << 18);
1212
LOG_DIS("br%s%s%s%s imm=%x\n",
1213
abs ? "a" : "", link ? "l" : "",
1214
dc->type_b ? "i" : "", dslot ? "d" : "",
1217
dc->delayed_branch = 1;
1219
dc->delayed_branch = 2;
1220
dc->tb_flags |= D_FLAG;
1221
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1222
cpu_env, offsetof(CPUState, bimm));
1225
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1227
dc->jmp = JMP_INDIRECT;
1229
tcg_gen_movi_tl(env_btaken, 1);
1230
tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1231
if (link && !dslot) {
1232
if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1233
t_gen_raise_exception(dc, EXCP_BREAK);
1235
if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1236
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1237
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1241
t_gen_raise_exception(dc, EXCP_DEBUG);
1245
if (dec_alu_op_b_is_small_imm(dc)) {
1246
dc->jmp = JMP_DIRECT;
1247
dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1249
tcg_gen_movi_tl(env_btaken, 1);
1250
tcg_gen_movi_tl(env_btarget, dc->pc);
1251
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1256
static inline void do_rti(DisasContext *dc)
1259
t0 = tcg_temp_new();
1260
t1 = tcg_temp_new();
1261
tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1262
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1263
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1265
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1266
tcg_gen_or_tl(t1, t1, t0);
1270
dc->tb_flags &= ~DRTI_FLAG;
1273
static inline void do_rtb(DisasContext *dc)
1276
t0 = tcg_temp_new();
1277
t1 = tcg_temp_new();
1278
tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1279
tcg_gen_shri_tl(t0, t1, 1);
1280
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1282
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1283
tcg_gen_or_tl(t1, t1, t0);
1287
dc->tb_flags &= ~DRTB_FLAG;
1290
static inline void do_rte(DisasContext *dc)
1293
t0 = tcg_temp_new();
1294
t1 = tcg_temp_new();
1296
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1297
tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1298
tcg_gen_shri_tl(t0, t1, 1);
1299
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1301
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1302
tcg_gen_or_tl(t1, t1, t0);
1306
dc->tb_flags &= ~DRTE_FLAG;
1309
static void dec_rts(DisasContext *dc)
1311
unsigned int b_bit, i_bit, e_bit;
1312
int mem_index = cpu_mmu_index(dc->env);
1314
i_bit = dc->ir & (1 << 21);
1315
b_bit = dc->ir & (1 << 22);
1316
e_bit = dc->ir & (1 << 23);
1318
dc->delayed_branch = 2;
1319
dc->tb_flags |= D_FLAG;
1320
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1321
cpu_env, offsetof(CPUState, bimm));
1324
LOG_DIS("rtid ir=%x\n", dc->ir);
1325
if ((dc->tb_flags & MSR_EE_FLAG)
1326
&& mem_index == MMU_USER_IDX) {
1327
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1328
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1330
dc->tb_flags |= DRTI_FLAG;
1332
LOG_DIS("rtbd ir=%x\n", dc->ir);
1333
if ((dc->tb_flags & MSR_EE_FLAG)
1334
&& mem_index == MMU_USER_IDX) {
1335
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1336
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1338
dc->tb_flags |= DRTB_FLAG;
1340
LOG_DIS("rted ir=%x\n", dc->ir);
1341
if ((dc->tb_flags & MSR_EE_FLAG)
1342
&& mem_index == MMU_USER_IDX) {
1343
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1344
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1346
dc->tb_flags |= DRTE_FLAG;
1348
LOG_DIS("rts ir=%x\n", dc->ir);
1350
dc->jmp = JMP_INDIRECT;
1351
tcg_gen_movi_tl(env_btaken, 1);
1352
tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1355
static int dec_check_fpuv2(DisasContext *dc)
1359
r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1361
if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1362
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1363
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1368
static void dec_fpu(DisasContext *dc)
1370
unsigned int fpu_insn;
1372
if ((dc->tb_flags & MSR_EE_FLAG)
1373
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1374
&& !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1375
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1376
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1380
fpu_insn = (dc->ir >> 7) & 7;
1384
gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1388
gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1392
gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1396
gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1400
switch ((dc->ir >> 4) & 7) {
1402
gen_helper_fcmp_un(cpu_R[dc->rd],
1403
cpu_R[dc->ra], cpu_R[dc->rb]);
1406
gen_helper_fcmp_lt(cpu_R[dc->rd],
1407
cpu_R[dc->ra], cpu_R[dc->rb]);
1410
gen_helper_fcmp_eq(cpu_R[dc->rd],
1411
cpu_R[dc->ra], cpu_R[dc->rb]);
1414
gen_helper_fcmp_le(cpu_R[dc->rd],
1415
cpu_R[dc->ra], cpu_R[dc->rb]);
1418
gen_helper_fcmp_gt(cpu_R[dc->rd],
1419
cpu_R[dc->ra], cpu_R[dc->rb]);
1422
gen_helper_fcmp_ne(cpu_R[dc->rd],
1423
cpu_R[dc->ra], cpu_R[dc->rb]);
1426
gen_helper_fcmp_ge(cpu_R[dc->rd],
1427
cpu_R[dc->ra], cpu_R[dc->rb]);
1430
qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1431
fpu_insn, dc->pc, dc->opcode);
1432
dc->abort_at_next_insn = 1;
1438
if (!dec_check_fpuv2(dc)) {
1441
gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1445
if (!dec_check_fpuv2(dc)) {
1448
gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1452
if (!dec_check_fpuv2(dc)) {
1455
gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1459
qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1460
fpu_insn, dc->pc, dc->opcode);
1461
dc->abort_at_next_insn = 1;
1466
static void dec_null(DisasContext *dc)
1468
if ((dc->tb_flags & MSR_EE_FLAG)
1469
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1470
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1471
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1474
qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1475
dc->abort_at_next_insn = 1;
1478
/* Insns connected to FSL or AXI stream attached devices. */
1479
static void dec_stream(DisasContext *dc)
1481
int mem_index = cpu_mmu_index(dc->env);
1482
TCGv_i32 t_id, t_ctrl;
1485
LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1486
dc->type_b ? "" : "d", dc->imm);
1488
if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1489
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1490
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1494
t_id = tcg_temp_new();
1496
tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1497
ctrl = dc->imm >> 10;
1499
tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1500
ctrl = dc->imm >> 5;
1503
t_ctrl = tcg_const_tl(ctrl);
1506
gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1508
gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1510
tcg_temp_free(t_id);
1511
tcg_temp_free(t_ctrl);
1514
static struct decoder_info {
1519
void (*dec)(DisasContext *dc);
1527
{DEC_BARREL, dec_barrel},
1529
{DEC_ST, dec_store},
1538
{DEC_STREAM, dec_stream},
1542
static inline void decode(DisasContext *dc)
1547
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1548
tcg_gen_debug_insn_start(dc->pc);
1550
dc->ir = ir = ldl_code(dc->pc);
1551
LOG_DIS("%8.8x\t", dc->ir);
1556
if ((dc->tb_flags & MSR_EE_FLAG)
1557
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1558
&& (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1559
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1560
t_gen_raise_exception(dc, EXCP_HW_EXCP);
1564
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1566
if (dc->nr_nops > 4)
1567
cpu_abort(dc->env, "fetching nop sequence\n");
1569
/* bit 2 seems to indicate insn type. */
1570
dc->type_b = ir & (1 << 29);
1572
dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1573
dc->rd = EXTRACT_FIELD(ir, 21, 25);
1574
dc->ra = EXTRACT_FIELD(ir, 16, 20);
1575
dc->rb = EXTRACT_FIELD(ir, 11, 15);
1576
dc->imm = EXTRACT_FIELD(ir, 0, 15);
1578
/* Large switch for all insns. */
1579
for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1580
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1587
static void check_breakpoint(CPUState *env, DisasContext *dc)
1591
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1592
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1593
if (bp->pc == dc->pc) {
1594
t_gen_raise_exception(dc, EXCP_DEBUG);
1595
dc->is_jmp = DISAS_UPDATE;
1601
/* generate intermediate code for basic block 'tb'. */
1603
gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1606
uint16_t *gen_opc_end;
1609
struct DisasContext ctx;
1610
struct DisasContext *dc = &ctx;
1611
uint32_t next_page_start, org_flags;
1616
qemu_log_try_set_file(stderr);
1621
org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1623
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1625
dc->is_jmp = DISAS_NEXT;
1627
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1628
if (dc->delayed_branch) {
1629
dc->jmp = JMP_INDIRECT;
1632
dc->singlestep_enabled = env->singlestep_enabled;
1633
dc->cpustate_changed = 0;
1634
dc->abort_at_next_insn = 0;
1638
cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1640
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1642
qemu_log("--------------\n");
1643
log_cpu_state(env, 0);
1647
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1650
max_insns = tb->cflags & CF_COUNT_MASK;
1652
max_insns = CF_COUNT_MASK;
1658
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1659
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1663
check_breakpoint(env, dc);
1666
j = gen_opc_ptr - gen_opc_buf;
1670
gen_opc_instr_start[lj++] = 0;
1672
gen_opc_pc[lj] = dc->pc;
1673
gen_opc_instr_start[lj] = 1;
1674
gen_opc_icount[lj] = num_insns;
1678
LOG_DIS("%8.8x:\t", dc->pc);
1680
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1686
dc->tb_flags &= ~IMM_FLAG;
1690
if (dc->delayed_branch) {
1691
dc->delayed_branch--;
1692
if (!dc->delayed_branch) {
1693
if (dc->tb_flags & DRTI_FLAG)
1695
if (dc->tb_flags & DRTB_FLAG)
1697
if (dc->tb_flags & DRTE_FLAG)
1699
/* Clear the delay slot flag. */
1700
dc->tb_flags &= ~D_FLAG;
1701
/* If it is a direct jump, try direct chaining. */
1702
if (dc->jmp == JMP_INDIRECT) {
1703
eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1704
dc->is_jmp = DISAS_JUMP;
1705
} else if (dc->jmp == JMP_DIRECT) {
1707
gen_goto_tb(dc, 0, dc->jmp_pc);
1708
dc->is_jmp = DISAS_TB_JUMP;
1709
} else if (dc->jmp == JMP_DIRECT_CC) {
1713
l1 = gen_new_label();
1714
/* Conditional jmp. */
1715
tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1716
gen_goto_tb(dc, 1, dc->pc);
1718
gen_goto_tb(dc, 0, dc->jmp_pc);
1720
dc->is_jmp = DISAS_TB_JUMP;
1725
if (env->singlestep_enabled)
1727
} while (!dc->is_jmp && !dc->cpustate_changed
1728
&& gen_opc_ptr < gen_opc_end
1730
&& (dc->pc < next_page_start)
1731
&& num_insns < max_insns);
1734
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1735
if (dc->tb_flags & D_FLAG) {
1736
dc->is_jmp = DISAS_UPDATE;
1737
tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1743
if (tb->cflags & CF_LAST_IO)
1745
/* Force an update if the per-tb cpu state has changed. */
1746
if (dc->is_jmp == DISAS_NEXT
1747
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1748
dc->is_jmp = DISAS_UPDATE;
1749
tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1753
if (unlikely(env->singlestep_enabled)) {
1754
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1756
if (dc->is_jmp != DISAS_JUMP) {
1757
tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1759
gen_helper_raise_exception(tmp);
1760
tcg_temp_free_i32(tmp);
1762
switch(dc->is_jmp) {
1764
gen_goto_tb(dc, 1, npc);
1769
/* indicate that the hash table must be used
1770
to find the next TB */
1774
/* nothing more to generate */
1778
gen_icount_end(tb, num_insns);
1779
*gen_opc_ptr = INDEX_op_end;
1781
j = gen_opc_ptr - gen_opc_buf;
1784
gen_opc_instr_start[lj++] = 0;
1786
tb->size = dc->pc - pc_start;
1787
tb->icount = num_insns;
1792
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1795
log_target_disas(pc_start, dc->pc - pc_start, 0);
1797
qemu_log("\nisize=%d osize=%td\n",
1798
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1802
assert(!dc->abort_at_next_insn);
1805
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1807
gen_intermediate_code_internal(env, tb, 0);
1810
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1812
gen_intermediate_code_internal(env, tb, 1);
1815
void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1823
cpu_fprintf(f, "IN: PC=%x %s\n",
1824
env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1825
cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1826
env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1827
env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1828
cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1829
env->btaken, env->btarget,
1830
(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1831
(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1832
(env->sregs[SR_MSR] & MSR_EIP),
1833
(env->sregs[SR_MSR] & MSR_IE));
1835
for (i = 0; i < 32; i++) {
1836
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1837
if ((i + 1) % 4 == 0)
1838
cpu_fprintf(f, "\n");
1840
cpu_fprintf(f, "\n\n");
1843
CPUState *cpu_mb_init (const char *cpu_model)
1846
static int tcg_initialized = 0;
1849
env = qemu_mallocz(sizeof(CPUState));
1853
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1855
if (tcg_initialized)
1858
tcg_initialized = 1;
1860
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1862
env_debug = tcg_global_mem_new(TCG_AREG0,
1863
offsetof(CPUState, debug),
1865
env_iflags = tcg_global_mem_new(TCG_AREG0,
1866
offsetof(CPUState, iflags),
1868
env_imm = tcg_global_mem_new(TCG_AREG0,
1869
offsetof(CPUState, imm),
1871
env_btarget = tcg_global_mem_new(TCG_AREG0,
1872
offsetof(CPUState, btarget),
1874
env_btaken = tcg_global_mem_new(TCG_AREG0,
1875
offsetof(CPUState, btaken),
1877
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1878
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1879
offsetof(CPUState, regs[i]),
1882
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1883
cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1884
offsetof(CPUState, sregs[i]),
1885
special_regnames[i]);
1887
#define GEN_HELPER 2
1893
void cpu_reset (CPUState *env)
1895
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1896
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1897
log_cpu_state(env, 0);
1900
memset(env, 0, offsetof(CPUMBState, breakpoints));
1903
env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1904
| PVR0_USE_BARREL_MASK \
1905
| PVR0_USE_DIV_MASK \
1906
| PVR0_USE_HW_MUL_MASK \
1907
| PVR0_USE_EXC_MASK \
1908
| PVR0_USE_ICACHE_MASK \
1909
| PVR0_USE_DCACHE_MASK \
1912
env->pvr.regs[2] = PVR2_D_OPB_MASK \
1916
| PVR2_USE_MSR_INSTR \
1917
| PVR2_USE_PCMP_INSTR \
1918
| PVR2_USE_BARREL_MASK \
1919
| PVR2_USE_DIV_MASK \
1920
| PVR2_USE_HW_MUL_MASK \
1921
| PVR2_USE_MUL64_MASK \
1922
| PVR2_USE_FPU_MASK \
1923
| PVR2_USE_FPU2_MASK \
1924
| PVR2_FPU_EXC_MASK \
1926
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1927
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1929
#if defined(CONFIG_USER_ONLY)
1930
/* start in user mode with interrupts enabled. */
1931
env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
1932
env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1934
env->sregs[SR_MSR] = 0;
1935
mmu_init(&env->mmu);
1937
env->mmu.c_mmu_tlb_access = 3;
1938
env->mmu.c_mmu_zones = 16;
1942
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
1944
env->sregs[SR_PC] = gen_opc_pc[pc_pos];