2
* QEMU USB OHCI Emulation
3
* Copyright (c) 2004 Gianni Tedesco
4
* Copyright (c) 2006 CodeSourcery
5
* Copyright (c) 2006 Openedhand Ltd.
7
* This library is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU Lesser General Public
9
* License as published by the Free Software Foundation; either
10
* version 2 of the License, or (at your option) any later version.
12
* This library is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15
* Lesser General Public License for more details.
17
* You should have received a copy of the GNU Lesser General Public
18
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
21
* o Isochronous transfers
22
* o Allocate bandwidth in frames properly
23
* o Disable timers when nothing needs to be done, or remove timer usage
25
* o Handle unrecoverable errors properly
26
* o BIOS work to boot from USB storage
30
#include "qemu-timer.h"
35
#include "qdev-addr.h"
38
/* Dump packet contents. */
39
//#define DEBUG_PACKET
41
/* This causes frames to occur 1000x slower */
42
//#define OHCI_TIME_WARP 1
45
#define DPRINTF printf
50
/* Number of Downstream Ports on the root hub. */
52
#define OHCI_MAX_PORTS 15
54
static int64_t usb_frame_time;
55
static int64_t usb_bit_time;
57
typedef struct OHCIPort {
73
/* Control partition */
78
/* memory pointer partition */
80
uint32_t ctrl_head, ctrl_cur;
81
uint32_t bulk_head, bulk_cur;
86
/* Frame counter partition */
91
uint16_t frame_number;
96
/* Root Hub partition */
97
uint32_t rhdesc_a, rhdesc_b;
99
OHCIPort rhport[OHCI_MAX_PORTS];
101
/* PXA27x Non-OHCI events */
107
/* SM501 local memory offset */
108
target_phys_addr_t localmem_base;
110
/* Active packets. */
112
USBPacket usb_packet;
113
uint8_t usb_buf[8192];
119
/* Host Controller Communications Area */
126
static void ohci_bus_stop(OHCIState *ohci);
127
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
129
/* Bitfields for the first word of an Endpoint Desciptor. */
130
#define OHCI_ED_FA_SHIFT 0
131
#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
132
#define OHCI_ED_EN_SHIFT 7
133
#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
134
#define OHCI_ED_D_SHIFT 11
135
#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
136
#define OHCI_ED_S (1<<13)
137
#define OHCI_ED_K (1<<14)
138
#define OHCI_ED_F (1<<15)
139
#define OHCI_ED_MPS_SHIFT 16
140
#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
142
/* Flags in the head field of an Endpoint Desciptor. */
146
/* Bitfields for the first word of a Transfer Desciptor. */
147
#define OHCI_TD_R (1<<18)
148
#define OHCI_TD_DP_SHIFT 19
149
#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
150
#define OHCI_TD_DI_SHIFT 21
151
#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
152
#define OHCI_TD_T0 (1<<24)
153
#define OHCI_TD_T1 (1<<24)
154
#define OHCI_TD_EC_SHIFT 26
155
#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
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#define OHCI_TD_CC_SHIFT 28
157
#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
159
/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
160
/* CC & DI - same as in the General Transfer Desciptor */
161
#define OHCI_TD_SF_SHIFT 0
162
#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
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#define OHCI_TD_FC_SHIFT 24
164
#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
166
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
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#define OHCI_TD_PSW_CC_SHIFT 12
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#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
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#define OHCI_TD_PSW_SIZE_SHIFT 0
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#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
172
#define OHCI_PAGE_MASK 0xfffff000
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#define OHCI_OFFSET_MASK 0xfff
175
#define OHCI_DPTR_MASK 0xfffffff0
177
#define OHCI_BM(val, field) \
178
(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
180
#define OHCI_SET_BM(val, field, newval) do { \
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val &= ~OHCI_##field##_MASK; \
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
185
/* endpoint descriptor */
193
/* General transfer descriptor */
201
/* Isochronous transfer descriptor */
210
#define USB_HZ 12000000
212
/* OHCI Local stuff */
213
#define OHCI_CTL_CBSR ((1<<0)|(1<<1))
214
#define OHCI_CTL_PLE (1<<2)
215
#define OHCI_CTL_IE (1<<3)
216
#define OHCI_CTL_CLE (1<<4)
217
#define OHCI_CTL_BLE (1<<5)
218
#define OHCI_CTL_HCFS ((1<<6)|(1<<7))
219
#define OHCI_USB_RESET 0x00
220
#define OHCI_USB_RESUME 0x40
221
#define OHCI_USB_OPERATIONAL 0x80
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#define OHCI_USB_SUSPEND 0xc0
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#define OHCI_CTL_IR (1<<8)
224
#define OHCI_CTL_RWC (1<<9)
225
#define OHCI_CTL_RWE (1<<10)
227
#define OHCI_STATUS_HCR (1<<0)
228
#define OHCI_STATUS_CLF (1<<1)
229
#define OHCI_STATUS_BLF (1<<2)
230
#define OHCI_STATUS_OCR (1<<3)
231
#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
233
#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
234
#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
235
#define OHCI_INTR_SF (1<<2) /* Start of frame */
236
#define OHCI_INTR_RD (1<<3) /* Resume detect */
237
#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
238
#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
239
#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
240
#define OHCI_INTR_OC (1<<30) /* Ownership change */
241
#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
243
#define OHCI_HCCA_SIZE 0x100
244
#define OHCI_HCCA_MASK 0xffffff00
246
#define OHCI_EDPTR_MASK 0xfffffff0
248
#define OHCI_FMI_FI 0x00003fff
249
#define OHCI_FMI_FSMPS 0xffff0000
250
#define OHCI_FMI_FIT 0x80000000
252
#define OHCI_FR_RT (1<<31)
254
#define OHCI_LS_THRESH 0x628
256
#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
257
#define OHCI_RHA_PSM (1<<8)
258
#define OHCI_RHA_NPS (1<<9)
259
#define OHCI_RHA_DT (1<<10)
260
#define OHCI_RHA_OCPM (1<<11)
261
#define OHCI_RHA_NOCP (1<<12)
262
#define OHCI_RHA_POTPGT_MASK 0xff000000
264
#define OHCI_RHS_LPS (1<<0)
265
#define OHCI_RHS_OCI (1<<1)
266
#define OHCI_RHS_DRWE (1<<15)
267
#define OHCI_RHS_LPSC (1<<16)
268
#define OHCI_RHS_OCIC (1<<17)
269
#define OHCI_RHS_CRWE (1<<31)
271
#define OHCI_PORT_CCS (1<<0)
272
#define OHCI_PORT_PES (1<<1)
273
#define OHCI_PORT_PSS (1<<2)
274
#define OHCI_PORT_POCI (1<<3)
275
#define OHCI_PORT_PRS (1<<4)
276
#define OHCI_PORT_PPS (1<<8)
277
#define OHCI_PORT_LSDA (1<<9)
278
#define OHCI_PORT_CSC (1<<16)
279
#define OHCI_PORT_PESC (1<<17)
280
#define OHCI_PORT_PSSC (1<<18)
281
#define OHCI_PORT_OCIC (1<<19)
282
#define OHCI_PORT_PRSC (1<<20)
283
#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
284
|OHCI_PORT_OCIC|OHCI_PORT_PRSC)
286
#define OHCI_TD_DIR_SETUP 0x0
287
#define OHCI_TD_DIR_OUT 0x1
288
#define OHCI_TD_DIR_IN 0x2
289
#define OHCI_TD_DIR_RESERVED 0x3
291
#define OHCI_CC_NOERROR 0x0
292
#define OHCI_CC_CRC 0x1
293
#define OHCI_CC_BITSTUFFING 0x2
294
#define OHCI_CC_DATATOGGLEMISMATCH 0x3
295
#define OHCI_CC_STALL 0x4
296
#define OHCI_CC_DEVICENOTRESPONDING 0x5
297
#define OHCI_CC_PIDCHECKFAILURE 0x6
298
#define OHCI_CC_UNDEXPETEDPID 0x7
299
#define OHCI_CC_DATAOVERRUN 0x8
300
#define OHCI_CC_DATAUNDERRUN 0x9
301
#define OHCI_CC_BUFFEROVERRUN 0xc
302
#define OHCI_CC_BUFFERUNDERRUN 0xd
304
#define OHCI_HRESET_FSBIR (1 << 0)
306
/* Update IRQ levels */
307
static inline void ohci_intr_update(OHCIState *ohci)
311
if ((ohci->intr & OHCI_INTR_MIE) &&
312
(ohci->intr_status & ohci->intr))
315
qemu_set_irq(ohci->irq, level);
318
/* Set an interrupt */
319
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
321
ohci->intr_status |= intr;
322
ohci_intr_update(ohci);
325
/* Attach or detach a device on a root hub port. */
326
static void ohci_attach(USBPort *port1)
328
OHCIState *s = port1->opaque;
329
OHCIPort *port = &s->rhport[port1->index];
330
uint32_t old_state = port->ctrl;
332
/* set connect status */
333
port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
336
if (port->port.dev->speed == USB_SPEED_LOW) {
337
port->ctrl |= OHCI_PORT_LSDA;
339
port->ctrl &= ~OHCI_PORT_LSDA;
342
/* notify of remote-wakeup */
343
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
344
ohci_set_interrupt(s, OHCI_INTR_RD);
347
DPRINTF("usb-ohci: Attached port %d\n", port1->index);
349
if (old_state != port->ctrl) {
350
ohci_set_interrupt(s, OHCI_INTR_RHSC);
354
static void ohci_detach(USBPort *port1)
356
OHCIState *s = port1->opaque;
357
OHCIPort *port = &s->rhport[port1->index];
358
uint32_t old_state = port->ctrl;
360
ohci_async_cancel_device(s, port1->dev);
362
/* set connect status */
363
if (port->ctrl & OHCI_PORT_CCS) {
364
port->ctrl &= ~OHCI_PORT_CCS;
365
port->ctrl |= OHCI_PORT_CSC;
368
if (port->ctrl & OHCI_PORT_PES) {
369
port->ctrl &= ~OHCI_PORT_PES;
370
port->ctrl |= OHCI_PORT_PESC;
372
DPRINTF("usb-ohci: Detached port %d\n", port1->index);
374
if (old_state != port->ctrl) {
375
ohci_set_interrupt(s, OHCI_INTR_RHSC);
379
static void ohci_wakeup(USBPort *port1)
381
OHCIState *s = port1->opaque;
382
OHCIPort *port = &s->rhport[port1->index];
384
if (port->ctrl & OHCI_PORT_PSS) {
385
DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
386
port->ctrl |= OHCI_PORT_PSSC;
387
port->ctrl &= ~OHCI_PORT_PSS;
388
intr = OHCI_INTR_RHSC;
390
/* Note that the controller can be suspended even if this port is not */
391
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
392
DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
393
/* This is the one state transition the controller can do by itself */
394
s->ctl &= ~OHCI_CTL_HCFS;
395
s->ctl |= OHCI_USB_RESUME;
396
/* In suspend mode only ResumeDetected is possible, not RHSC:
397
* see the OHCI spec 5.1.2.3.
401
ohci_set_interrupt(s, intr);
404
static void ohci_child_detach(USBPort *port1, USBDevice *child)
406
OHCIState *s = port1->opaque;
408
ohci_async_cancel_device(s, child);
411
/* Reset the controller */
412
static void ohci_reset(void *opaque)
414
OHCIState *ohci = opaque;
422
ohci->intr_status = 0;
423
ohci->intr = OHCI_INTR_MIE;
426
ohci->ctrl_head = ohci->ctrl_cur = 0;
427
ohci->bulk_head = ohci->bulk_cur = 0;
430
ohci->done_count = 7;
432
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
433
* I took the value linux sets ...
435
ohci->fsmps = 0x2778;
439
ohci->frame_number = 0;
441
ohci->lst = OHCI_LS_THRESH;
443
ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
444
ohci->rhdesc_b = 0x0; /* Impl. specific */
447
for (i = 0; i < ohci->num_ports; i++)
449
port = &ohci->rhport[i];
451
if (port->port.dev) {
452
usb_attach(&port->port, port->port.dev);
455
if (ohci->async_td) {
456
usb_cancel_packet(&ohci->usb_packet);
459
DPRINTF("usb-ohci: Reset %s\n", ohci->name);
462
/* Get an array of dwords from main memory */
463
static inline int get_dwords(OHCIState *ohci,
464
uint32_t addr, uint32_t *buf, int num)
468
addr += ohci->localmem_base;
470
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
471
cpu_physical_memory_read(addr, buf, sizeof(*buf));
472
*buf = le32_to_cpu(*buf);
478
/* Put an array of dwords in to main memory */
479
static inline int put_dwords(OHCIState *ohci,
480
uint32_t addr, uint32_t *buf, int num)
484
addr += ohci->localmem_base;
486
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
487
uint32_t tmp = cpu_to_le32(*buf);
488
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
494
/* Get an array of words from main memory */
495
static inline int get_words(OHCIState *ohci,
496
uint32_t addr, uint16_t *buf, int num)
500
addr += ohci->localmem_base;
502
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
503
cpu_physical_memory_read(addr, buf, sizeof(*buf));
504
*buf = le16_to_cpu(*buf);
510
/* Put an array of words in to main memory */
511
static inline int put_words(OHCIState *ohci,
512
uint32_t addr, uint16_t *buf, int num)
516
addr += ohci->localmem_base;
518
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
519
uint16_t tmp = cpu_to_le16(*buf);
520
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
526
static inline int ohci_read_ed(OHCIState *ohci,
527
uint32_t addr, struct ohci_ed *ed)
529
return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
532
static inline int ohci_read_td(OHCIState *ohci,
533
uint32_t addr, struct ohci_td *td)
535
return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
538
static inline int ohci_read_iso_td(OHCIState *ohci,
539
uint32_t addr, struct ohci_iso_td *td)
541
return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
542
get_words(ohci, addr + 16, td->offset, 8));
545
static inline int ohci_read_hcca(OHCIState *ohci,
546
uint32_t addr, struct ohci_hcca *hcca)
548
cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
552
static inline int ohci_put_ed(OHCIState *ohci,
553
uint32_t addr, struct ohci_ed *ed)
555
return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
558
static inline int ohci_put_td(OHCIState *ohci,
559
uint32_t addr, struct ohci_td *td)
561
return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
564
static inline int ohci_put_iso_td(OHCIState *ohci,
565
uint32_t addr, struct ohci_iso_td *td)
567
return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
568
put_words(ohci, addr + 16, td->offset, 8));
571
static inline int ohci_put_hcca(OHCIState *ohci,
572
uint32_t addr, struct ohci_hcca *hcca)
574
cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
578
/* Read/Write the contents of a TD from/to main memory. */
579
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
580
uint8_t *buf, int len, int write)
586
n = 0x1000 - (ptr & 0xfff);
589
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
592
ptr = td->be & ~0xfffu;
594
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
597
/* Read/Write the contents of an ISO TD from/to main memory. */
598
static void ohci_copy_iso_td(OHCIState *ohci,
599
uint32_t start_addr, uint32_t end_addr,
600
uint8_t *buf, int len, int write)
606
n = 0x1000 - (ptr & 0xfff);
609
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
612
ptr = end_addr & ~0xfffu;
614
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
617
static void ohci_process_lists(OHCIState *ohci, int completion);
619
static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
621
OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
623
DPRINTF("Async packet complete\n");
625
ohci->async_complete = 1;
626
ohci_process_lists(ohci, 1);
629
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
631
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
637
const char *str = NULL;
643
struct ohci_iso_td iso_td;
645
uint16_t starting_frame;
646
int16_t relative_frame_number;
648
uint32_t start_offset, next_offset, end_offset = 0;
649
uint32_t start_addr, end_addr;
651
addr = ed->head & OHCI_DPTR_MASK;
653
if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
654
printf("usb-ohci: ISO_TD read error at %x\n", addr);
658
starting_frame = OHCI_BM(iso_td.flags, TD_SF);
659
frame_count = OHCI_BM(iso_td.flags, TD_FC);
660
relative_frame_number = USUB(ohci->frame_number, starting_frame);
663
printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
664
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
665
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
666
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
667
"frame_number 0x%.8x starting_frame 0x%.8x\n"
668
"frame_count 0x%.8x relative %d\n"
669
"di 0x%.8x cc 0x%.8x\n",
670
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
671
iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
672
iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
673
iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
674
ohci->frame_number, starting_frame,
675
frame_count, relative_frame_number,
676
OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
679
if (relative_frame_number < 0) {
680
DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
682
} else if (relative_frame_number > frame_count) {
683
/* ISO TD expired - retire the TD to the Done Queue and continue with
684
the next ISO TD of the same ED */
685
DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
687
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
688
ed->head &= ~OHCI_DPTR_MASK;
689
ed->head |= (iso_td.next & OHCI_DPTR_MASK);
690
iso_td.next = ohci->done;
692
i = OHCI_BM(iso_td.flags, TD_DI);
693
if (i < ohci->done_count)
694
ohci->done_count = i;
695
ohci_put_iso_td(ohci, addr, &iso_td);
699
dir = OHCI_BM(ed->flags, ED_D);
707
case OHCI_TD_DIR_OUT:
713
case OHCI_TD_DIR_SETUP:
717
pid = USB_TOKEN_SETUP;
720
printf("usb-ohci: Bad direction %d\n", dir);
724
if (!iso_td.bp || !iso_td.be) {
725
printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
729
start_offset = iso_td.offset[relative_frame_number];
730
next_offset = iso_td.offset[relative_frame_number + 1];
732
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
733
((relative_frame_number < frame_count) &&
734
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
735
printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
736
start_offset, next_offset);
740
if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
741
printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
742
start_offset, next_offset);
746
if ((start_offset & 0x1000) == 0) {
747
start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
748
(start_offset & OHCI_OFFSET_MASK);
750
start_addr = (iso_td.be & OHCI_PAGE_MASK) |
751
(start_offset & OHCI_OFFSET_MASK);
754
if (relative_frame_number < frame_count) {
755
end_offset = next_offset - 1;
756
if ((end_offset & 0x1000) == 0) {
757
end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
758
(end_offset & OHCI_OFFSET_MASK);
760
end_addr = (iso_td.be & OHCI_PAGE_MASK) |
761
(end_offset & OHCI_OFFSET_MASK);
764
/* Last packet in the ISO TD */
765
end_addr = iso_td.be;
768
if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
769
len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
770
- (start_addr & OHCI_OFFSET_MASK);
772
len = end_addr - start_addr + 1;
775
if (len && dir != OHCI_TD_DIR_IN) {
776
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
780
ret = ohci->usb_packet.len;
783
for (i = 0; i < ohci->num_ports; i++) {
784
dev = ohci->rhport[i].port.dev;
785
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
787
ohci->usb_packet.pid = pid;
788
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
789
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
790
ohci->usb_packet.data = ohci->usb_buf;
791
ohci->usb_packet.len = len;
792
ret = usb_handle_packet(dev, &ohci->usb_packet);
793
if (ret != USB_RET_NODEV)
797
if (ret == USB_RET_ASYNC) {
803
printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
804
start_offset, end_offset, start_addr, end_addr, str, len, ret);
808
if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
809
/* IN transfer succeeded */
810
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
811
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
813
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
814
} else if (dir == OHCI_TD_DIR_OUT && ret == len) {
815
/* OUT transfer succeeded */
816
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
818
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
820
if (ret > (ssize_t) len) {
821
printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
822
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
823
OHCI_CC_DATAOVERRUN);
824
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
826
} else if (ret >= 0) {
827
printf("usb-ohci: DataUnderrun %d\n", ret);
828
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
829
OHCI_CC_DATAUNDERRUN);
833
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
834
OHCI_CC_DEVICENOTRESPONDING);
835
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
840
printf("usb-ohci: got NAK/STALL %d\n", ret);
841
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
843
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
847
printf("usb-ohci: Bad device response %d\n", ret);
848
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
849
OHCI_CC_UNDEXPETEDPID);
855
if (relative_frame_number == frame_count) {
856
/* Last data packet of ISO TD - retire the TD to the Done Queue */
857
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
858
ed->head &= ~OHCI_DPTR_MASK;
859
ed->head |= (iso_td.next & OHCI_DPTR_MASK);
860
iso_td.next = ohci->done;
862
i = OHCI_BM(iso_td.flags, TD_DI);
863
if (i < ohci->done_count)
864
ohci->done_count = i;
866
ohci_put_iso_td(ohci, addr, &iso_td);
870
/* Service a transport descriptor.
871
Returns nonzero to terminate processing of this endpoint. */
873
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
878
const char *str = NULL;
889
addr = ed->head & OHCI_DPTR_MASK;
890
/* See if this TD has already been submitted to the device. */
891
completion = (addr == ohci->async_td);
892
if (completion && !ohci->async_complete) {
894
DPRINTF("Skipping async TD\n");
898
if (!ohci_read_td(ohci, addr, &td)) {
899
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
903
dir = OHCI_BM(ed->flags, ED_D);
905
case OHCI_TD_DIR_OUT:
910
dir = OHCI_BM(td.flags, TD_DP);
921
case OHCI_TD_DIR_OUT:
927
case OHCI_TD_DIR_SETUP:
931
pid = USB_TOKEN_SETUP;
934
fprintf(stderr, "usb-ohci: Bad direction\n");
937
if (td.cbp && td.be) {
938
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
939
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
941
len = (td.be - td.cbp) + 1;
944
if (len && dir != OHCI_TD_DIR_IN && !completion) {
945
ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
949
flag_r = (td.flags & OHCI_TD_R) != 0;
951
DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
952
addr, (int64_t)len, str, flag_r, td.cbp, td.be);
954
if (len > 0 && dir != OHCI_TD_DIR_IN) {
956
for (i = 0; i < len; i++)
957
printf(" %.2x", ohci->usb_buf[i]);
962
ret = ohci->usb_packet.len;
964
ohci->async_complete = 0;
967
for (i = 0; i < ohci->num_ports; i++) {
968
dev = ohci->rhport[i].port.dev;
969
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
972
if (ohci->async_td) {
973
/* ??? The hardware should allow one active packet per
974
endpoint. We only allow one active packet per controller.
975
This should be sufficient as long as devices respond in a
979
DPRINTF("Too many pending packets\n");
983
ohci->usb_packet.pid = pid;
984
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
985
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
986
ohci->usb_packet.data = ohci->usb_buf;
987
ohci->usb_packet.len = len;
988
ret = usb_handle_packet(dev, &ohci->usb_packet);
989
if (ret != USB_RET_NODEV)
993
DPRINTF("ret=%d\n", ret);
995
if (ret == USB_RET_ASYNC) {
996
ohci->async_td = addr;
1001
if (dir == OHCI_TD_DIR_IN) {
1002
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
1005
for (i = 0; i < ret; i++)
1006
printf(" %.2x", ohci->usb_buf[i]);
1015
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1016
/* Transmission succeeded. */
1021
if ((td.cbp & 0xfff) + ret > 0xfff) {
1023
td.cbp |= td.be & ~0xfff;
1026
td.flags |= OHCI_TD_T1;
1027
td.flags ^= OHCI_TD_T0;
1028
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1029
OHCI_SET_BM(td.flags, TD_EC, 0);
1031
ed->head &= ~OHCI_ED_C;
1032
if (td.flags & OHCI_TD_T0)
1033
ed->head |= OHCI_ED_C;
1036
DPRINTF("usb-ohci: Underrun\n");
1037
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1041
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1043
DPRINTF("usb-ohci: got NAK\n");
1046
DPRINTF("usb-ohci: got STALL\n");
1047
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1049
case USB_RET_BABBLE:
1050
DPRINTF("usb-ohci: got BABBLE\n");
1051
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1054
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1055
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1056
OHCI_SET_BM(td.flags, TD_EC, 3);
1060
ed->head |= OHCI_ED_H;
1063
/* Retire this TD */
1064
ed->head &= ~OHCI_DPTR_MASK;
1065
ed->head |= td.next & OHCI_DPTR_MASK;
1066
td.next = ohci->done;
1068
i = OHCI_BM(td.flags, TD_DI);
1069
if (i < ohci->done_count)
1070
ohci->done_count = i;
1071
ohci_put_td(ohci, addr, &td);
1072
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1075
/* Service an endpoint list. Returns nonzero if active TD were found. */
1076
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1088
for (cur = head; cur; cur = next_ed) {
1089
if (!ohci_read_ed(ohci, cur, &ed)) {
1090
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1094
next_ed = ed.next & OHCI_DPTR_MASK;
1096
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1098
/* Cancel pending packets for ED that have been paused. */
1099
addr = ed.head & OHCI_DPTR_MASK;
1100
if (ohci->async_td && addr == ohci->async_td) {
1101
usb_cancel_packet(&ohci->usb_packet);
1107
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1109
DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1110
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1111
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1112
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1113
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1114
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1115
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1116
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1120
if ((ed.flags & OHCI_ED_F) == 0) {
1121
if (ohci_service_td(ohci, &ed))
1124
/* Handle isochronous endpoints */
1125
if (ohci_service_iso_td(ohci, &ed, completion))
1130
ohci_put_ed(ohci, cur, &ed);
1136
/* Generate a SOF event, and set a timer for EOF */
1137
static void ohci_sof(OHCIState *ohci)
1139
ohci->sof_time = qemu_get_clock_ns(vm_clock);
1140
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1141
ohci_set_interrupt(ohci, OHCI_INTR_SF);
1144
/* Process Control and Bulk lists. */
1145
static void ohci_process_lists(OHCIState *ohci, int completion)
1147
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1148
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1149
DPRINTF("usb-ohci: head %x, cur %x\n",
1150
ohci->ctrl_head, ohci->ctrl_cur);
1152
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1154
ohci->status &= ~OHCI_STATUS_CLF;
1158
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1159
if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1161
ohci->status &= ~OHCI_STATUS_BLF;
1166
/* Do frame processing on frame boundary */
1167
static void ohci_frame_boundary(void *opaque)
1169
OHCIState *ohci = opaque;
1170
struct ohci_hcca hcca;
1172
ohci_read_hcca(ohci, ohci->hcca, &hcca);
1174
/* Process all the lists at the end of the frame */
1175
if (ohci->ctl & OHCI_CTL_PLE) {
1178
n = ohci->frame_number & 0x1f;
1179
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1182
/* Cancel all pending packets if either of the lists has been disabled. */
1183
if (ohci->async_td &&
1184
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1185
usb_cancel_packet(&ohci->usb_packet);
1188
ohci->old_ctl = ohci->ctl;
1189
ohci_process_lists(ohci, 0);
1191
/* Frame boundary, so do EOF stuf here */
1192
ohci->frt = ohci->fit;
1194
/* Increment frame number and take care of endianness. */
1195
ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1196
hcca.frame = cpu_to_le16(ohci->frame_number);
1198
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1201
if (ohci->intr & ohci->intr_status)
1203
hcca.done = cpu_to_le32(ohci->done);
1205
ohci->done_count = 7;
1206
ohci_set_interrupt(ohci, OHCI_INTR_WD);
1209
if (ohci->done_count != 7 && ohci->done_count != 0)
1212
/* Do SOF stuff here */
1215
/* Writeback HCCA */
1216
ohci_put_hcca(ohci, ohci->hcca, &hcca);
1219
/* Start sending SOF tokens across the USB bus, lists are processed in
1222
static int ohci_bus_start(OHCIState *ohci)
1224
ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1225
ohci_frame_boundary,
1228
if (ohci->eof_timer == NULL) {
1229
fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1230
/* TODO: Signal unrecoverable error */
1234
DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1241
/* Stop sending SOF tokens on the bus */
1242
static void ohci_bus_stop(OHCIState *ohci)
1244
if (ohci->eof_timer)
1245
qemu_del_timer(ohci->eof_timer);
1246
ohci->eof_timer = NULL;
1249
/* Sets a flag in a port status register but only set it if the port is
1250
* connected, if not set ConnectStatusChange flag. If flag is enabled
1253
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1257
/* writing a 0 has no effect */
1261
/* If CurrentConnectStatus is cleared we set
1262
* ConnectStatusChange
1264
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1265
ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1266
if (ohci->rhstatus & OHCI_RHS_DRWE) {
1267
/* TODO: CSC is a wakeup event */
1272
if (ohci->rhport[i].ctrl & val)
1276
ohci->rhport[i].ctrl |= val;
1281
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1282
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1286
if (val != ohci->fi) {
1287
DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1288
ohci->name, ohci->fi, ohci->fi);
1294
static void ohci_port_power(OHCIState *ohci, int i, int p)
1297
ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1299
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1306
/* Set HcControlRegister */
1307
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1312
old_state = ohci->ctl & OHCI_CTL_HCFS;
1314
new_state = ohci->ctl & OHCI_CTL_HCFS;
1316
/* no state change */
1317
if (old_state == new_state)
1320
switch (new_state) {
1321
case OHCI_USB_OPERATIONAL:
1322
ohci_bus_start(ohci);
1324
case OHCI_USB_SUSPEND:
1325
ohci_bus_stop(ohci);
1326
DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1328
case OHCI_USB_RESUME:
1329
DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1331
case OHCI_USB_RESET:
1333
DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1338
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1343
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1344
return (ohci->frt << 31);
1346
/* Being in USB operational state guarnatees sof_time was
1349
tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1351
/* avoid muldiv if possible */
1352
if (tks >= usb_frame_time)
1353
return (ohci->frt << 31);
1355
tks = muldiv64(1, tks, usb_bit_time);
1356
fr = (uint16_t)(ohci->fi - tks);
1358
return (ohci->frt << 31) | fr;
1362
/* Set root hub status */
1363
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1367
old_state = ohci->rhstatus;
1369
/* write 1 to clear OCIC */
1370
if (val & OHCI_RHS_OCIC)
1371
ohci->rhstatus &= ~OHCI_RHS_OCIC;
1373
if (val & OHCI_RHS_LPS) {
1376
for (i = 0; i < ohci->num_ports; i++)
1377
ohci_port_power(ohci, i, 0);
1378
DPRINTF("usb-ohci: powered down all ports\n");
1381
if (val & OHCI_RHS_LPSC) {
1384
for (i = 0; i < ohci->num_ports; i++)
1385
ohci_port_power(ohci, i, 1);
1386
DPRINTF("usb-ohci: powered up all ports\n");
1389
if (val & OHCI_RHS_DRWE)
1390
ohci->rhstatus |= OHCI_RHS_DRWE;
1392
if (val & OHCI_RHS_CRWE)
1393
ohci->rhstatus &= ~OHCI_RHS_DRWE;
1395
if (old_state != ohci->rhstatus)
1396
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1399
/* Set root hub port status */
1400
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1405
port = &ohci->rhport[portnum];
1406
old_state = port->ctrl;
1408
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1409
if (val & OHCI_PORT_WTC)
1410
port->ctrl &= ~(val & OHCI_PORT_WTC);
1412
if (val & OHCI_PORT_CCS)
1413
port->ctrl &= ~OHCI_PORT_PES;
1415
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1417
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1418
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1421
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1422
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1423
usb_send_msg(port->port.dev, USB_MSG_RESET);
1424
port->ctrl &= ~OHCI_PORT_PRS;
1425
/* ??? Should this also set OHCI_PORT_PESC. */
1426
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1429
/* Invert order here to ensure in ambiguous case, device is
1432
if (val & OHCI_PORT_LSDA)
1433
ohci_port_power(ohci, portnum, 0);
1434
if (val & OHCI_PORT_PPS)
1435
ohci_port_power(ohci, portnum, 1);
1437
if (old_state != port->ctrl)
1438
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1443
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1445
OHCIState *ohci = ptr;
1450
/* Only aligned reads are allowed on OHCI */
1452
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1454
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1455
/* HcRhPortStatus */
1456
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1458
switch (addr >> 2) {
1459
case 0: /* HcRevision */
1463
case 1: /* HcControl */
1467
case 2: /* HcCommandStatus */
1468
retval = ohci->status;
1471
case 3: /* HcInterruptStatus */
1472
retval = ohci->intr_status;
1475
case 4: /* HcInterruptEnable */
1476
case 5: /* HcInterruptDisable */
1477
retval = ohci->intr;
1480
case 6: /* HcHCCA */
1481
retval = ohci->hcca;
1484
case 7: /* HcPeriodCurrentED */
1485
retval = ohci->per_cur;
1488
case 8: /* HcControlHeadED */
1489
retval = ohci->ctrl_head;
1492
case 9: /* HcControlCurrentED */
1493
retval = ohci->ctrl_cur;
1496
case 10: /* HcBulkHeadED */
1497
retval = ohci->bulk_head;
1500
case 11: /* HcBulkCurrentED */
1501
retval = ohci->bulk_cur;
1504
case 12: /* HcDoneHead */
1505
retval = ohci->done;
1508
case 13: /* HcFmInterretval */
1509
retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1512
case 14: /* HcFmRemaining */
1513
retval = ohci_get_frame_remaining(ohci);
1516
case 15: /* HcFmNumber */
1517
retval = ohci->frame_number;
1520
case 16: /* HcPeriodicStart */
1521
retval = ohci->pstart;
1524
case 17: /* HcLSThreshold */
1528
case 18: /* HcRhDescriptorA */
1529
retval = ohci->rhdesc_a;
1532
case 19: /* HcRhDescriptorB */
1533
retval = ohci->rhdesc_b;
1536
case 20: /* HcRhStatus */
1537
retval = ohci->rhstatus;
1540
/* PXA27x specific registers */
1541
case 24: /* HcStatus */
1542
retval = ohci->hstatus & ohci->hmask;
1545
case 25: /* HcHReset */
1546
retval = ohci->hreset;
1549
case 26: /* HcHInterruptEnable */
1550
retval = ohci->hmask;
1553
case 27: /* HcHInterruptTest */
1554
retval = ohci->htest;
1558
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1559
retval = 0xffffffff;
1566
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1568
OHCIState *ohci = ptr;
1572
/* Only aligned reads are allowed on OHCI */
1574
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1578
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1579
/* HcRhPortStatus */
1580
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1584
switch (addr >> 2) {
1585
case 1: /* HcControl */
1586
ohci_set_ctl(ohci, val);
1589
case 2: /* HcCommandStatus */
1590
/* SOC is read-only */
1591
val = (val & ~OHCI_STATUS_SOC);
1593
/* Bits written as '0' remain unchanged in the register */
1594
ohci->status |= val;
1596
if (ohci->status & OHCI_STATUS_HCR)
1600
case 3: /* HcInterruptStatus */
1601
ohci->intr_status &= ~val;
1602
ohci_intr_update(ohci);
1605
case 4: /* HcInterruptEnable */
1607
ohci_intr_update(ohci);
1610
case 5: /* HcInterruptDisable */
1612
ohci_intr_update(ohci);
1615
case 6: /* HcHCCA */
1616
ohci->hcca = val & OHCI_HCCA_MASK;
1619
case 7: /* HcPeriodCurrentED */
1620
/* Ignore writes to this read-only register, Linux does them */
1623
case 8: /* HcControlHeadED */
1624
ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1627
case 9: /* HcControlCurrentED */
1628
ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1631
case 10: /* HcBulkHeadED */
1632
ohci->bulk_head = val & OHCI_EDPTR_MASK;
1635
case 11: /* HcBulkCurrentED */
1636
ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1639
case 13: /* HcFmInterval */
1640
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1641
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1642
ohci_set_frame_interval(ohci, val);
1645
case 15: /* HcFmNumber */
1648
case 16: /* HcPeriodicStart */
1649
ohci->pstart = val & 0xffff;
1652
case 17: /* HcLSThreshold */
1653
ohci->lst = val & 0xffff;
1656
case 18: /* HcRhDescriptorA */
1657
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1658
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1661
case 19: /* HcRhDescriptorB */
1664
case 20: /* HcRhStatus */
1665
ohci_set_hub_status(ohci, val);
1668
/* PXA27x specific registers */
1669
case 24: /* HcStatus */
1670
ohci->hstatus &= ~(val & ohci->hmask);
1672
case 25: /* HcHReset */
1673
ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1674
if (val & OHCI_HRESET_FSBIR)
1678
case 26: /* HcHInterruptEnable */
1682
case 27: /* HcHInterruptTest */
1687
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1692
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
1694
if (ohci->async_td && ohci->usb_packet.owner == dev) {
1695
usb_cancel_packet(&ohci->usb_packet);
1700
/* Only dword reads are defined on OHCI register space */
1701
static CPUReadMemoryFunc * const ohci_readfn[3]={
1707
/* Only dword writes are defined on OHCI register space */
1708
static CPUWriteMemoryFunc * const ohci_writefn[3]={
1714
static USBPortOps ohci_port_ops = {
1715
.attach = ohci_attach,
1716
.detach = ohci_detach,
1717
.child_detach = ohci_child_detach,
1718
.wakeup = ohci_wakeup,
1719
.complete = ohci_async_complete_packet,
1722
static USBBusOps ohci_bus_ops = {
1725
static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1726
int num_ports, uint32_t localmem_base,
1727
char *masterbus, uint32_t firstport)
1731
if (usb_frame_time == 0) {
1732
#ifdef OHCI_TIME_WARP
1733
usb_frame_time = get_ticks_per_sec();
1734
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1736
usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1737
if (get_ticks_per_sec() >= USB_HZ) {
1738
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1743
DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1744
usb_frame_time, usb_bit_time);
1747
ohci->num_ports = num_ports;
1749
USBPort *ports[OHCI_MAX_PORTS];
1750
for(i = 0; i < num_ports; i++) {
1751
ports[i] = &ohci->rhport[i].port;
1753
if (usb_register_companion(masterbus, ports, num_ports,
1754
firstport, ohci, &ohci_port_ops,
1755
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1759
usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1760
for (i = 0; i < num_ports; i++) {
1761
usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1762
ohci, i, &ohci_port_ops,
1763
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1767
ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1768
DEVICE_LITTLE_ENDIAN);
1769
ohci->localmem_base = localmem_base;
1771
ohci->name = dev->info->name;
1774
qemu_register_reset(ohci_reset, ohci);
1787
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1789
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1791
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1792
/* TODO: RST# value should be 0. */
1793
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1795
if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
1796
ohci->masterbus, ohci->firstport) != 0) {
1799
ohci->state.irq = ohci->pci_dev.irq[0];
1801
/* TODO: avoid cast below by using dev */
1802
pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem);
1806
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1808
pci_create_simple(bus, devfn, "pci-ohci");
1812
SysBusDevice busdev;
1815
target_phys_addr_t dma_offset;
1818
static int ohci_init_pxa(SysBusDevice *dev)
1820
OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1822
/* Cannot fail as we pass NULL for masterbus */
1823
usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0);
1824
sysbus_init_irq(dev, &s->ohci.irq);
1825
sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1830
static PCIDeviceInfo ohci_pci_info = {
1831
.qdev.name = "pci-ohci",
1832
.qdev.desc = "Apple USB Controller",
1833
.qdev.size = sizeof(OHCIPCIState),
1834
.init = usb_ohci_initfn_pci,
1835
.vendor_id = PCI_VENDOR_ID_APPLE,
1836
.device_id = PCI_DEVICE_ID_APPLE_IPID_USB,
1837
.class_id = PCI_CLASS_SERIAL_USB,
1838
.qdev.props = (Property[]) {
1839
DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
1840
DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
1841
DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
1842
DEFINE_PROP_END_OF_LIST(),
1846
static SysBusDeviceInfo ohci_sysbus_info = {
1847
.init = ohci_init_pxa,
1848
.qdev.name = "sysbus-ohci",
1849
.qdev.desc = "OHCI USB Controller",
1850
.qdev.size = sizeof(OHCISysBusState),
1851
.qdev.props = (Property[]) {
1852
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1853
DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1854
DEFINE_PROP_END_OF_LIST(),
1858
static void ohci_register(void)
1860
pci_qdev_register(&ohci_pci_info);
1861
sysbus_register_withprop(&ohci_sysbus_info);
1863
device_init(ohci_register);