2
* QEMU Malta board support
4
* Copyright (c) 2006 Aurelien Jarno
6
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
* of this software and associated documentation files (the "Software"), to deal
8
* in the Software without restriction, including without limitation the rights
9
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
* copies of the Software, and to permit persons to whom the Software is
11
* furnished to do so, subject to the following conditions:
13
* The above copyright notice and this permission notice shall be included in
14
* all copies or substantial portions of the Software.
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34
#include "mips_cpudevs.h"
37
#include "vmware_vga.h"
38
#include "qemu-char.h"
40
#include "arch_init.h"
43
#include "mips-bios.h"
47
#include "mc146818rtc.h"
50
//#define DEBUG_BOARD_INIT
52
#define ENVP_ADDR 0x80002000l
53
#define ENVP_NB_ENTRIES 16
54
#define ENVP_ENTRY_SIZE 256
66
CharDriverState *display;
71
static ISADevice *pit;
73
static struct _loaderparams {
75
const char *kernel_filename;
76
const char *kernel_cmdline;
77
const char *initrd_filename;
81
static void malta_fpga_update_display(void *opaque)
85
MaltaFPGAState *s = opaque;
87
for (i = 7 ; i >= 0 ; i--) {
88
if (s->leds & (1 << i))
95
qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
96
qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
100
* EEPROM 24C01 / 24C02 emulation.
102
* Emulation for serial EEPROMs:
103
* 24C01 - 1024 bit (128 x 8)
104
* 24C02 - 2048 bit (256 x 8)
106
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
112
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
114
# define logout(fmt, ...) ((void)0)
117
struct _eeprom24c0x_t {
126
uint8_t contents[256];
129
typedef struct _eeprom24c0x_t eeprom24c0x_t;
131
static eeprom24c0x_t eeprom = {
133
/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
134
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
135
/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
136
/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
137
/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
138
/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
139
/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
140
/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
141
/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
142
/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
143
/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
144
/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
145
/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
146
/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
147
/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
148
/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
152
static uint8_t eeprom24c0x_read(void)
154
logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
155
eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
159
static void eeprom24c0x_write(int scl, int sda)
161
if (eeprom.scl && scl && (eeprom.sda != sda)) {
162
logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
163
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
168
} else if (eeprom.tick == 0 && !eeprom.ack) {
169
/* Waiting for start. */
170
logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
171
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
172
} else if (!eeprom.scl && scl) {
173
logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
174
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
176
logout("\ti2c ack bit = 0\n");
179
} else if (eeprom.sda == sda) {
180
uint8_t bit = (sda != 0);
181
logout("\ti2c bit = %d\n", bit);
182
if (eeprom.tick < 9) {
183
eeprom.command <<= 1;
184
eeprom.command += bit;
186
if (eeprom.tick == 9) {
187
logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
190
} else if (eeprom.tick < 17) {
191
if (eeprom.command & 1) {
192
sda = ((eeprom.data & 0x80) != 0);
194
eeprom.address <<= 1;
195
eeprom.address += bit;
198
if (eeprom.tick == 17) {
199
eeprom.data = eeprom.contents[eeprom.address];
200
logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
204
} else if (eeprom.tick >= 17) {
208
logout("\tsda changed with raising scl\n");
211
logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
217
static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
219
MaltaFPGAState *s = opaque;
223
saddr = (addr & 0xfffff);
227
/* SWITCH Register */
229
val = 0x00000000; /* All switches closed */
232
/* STATUS Register */
234
#ifdef TARGET_WORDS_BIGENDIAN
246
/* LEDBAR Register */
251
/* BRKRES Register */
256
/* UART Registers are handled directly by the serial device */
263
/* XXX: implement a real I2C controller */
267
/* IN = OUT until a real I2C control is implemented */
274
/* I2CINP Register */
276
val = ((s->i2cin & ~1) | eeprom24c0x_read());
284
/* I2COUT Register */
289
/* I2CSEL Register */
296
printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
304
static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
307
MaltaFPGAState *s = opaque;
310
saddr = (addr & 0xfffff);
314
/* SWITCH Register */
322
/* LEDBAR Register */
323
/* XXX: implement a 8-LED array */
325
s->leds = val & 0xff;
328
/* ASCIIWORD Register */
330
snprintf(s->display_text, 9, "%08X", val);
331
malta_fpga_update_display(s);
334
/* ASCIIPOS0 to ASCIIPOS7 Registers */
343
s->display_text[(saddr - 0x00418) >> 3] = (char) val;
344
malta_fpga_update_display(s);
347
/* SOFTRES Register */
350
qemu_system_reset_request ();
353
/* BRKRES Register */
358
/* UART Registers are handled directly by the serial device */
362
s->gpout = val & 0xff;
367
s->i2coe = val & 0x03;
370
/* I2COUT Register */
372
eeprom24c0x_write(val & 0x02, val & 0x01);
376
/* I2CSEL Register */
378
s->i2csel = val & 0x01;
383
printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
390
static CPUReadMemoryFunc * const malta_fpga_read[] = {
396
static CPUWriteMemoryFunc * const malta_fpga_write[] = {
402
static void malta_fpga_reset(void *opaque)
404
MaltaFPGAState *s = opaque;
414
s->display_text[8] = '\0';
415
snprintf(s->display_text, 9, " ");
418
static void malta_fpga_led_init(CharDriverState *chr)
420
qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n");
421
qemu_chr_printf(chr, "+--------+\r\n");
422
qemu_chr_printf(chr, "+ +\r\n");
423
qemu_chr_printf(chr, "+--------+\r\n");
424
qemu_chr_printf(chr, "\n");
425
qemu_chr_printf(chr, "Malta ASCII\r\n");
426
qemu_chr_printf(chr, "+--------+\r\n");
427
qemu_chr_printf(chr, "+ +\r\n");
428
qemu_chr_printf(chr, "+--------+\r\n");
431
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
436
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
438
malta = cpu_register_io_memory(malta_fpga_read,
440
DEVICE_NATIVE_ENDIAN);
442
cpu_register_physical_memory(base, 0x900, malta);
443
/* 0xa00 is less than a page, so will still get the right offsets. */
444
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
446
s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);
448
#ifdef TARGET_WORDS_BIGENDIAN
449
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1);
451
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 0);
455
qemu_register_reset(malta_fpga_reset, s);
460
/* Network support */
461
static void network_init(void)
465
for(i = 0; i < nb_nics; i++) {
466
NICInfo *nd = &nd_table[i];
467
const char *default_devaddr = NULL;
469
if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
470
/* The malta board has a PCNet card using PCI SLOT 11 */
471
default_devaddr = "0b";
473
pci_nic_init_nofail(nd, "pcnet", default_devaddr);
477
/* ROM and pseudo bootloader
479
The following code implements a very very simple bootloader. It first
480
loads the registers a0 to a3 to the values expected by the OS, and
481
then jump at the kernel address.
483
The bootloader should pass the locations of the kernel arguments and
484
environment variables tables. Those tables contain the 32-bit address
485
of NULL terminated strings. The environment variables table should be
486
terminated by a NULL address.
488
For a simpler implementation, the number of kernel arguments is fixed
489
to two (the name of the kernel and the command line), and the two
490
tables are actually the same one.
492
The registers a0 to a3 should contain the following values:
493
a0 - number of kernel arguments
494
a1 - 32-bit address of the kernel arguments table
495
a2 - 32-bit address of the environment variables table
496
a3 - RAM size in bytes
499
static void write_bootloader (CPUState *env, uint8_t *base,
500
int64_t kernel_entry)
504
/* Small bootloader */
505
p = (uint32_t *)base;
506
stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
507
stl_raw(p++, 0x00000000); /* nop */
509
/* YAMON service vector */
510
stl_raw(base + 0x500, 0xbfc00580); /* start: */
511
stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
512
stl_raw(base + 0x520, 0xbfc00580); /* start: */
513
stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
514
stl_raw(base + 0x534, 0xbfc00808); /* print: */
515
stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
516
stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
517
stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
518
stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
519
stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
520
stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
521
stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
522
stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
525
/* Second part of the bootloader */
526
p = (uint32_t *) (base + 0x580);
527
stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
528
stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
529
stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
530
stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
531
stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
532
stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
533
stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
534
stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
535
stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
537
/* Load BAR registers as done by YAMON */
538
stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
540
#ifdef TARGET_WORDS_BIGENDIAN
541
stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
543
stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
545
stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
547
stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
549
#ifdef TARGET_WORDS_BIGENDIAN
550
stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
552
stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
554
stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
555
#ifdef TARGET_WORDS_BIGENDIAN
556
stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
558
stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
560
stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
562
#ifdef TARGET_WORDS_BIGENDIAN
563
stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
565
stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
567
stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
568
#ifdef TARGET_WORDS_BIGENDIAN
569
stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
571
stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
573
stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
575
#ifdef TARGET_WORDS_BIGENDIAN
576
stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
578
stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
580
stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
581
#ifdef TARGET_WORDS_BIGENDIAN
582
stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
584
stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
586
stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
588
/* Jump to kernel code */
589
stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
590
stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
591
stl_raw(p++, 0x03e00008); /* jr ra */
592
stl_raw(p++, 0x00000000); /* nop */
594
/* YAMON subroutines */
595
p = (uint32_t *) (base + 0x800);
596
stl_raw(p++, 0x03e00008); /* jr ra */
597
stl_raw(p++, 0x24020000); /* li v0,0 */
598
/* 808 YAMON print */
599
stl_raw(p++, 0x03e06821); /* move t5,ra */
600
stl_raw(p++, 0x00805821); /* move t3,a0 */
601
stl_raw(p++, 0x00a05021); /* move t2,a1 */
602
stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
603
stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
604
stl_raw(p++, 0x10800005); /* beqz a0,834 */
605
stl_raw(p++, 0x00000000); /* nop */
606
stl_raw(p++, 0x0ff0021c); /* jal 870 */
607
stl_raw(p++, 0x00000000); /* nop */
608
stl_raw(p++, 0x08000205); /* j 814 */
609
stl_raw(p++, 0x00000000); /* nop */
610
stl_raw(p++, 0x01a00008); /* jr t5 */
611
stl_raw(p++, 0x01602021); /* move a0,t3 */
612
/* 0x83c YAMON print_count */
613
stl_raw(p++, 0x03e06821); /* move t5,ra */
614
stl_raw(p++, 0x00805821); /* move t3,a0 */
615
stl_raw(p++, 0x00a05021); /* move t2,a1 */
616
stl_raw(p++, 0x00c06021); /* move t4,a2 */
617
stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
618
stl_raw(p++, 0x0ff0021c); /* jal 870 */
619
stl_raw(p++, 0x00000000); /* nop */
620
stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
621
stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
622
stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
623
stl_raw(p++, 0x00000000); /* nop */
624
stl_raw(p++, 0x01a00008); /* jr t5 */
625
stl_raw(p++, 0x01602021); /* move a0,t3 */
627
stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
628
stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
629
stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
630
stl_raw(p++, 0x00000000); /* nop */
631
stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
632
stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
633
stl_raw(p++, 0x00000000); /* nop */
634
stl_raw(p++, 0x03e00008); /* jr ra */
635
stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
639
static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
640
const char *string, ...)
645
if (index >= ENVP_NB_ENTRIES)
648
if (string == NULL) {
653
table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
654
prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
656
va_start(ap, string);
657
vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
662
static int64_t load_kernel (void)
664
int64_t kernel_entry, kernel_high;
666
ram_addr_t initrd_offset;
672
#ifdef TARGET_WORDS_BIGENDIAN
678
if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
679
(uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
680
big_endian, ELF_MACHINE, 1) < 0) {
681
fprintf(stderr, "qemu: could not load kernel '%s'\n",
682
loaderparams.kernel_filename);
689
if (loaderparams.initrd_filename) {
690
initrd_size = get_image_size (loaderparams.initrd_filename);
691
if (initrd_size > 0) {
692
initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
693
if (initrd_offset + initrd_size > ram_size) {
695
"qemu: memory too small for initial ram disk '%s'\n",
696
loaderparams.initrd_filename);
699
initrd_size = load_image_targphys(loaderparams.initrd_filename,
701
ram_size - initrd_offset);
703
if (initrd_size == (target_ulong) -1) {
704
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
705
loaderparams.initrd_filename);
710
/* Setup prom parameters. */
711
prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
712
prom_buf = qemu_malloc(prom_size);
714
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
715
if (initrd_size > 0) {
716
prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
717
cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
718
loaderparams.kernel_cmdline);
720
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
723
prom_set(prom_buf, prom_index++, "memsize");
724
prom_set(prom_buf, prom_index++, "%i", loaderparams.ram_size);
725
prom_set(prom_buf, prom_index++, "modetty0");
726
prom_set(prom_buf, prom_index++, "38400n8r");
727
prom_set(prom_buf, prom_index++, NULL);
729
rom_add_blob_fixed("prom", prom_buf, prom_size,
730
cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
735
static void main_cpu_reset(void *opaque)
737
CPUState *env = opaque;
740
/* The bootloader does not need to be rewritten as it is located in a
741
read only location. The kernel location and the arguments table
742
location does not change. */
743
if (loaderparams.kernel_filename) {
744
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
748
static void cpu_request_exit(void *opaque, int irq, int level)
750
CPUState *env = cpu_single_env;
758
void mips_malta_init (ram_addr_t ram_size,
759
const char *boot_device,
760
const char *kernel_filename, const char *kernel_cmdline,
761
const char *initrd_filename, const char *cpu_model)
764
ram_addr_t ram_offset;
765
ram_addr_t bios_offset;
766
target_long bios_size;
767
int64_t kernel_entry;
771
qemu_irq *cpu_exit_irq;
776
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
777
DriveInfo *fd[MAX_FD];
782
/* Make sure the first 3 serial ports are associated with a device. */
783
for(i = 0; i < 3; i++) {
784
if (!serial_hds[i]) {
786
snprintf(label, sizeof(label), "serial%d", i);
787
serial_hds[i] = qemu_chr_open(label, "null", NULL);
792
if (cpu_model == NULL) {
799
env = cpu_init(cpu_model);
801
fprintf(stderr, "Unable to find CPU definition\n");
804
qemu_register_reset(main_cpu_reset, env);
807
if (ram_size > (256 << 20)) {
809
"qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
810
((unsigned int)ram_size / (1 << 20)));
813
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
814
bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE);
817
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
819
/* Map the bios at two physical locations, as on the real board. */
820
cpu_register_physical_memory(0x1e000000LL,
821
BIOS_SIZE, bios_offset | IO_MEM_ROM);
822
cpu_register_physical_memory(0x1fc00000LL,
823
BIOS_SIZE, bios_offset | IO_MEM_ROM);
825
#ifdef TARGET_WORDS_BIGENDIAN
831
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
833
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
834
if (kernel_filename) {
835
/* Write a small bootloader to the flash location. */
836
loaderparams.ram_size = ram_size;
837
loaderparams.kernel_filename = kernel_filename;
838
loaderparams.kernel_cmdline = kernel_cmdline;
839
loaderparams.initrd_filename = initrd_filename;
840
kernel_entry = load_kernel();
841
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
843
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
845
/* Load firmware from flash. */
846
bios_size = 0x400000;
847
fl_sectors = bios_size >> 16;
848
#ifdef DEBUG_BOARD_INIT
849
printf("Register parallel flash %d size " TARGET_FMT_lx " at "
850
"offset %08lx addr %08llx '%s' %x\n",
851
fl_idx, bios_size, bios_offset, 0x1e000000LL,
852
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
854
pflash_cfi01_register(0x1e000000LL, bios_offset,
855
dinfo->bdrv, 65536, fl_sectors,
856
4, 0x0000, 0x0000, 0x0000, 0x0000, be);
859
/* Load a BIOS image. */
860
if (bios_name == NULL)
861
bios_name = BIOS_FILENAME;
862
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
864
bios_size = load_image_targphys(filename, 0x1fc00000LL,
870
if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
872
"qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
877
/* In little endian mode the 32bit words in the bios are swapped,
878
a neat trick which allows bi-endian firmware. */
879
#ifndef TARGET_WORDS_BIGENDIAN
881
uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
882
uint32_t *end = addr + bios_size;
890
/* Board ID = 0x420 (Malta Board with CoreLV)
891
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
892
map to the board ID. */
893
stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420);
895
/* Init internal devices */
896
cpu_mips_irq_init_cpu(env);
897
cpu_mips_clock_init(env);
899
/* Interrupt controller */
900
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
901
i8259 = i8259_init(env->irq[2]);
904
pci_bus = gt64120_register(i8259);
907
ide_drive_get(hd, MAX_IDE_BUS);
909
piix4_devfn = piix4_init(pci_bus, 80);
911
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
912
usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
913
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(9),
915
/* TODO: Populate SPD eeprom data. */
916
smbus_eeprom_init(smbus, 8, NULL, 0);
917
pit = pit_init(0x40, 0);
918
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
919
DMA_init(0, cpu_exit_irq);
922
isa_create_simple("i8042");
924
rtc_init(2000, NULL);
925
serial_isa_init(0, serial_hds[0]);
926
serial_isa_init(1, serial_hds[1]);
928
parallel_init(0, parallel_hds[0]);
929
for(i = 0; i < MAX_FD; i++) {
930
fd[i] = drive_get(IF_FLOPPY, 0, i);
935
audio_init(NULL, pci_bus);
940
/* Optional PCI video card */
941
if (cirrus_vga_enabled) {
942
pci_cirrus_vga_init(pci_bus);
943
} else if (vmsvga_enabled) {
944
if (!pci_vmsvga_init(pci_bus)) {
945
fprintf(stderr, "Warning: vmware_vga not available,"
946
" using standard VGA instead\n");
947
pci_vga_init(pci_bus);
949
} else if (std_vga_enabled) {
950
pci_vga_init(pci_bus);
954
static QEMUMachine mips_malta_machine = {
956
.desc = "MIPS Malta Core LV",
957
.init = mips_malta_init,
961
static void mips_malta_machine_init(void)
963
qemu_register_machine(&mips_malta_machine);
966
machine_init(mips_malta_machine_init);
added
removed
hw/mips_malta.c
