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* Tiny Code Generator for QEMU
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* Copyright (c) 2008 Fabrice Bellard
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
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*gen_opparam_ptr++ = arg1;
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = arg2;
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = arg2;
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
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*gen_opparam_ptr++ = arg1;
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*gen_opparam_ptr++ = arg2;
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
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TCGv_i32 arg2, TCGArg arg3)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = arg3;
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
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TCGv_i64 arg2, TCGArg arg3)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = arg3;
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
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TCGv_ptr base, TCGArg offset)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(val);
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*gen_opparam_ptr++ = GET_TCGV_PTR(base);
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*gen_opparam_ptr++ = offset;
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
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TCGv_ptr base, TCGArg offset)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(val);
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*gen_opparam_ptr++ = GET_TCGV_PTR(base);
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*gen_opparam_ptr++ = offset;
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
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TCGv_i32 addr, TCGArg mem_index)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(val);
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*gen_opparam_ptr++ = GET_TCGV_I32(addr);
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*gen_opparam_ptr++ = mem_index;
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
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TCGv_i64 addr, TCGArg mem_index)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(val);
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*gen_opparam_ptr++ = GET_TCGV_I64(addr);
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*gen_opparam_ptr++ = mem_index;
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGv_i32 arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGv_i64 arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGArg arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = arg4;
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGArg arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = arg4;
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGArg arg3, TCGArg arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = arg3;
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*gen_opparam_ptr++ = arg4;
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGArg arg3, TCGArg arg4)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = arg3;
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*gen_opparam_ptr++ = arg4;
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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*gen_opparam_ptr++ = arg5;
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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*gen_opparam_ptr++ = arg5;
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static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
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TCGv_i32 arg2, TCGv_i32 arg3,
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TCGArg arg4, TCGArg arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = arg4;
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*gen_opparam_ptr++ = arg5;
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static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
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TCGv_i64 arg2, TCGv_i64 arg3,
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TCGArg arg4, TCGArg arg5)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = arg4;
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*gen_opparam_ptr++ = arg5;
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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TCGv_i32 arg3, TCGv_i32 arg4,
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TCGv_i32 arg5, TCGArg arg6)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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*gen_opparam_ptr++ = arg6;
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static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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TCGv_i64 arg3, TCGv_i64 arg4,
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TCGv_i64 arg5, TCGArg arg6)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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*gen_opparam_ptr++ = arg6;
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static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
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TCGv_i32 arg2, TCGv_i32 arg3,
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TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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*gen_opparam_ptr++ = arg5;
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*gen_opparam_ptr++ = arg6;
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static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
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TCGv_i64 arg2, TCGv_i64 arg3,
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TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
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*gen_opc_ptr++ = opc;
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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*gen_opparam_ptr++ = arg5;
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*gen_opparam_ptr++ = arg6;
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static inline void gen_set_label(int n)
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tcg_gen_op1i(INDEX_op_set_label, n);
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static inline void tcg_gen_br(int label)
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tcg_gen_op1i(INDEX_op_br, label);
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
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if (!TCGV_EQUAL_I32(ret, arg))
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tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
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tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
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/* A version of dh_sizemask from def-helper.h that doesn't rely on
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preprocessor magic. */
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static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
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return (is_64bit << n*2) | (is_signed << (n*2 + 1));
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static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
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TCGArg ret, int nargs, TCGArg *args)
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fn = tcg_const_ptr((tcg_target_long)func);
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tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
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tcg_temp_free_ptr(fn);
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/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
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reserved for helpers in tcg-runtime.c. These helpers are all const
400
and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
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TCG_CALL_PURE. This may need to be adjusted if these functions
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start to be used with other helpers. */
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static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
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TCGv_i32 a, TCGv_i32 b)
408
fn = tcg_const_ptr((tcg_target_long)func);
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args[0] = GET_TCGV_I32(a);
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args[1] = GET_TCGV_I32(b);
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tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
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GET_TCGV_I32(ret), 2, args);
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tcg_temp_free_ptr(fn);
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static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
417
TCGv_i64 a, TCGv_i64 b)
421
fn = tcg_const_ptr((tcg_target_long)func);
422
args[0] = GET_TCGV_I64(a);
423
args[1] = GET_TCGV_I64(b);
424
tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
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GET_TCGV_I64(ret), 2, args);
426
tcg_temp_free_ptr(fn);
431
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
433
tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
436
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
438
tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
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static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
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tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
446
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
448
tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
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static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
453
tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
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static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
458
tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
461
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
463
tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
466
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
468
tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
471
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
473
tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
476
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
478
/* some cases can be optimized here */
480
tcg_gen_mov_i32(ret, arg1);
482
TCGv_i32 t0 = tcg_const_i32(arg2);
483
tcg_gen_add_i32(ret, arg1, t0);
484
tcg_temp_free_i32(t0);
488
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
490
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
493
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
495
TCGv_i32 t0 = tcg_const_i32(arg1);
496
tcg_gen_sub_i32(ret, t0, arg2);
497
tcg_temp_free_i32(t0);
500
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
502
/* some cases can be optimized here */
504
tcg_gen_mov_i32(ret, arg1);
506
TCGv_i32 t0 = tcg_const_i32(arg2);
507
tcg_gen_sub_i32(ret, arg1, t0);
508
tcg_temp_free_i32(t0);
512
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
514
if (TCGV_EQUAL_I32(arg1, arg2)) {
515
tcg_gen_mov_i32(ret, arg1);
517
tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
521
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
523
/* some cases can be optimized here */
525
tcg_gen_movi_i32(ret, 0);
526
} else if (arg2 == 0xffffffff) {
527
tcg_gen_mov_i32(ret, arg1);
529
TCGv_i32 t0 = tcg_const_i32(arg2);
530
tcg_gen_and_i32(ret, arg1, t0);
531
tcg_temp_free_i32(t0);
535
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
537
if (TCGV_EQUAL_I32(arg1, arg2)) {
538
tcg_gen_mov_i32(ret, arg1);
540
tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
544
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
546
/* some cases can be optimized here */
547
if (arg2 == 0xffffffff) {
548
tcg_gen_movi_i32(ret, 0xffffffff);
549
} else if (arg2 == 0) {
550
tcg_gen_mov_i32(ret, arg1);
552
TCGv_i32 t0 = tcg_const_i32(arg2);
553
tcg_gen_or_i32(ret, arg1, t0);
554
tcg_temp_free_i32(t0);
558
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
560
if (TCGV_EQUAL_I32(arg1, arg2)) {
561
tcg_gen_movi_i32(ret, 0);
563
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
567
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
569
/* some cases can be optimized here */
571
tcg_gen_mov_i32(ret, arg1);
573
TCGv_i32 t0 = tcg_const_i32(arg2);
574
tcg_gen_xor_i32(ret, arg1, t0);
575
tcg_temp_free_i32(t0);
579
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
581
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
584
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
587
tcg_gen_mov_i32(ret, arg1);
589
TCGv_i32 t0 = tcg_const_i32(arg2);
590
tcg_gen_shl_i32(ret, arg1, t0);
591
tcg_temp_free_i32(t0);
595
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
597
tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
600
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
603
tcg_gen_mov_i32(ret, arg1);
605
TCGv_i32 t0 = tcg_const_i32(arg2);
606
tcg_gen_shr_i32(ret, arg1, t0);
607
tcg_temp_free_i32(t0);
611
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
613
tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
616
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
619
tcg_gen_mov_i32(ret, arg1);
621
TCGv_i32 t0 = tcg_const_i32(arg2);
622
tcg_gen_sar_i32(ret, arg1, t0);
623
tcg_temp_free_i32(t0);
627
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
628
TCGv_i32 arg2, int label_index)
630
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
633
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
634
int32_t arg2, int label_index)
636
TCGv_i32 t0 = tcg_const_i32(arg2);
637
tcg_gen_brcond_i32(cond, arg1, t0, label_index);
638
tcg_temp_free_i32(t0);
641
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
642
TCGv_i32 arg1, TCGv_i32 arg2)
644
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
647
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
648
TCGv_i32 arg1, int32_t arg2)
650
TCGv_i32 t0 = tcg_const_i32(arg2);
651
tcg_gen_setcond_i32(cond, ret, arg1, t0);
652
tcg_temp_free_i32(t0);
655
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
657
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
660
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
662
TCGv_i32 t0 = tcg_const_i32(arg2);
663
tcg_gen_mul_i32(ret, arg1, t0);
664
tcg_temp_free_i32(t0);
667
#ifdef TCG_TARGET_HAS_div_i32
668
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
670
tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
673
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
675
tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
678
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
680
tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
683
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
685
tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
687
#elif defined(TCG_TARGET_HAS_div2_i32)
688
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
691
t0 = tcg_temp_new_i32();
692
tcg_gen_sari_i32(t0, arg1, 31);
693
tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
694
tcg_temp_free_i32(t0);
697
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
700
t0 = tcg_temp_new_i32();
701
tcg_gen_sari_i32(t0, arg1, 31);
702
tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
703
tcg_temp_free_i32(t0);
706
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
709
t0 = tcg_temp_new_i32();
710
tcg_gen_movi_i32(t0, 0);
711
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
712
tcg_temp_free_i32(t0);
715
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
718
t0 = tcg_temp_new_i32();
719
tcg_gen_movi_i32(t0, 0);
720
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
721
tcg_temp_free_i32(t0);
724
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
727
/* Return value and both arguments are 32-bit and signed. */
728
sizemask |= tcg_gen_sizemask(0, 0, 1);
729
sizemask |= tcg_gen_sizemask(1, 0, 1);
730
sizemask |= tcg_gen_sizemask(2, 0, 1);
732
tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
735
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
738
/* Return value and both arguments are 32-bit and signed. */
739
sizemask |= tcg_gen_sizemask(0, 0, 1);
740
sizemask |= tcg_gen_sizemask(1, 0, 1);
741
sizemask |= tcg_gen_sizemask(2, 0, 1);
743
tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
746
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
749
/* Return value and both arguments are 32-bit and unsigned. */
750
sizemask |= tcg_gen_sizemask(0, 0, 0);
751
sizemask |= tcg_gen_sizemask(1, 0, 0);
752
sizemask |= tcg_gen_sizemask(2, 0, 0);
754
tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
757
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
760
/* Return value and both arguments are 32-bit and unsigned. */
761
sizemask |= tcg_gen_sizemask(0, 0, 0);
762
sizemask |= tcg_gen_sizemask(1, 0, 0);
763
sizemask |= tcg_gen_sizemask(2, 0, 0);
765
tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
769
#if TCG_TARGET_REG_BITS == 32
771
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
773
if (!TCGV_EQUAL_I64(ret, arg)) {
774
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
775
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
779
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
781
tcg_gen_movi_i32(TCGV_LOW(ret), arg);
782
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
785
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
786
tcg_target_long offset)
788
tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
789
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
792
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
793
tcg_target_long offset)
795
tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
796
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
799
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
800
tcg_target_long offset)
802
tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
803
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
806
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
807
tcg_target_long offset)
809
tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
810
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
813
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
814
tcg_target_long offset)
816
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
817
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
820
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
821
tcg_target_long offset)
823
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
824
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
827
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
828
tcg_target_long offset)
830
/* since arg2 and ret have different types, they cannot be the
832
#ifdef TCG_TARGET_WORDS_BIGENDIAN
833
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
834
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
836
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
837
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
841
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
842
tcg_target_long offset)
844
tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
847
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
848
tcg_target_long offset)
850
tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
853
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
854
tcg_target_long offset)
856
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
859
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
860
tcg_target_long offset)
862
#ifdef TCG_TARGET_WORDS_BIGENDIAN
863
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
864
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
866
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
867
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
871
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
873
tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
878
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
880
tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
881
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
885
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
887
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
888
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
891
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
893
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
894
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
897
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
899
tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
900
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
903
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
905
tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
906
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
909
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
911
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
912
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
915
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
917
tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
918
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
921
/* XXX: use generic code when basic block handling is OK or CPU
922
specific code (x86) */
923
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
926
/* Return value and both arguments are 64-bit and signed. */
927
sizemask |= tcg_gen_sizemask(0, 1, 1);
928
sizemask |= tcg_gen_sizemask(1, 1, 1);
929
sizemask |= tcg_gen_sizemask(2, 1, 1);
931
tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
934
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
936
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
939
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
942
/* Return value and both arguments are 64-bit and signed. */
943
sizemask |= tcg_gen_sizemask(0, 1, 1);
944
sizemask |= tcg_gen_sizemask(1, 1, 1);
945
sizemask |= tcg_gen_sizemask(2, 1, 1);
947
tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
950
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
952
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
955
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
958
/* Return value and both arguments are 64-bit and signed. */
959
sizemask |= tcg_gen_sizemask(0, 1, 1);
960
sizemask |= tcg_gen_sizemask(1, 1, 1);
961
sizemask |= tcg_gen_sizemask(2, 1, 1);
963
tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
966
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
968
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
971
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
972
TCGv_i64 arg2, int label_index)
974
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
975
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
976
TCGV_HIGH(arg2), cond, label_index);
979
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
980
TCGv_i64 arg1, TCGv_i64 arg2)
982
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
983
TCGV_LOW(arg1), TCGV_HIGH(arg1),
984
TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
985
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
988
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
993
t0 = tcg_temp_new_i64();
994
t1 = tcg_temp_new_i32();
996
tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
997
TCGV_LOW(arg1), TCGV_LOW(arg2));
999
tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1000
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1001
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1002
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1004
tcg_gen_mov_i64(ret, t0);
1005
tcg_temp_free_i64(t0);
1006
tcg_temp_free_i32(t1);
1009
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1012
/* Return value and both arguments are 64-bit and signed. */
1013
sizemask |= tcg_gen_sizemask(0, 1, 1);
1014
sizemask |= tcg_gen_sizemask(1, 1, 1);
1015
sizemask |= tcg_gen_sizemask(2, 1, 1);
1017
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1020
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1023
/* Return value and both arguments are 64-bit and signed. */
1024
sizemask |= tcg_gen_sizemask(0, 1, 1);
1025
sizemask |= tcg_gen_sizemask(1, 1, 1);
1026
sizemask |= tcg_gen_sizemask(2, 1, 1);
1028
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1031
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1034
/* Return value and both arguments are 64-bit and unsigned. */
1035
sizemask |= tcg_gen_sizemask(0, 1, 0);
1036
sizemask |= tcg_gen_sizemask(1, 1, 0);
1037
sizemask |= tcg_gen_sizemask(2, 1, 0);
1039
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1042
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1045
/* Return value and both arguments are 64-bit and unsigned. */
1046
sizemask |= tcg_gen_sizemask(0, 1, 0);
1047
sizemask |= tcg_gen_sizemask(1, 1, 0);
1048
sizemask |= tcg_gen_sizemask(2, 1, 0);
1050
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1055
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1057
if (!TCGV_EQUAL_I64(ret, arg))
1058
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1061
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1063
tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1066
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1067
tcg_target_long offset)
1069
tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1072
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1073
tcg_target_long offset)
1075
tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1078
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1079
tcg_target_long offset)
1081
tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1084
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1085
tcg_target_long offset)
1087
tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1090
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1091
tcg_target_long offset)
1093
tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1096
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1097
tcg_target_long offset)
1099
tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1102
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1104
tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1107
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1108
tcg_target_long offset)
1110
tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1113
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1114
tcg_target_long offset)
1116
tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1119
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1120
tcg_target_long offset)
1122
tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1125
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1127
tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1130
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1132
tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1135
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1137
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1140
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1142
if (TCGV_EQUAL_I64(arg1, arg2)) {
1143
tcg_gen_mov_i64(ret, arg1);
1145
tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1149
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1151
TCGv_i64 t0 = tcg_const_i64(arg2);
1152
tcg_gen_and_i64(ret, arg1, t0);
1153
tcg_temp_free_i64(t0);
1156
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1158
if (TCGV_EQUAL_I64(arg1, arg2)) {
1159
tcg_gen_mov_i64(ret, arg1);
1161
tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1165
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1167
TCGv_i64 t0 = tcg_const_i64(arg2);
1168
tcg_gen_or_i64(ret, arg1, t0);
1169
tcg_temp_free_i64(t0);
1172
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1174
if (TCGV_EQUAL_I64(arg1, arg2)) {
1175
tcg_gen_movi_i64(ret, 0);
1177
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1181
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1183
TCGv_i64 t0 = tcg_const_i64(arg2);
1184
tcg_gen_xor_i64(ret, arg1, t0);
1185
tcg_temp_free_i64(t0);
1188
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1190
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1193
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1196
tcg_gen_mov_i64(ret, arg1);
1198
TCGv_i64 t0 = tcg_const_i64(arg2);
1199
tcg_gen_shl_i64(ret, arg1, t0);
1200
tcg_temp_free_i64(t0);
1204
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1206
tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1209
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1212
tcg_gen_mov_i64(ret, arg1);
1214
TCGv_i64 t0 = tcg_const_i64(arg2);
1215
tcg_gen_shr_i64(ret, arg1, t0);
1216
tcg_temp_free_i64(t0);
1220
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1222
tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1225
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1228
tcg_gen_mov_i64(ret, arg1);
1230
TCGv_i64 t0 = tcg_const_i64(arg2);
1231
tcg_gen_sar_i64(ret, arg1, t0);
1232
tcg_temp_free_i64(t0);
1236
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1237
TCGv_i64 arg2, int label_index)
1239
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1242
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1243
TCGv_i64 arg1, TCGv_i64 arg2)
1245
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1248
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1250
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1253
#ifdef TCG_TARGET_HAS_div_i64
1254
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1256
tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1259
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1261
tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1264
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1266
tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1269
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1271
tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1273
#elif defined(TCG_TARGET_HAS_div2_i64)
1274
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1277
t0 = tcg_temp_new_i64();
1278
tcg_gen_sari_i64(t0, arg1, 63);
1279
tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1280
tcg_temp_free_i64(t0);
1283
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1286
t0 = tcg_temp_new_i64();
1287
tcg_gen_sari_i64(t0, arg1, 63);
1288
tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1289
tcg_temp_free_i64(t0);
1292
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1295
t0 = tcg_temp_new_i64();
1296
tcg_gen_movi_i64(t0, 0);
1297
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1298
tcg_temp_free_i64(t0);
1301
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1304
t0 = tcg_temp_new_i64();
1305
tcg_gen_movi_i64(t0, 0);
1306
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1307
tcg_temp_free_i64(t0);
1310
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1313
/* Return value and both arguments are 64-bit and signed. */
1314
sizemask |= tcg_gen_sizemask(0, 1, 1);
1315
sizemask |= tcg_gen_sizemask(1, 1, 1);
1316
sizemask |= tcg_gen_sizemask(2, 1, 1);
1318
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1321
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1324
/* Return value and both arguments are 64-bit and signed. */
1325
sizemask |= tcg_gen_sizemask(0, 1, 1);
1326
sizemask |= tcg_gen_sizemask(1, 1, 1);
1327
sizemask |= tcg_gen_sizemask(2, 1, 1);
1329
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1332
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1335
/* Return value and both arguments are 64-bit and unsigned. */
1336
sizemask |= tcg_gen_sizemask(0, 1, 0);
1337
sizemask |= tcg_gen_sizemask(1, 1, 0);
1338
sizemask |= tcg_gen_sizemask(2, 1, 0);
1340
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1343
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1346
/* Return value and both arguments are 64-bit and unsigned. */
1347
sizemask |= tcg_gen_sizemask(0, 1, 0);
1348
sizemask |= tcg_gen_sizemask(1, 1, 0);
1349
sizemask |= tcg_gen_sizemask(2, 1, 0);
1351
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1357
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1359
/* some cases can be optimized here */
1361
tcg_gen_mov_i64(ret, arg1);
1363
TCGv_i64 t0 = tcg_const_i64(arg2);
1364
tcg_gen_add_i64(ret, arg1, t0);
1365
tcg_temp_free_i64(t0);
1369
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1371
TCGv_i64 t0 = tcg_const_i64(arg1);
1372
tcg_gen_sub_i64(ret, t0, arg2);
1373
tcg_temp_free_i64(t0);
1376
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1378
/* some cases can be optimized here */
1380
tcg_gen_mov_i64(ret, arg1);
1382
TCGv_i64 t0 = tcg_const_i64(arg2);
1383
tcg_gen_sub_i64(ret, arg1, t0);
1384
tcg_temp_free_i64(t0);
1387
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1388
int64_t arg2, int label_index)
1390
TCGv_i64 t0 = tcg_const_i64(arg2);
1391
tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1392
tcg_temp_free_i64(t0);
1395
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1396
TCGv_i64 arg1, int64_t arg2)
1398
TCGv_i64 t0 = tcg_const_i64(arg2);
1399
tcg_gen_setcond_i64(cond, ret, arg1, t0);
1400
tcg_temp_free_i64(t0);
1403
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1405
TCGv_i64 t0 = tcg_const_i64(arg2);
1406
tcg_gen_mul_i64(ret, arg1, t0);
1407
tcg_temp_free_i64(t0);
1411
/***************************************/
1412
/* optional operations */
1414
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1416
#ifdef TCG_TARGET_HAS_ext8s_i32
1417
tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1419
tcg_gen_shli_i32(ret, arg, 24);
1420
tcg_gen_sari_i32(ret, ret, 24);
1424
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1426
#ifdef TCG_TARGET_HAS_ext16s_i32
1427
tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1429
tcg_gen_shli_i32(ret, arg, 16);
1430
tcg_gen_sari_i32(ret, ret, 16);
1434
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1436
#ifdef TCG_TARGET_HAS_ext8u_i32
1437
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1439
tcg_gen_andi_i32(ret, arg, 0xffu);
1443
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1445
#ifdef TCG_TARGET_HAS_ext16u_i32
1446
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1448
tcg_gen_andi_i32(ret, arg, 0xffffu);
1452
/* Note: we assume the two high bytes are set to zero */
1453
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1455
#ifdef TCG_TARGET_HAS_bswap16_i32
1456
tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1458
TCGv_i32 t0 = tcg_temp_new_i32();
1460
tcg_gen_ext8u_i32(t0, arg);
1461
tcg_gen_shli_i32(t0, t0, 8);
1462
tcg_gen_shri_i32(ret, arg, 8);
1463
tcg_gen_or_i32(ret, ret, t0);
1464
tcg_temp_free_i32(t0);
1468
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1470
#ifdef TCG_TARGET_HAS_bswap32_i32
1471
tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1474
t0 = tcg_temp_new_i32();
1475
t1 = tcg_temp_new_i32();
1477
tcg_gen_shli_i32(t0, arg, 24);
1479
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1480
tcg_gen_shli_i32(t1, t1, 8);
1481
tcg_gen_or_i32(t0, t0, t1);
1483
tcg_gen_shri_i32(t1, arg, 8);
1484
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1485
tcg_gen_or_i32(t0, t0, t1);
1487
tcg_gen_shri_i32(t1, arg, 24);
1488
tcg_gen_or_i32(ret, t0, t1);
1489
tcg_temp_free_i32(t0);
1490
tcg_temp_free_i32(t1);
1494
#if TCG_TARGET_REG_BITS == 32
1495
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1497
tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1498
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1501
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1503
tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1504
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1507
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1509
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1510
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1513
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1515
tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1516
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1519
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1521
tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1522
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1525
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1527
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1528
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1531
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1533
tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1536
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1538
tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1539
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1542
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1544
tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1545
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1548
/* Note: we assume the six high bytes are set to zero */
1549
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1551
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1552
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1555
/* Note: we assume the four high bytes are set to zero */
1556
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1558
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1559
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1562
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1565
t0 = tcg_temp_new_i32();
1566
t1 = tcg_temp_new_i32();
1568
tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1569
tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1570
tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1571
tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1572
tcg_temp_free_i32(t0);
1573
tcg_temp_free_i32(t1);
1577
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1579
#ifdef TCG_TARGET_HAS_ext8s_i64
1580
tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1582
tcg_gen_shli_i64(ret, arg, 56);
1583
tcg_gen_sari_i64(ret, ret, 56);
1587
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1589
#ifdef TCG_TARGET_HAS_ext16s_i64
1590
tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1592
tcg_gen_shli_i64(ret, arg, 48);
1593
tcg_gen_sari_i64(ret, ret, 48);
1597
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1599
#ifdef TCG_TARGET_HAS_ext32s_i64
1600
tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1602
tcg_gen_shli_i64(ret, arg, 32);
1603
tcg_gen_sari_i64(ret, ret, 32);
1607
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1609
#ifdef TCG_TARGET_HAS_ext8u_i64
1610
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1612
tcg_gen_andi_i64(ret, arg, 0xffu);
1616
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1618
#ifdef TCG_TARGET_HAS_ext16u_i64
1619
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1621
tcg_gen_andi_i64(ret, arg, 0xffffu);
1625
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1627
#ifdef TCG_TARGET_HAS_ext32u_i64
1628
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1630
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1634
/* Note: we assume the target supports move between 32 and 64 bit
1635
registers. This will probably break MIPS64 targets. */
1636
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1638
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1641
/* Note: we assume the target supports move between 32 and 64 bit
1643
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1645
tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1648
/* Note: we assume the target supports move between 32 and 64 bit
1650
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1652
tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1655
/* Note: we assume the six high bytes are set to zero */
1656
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1658
#ifdef TCG_TARGET_HAS_bswap16_i64
1659
tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1661
TCGv_i64 t0 = tcg_temp_new_i64();
1663
tcg_gen_ext8u_i64(t0, arg);
1664
tcg_gen_shli_i64(t0, t0, 8);
1665
tcg_gen_shri_i64(ret, arg, 8);
1666
tcg_gen_or_i64(ret, ret, t0);
1667
tcg_temp_free_i64(t0);
1671
/* Note: we assume the four high bytes are set to zero */
1672
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1674
#ifdef TCG_TARGET_HAS_bswap32_i64
1675
tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1678
t0 = tcg_temp_new_i64();
1679
t1 = tcg_temp_new_i64();
1681
tcg_gen_shli_i64(t0, arg, 24);
1682
tcg_gen_ext32u_i64(t0, t0);
1684
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1685
tcg_gen_shli_i64(t1, t1, 8);
1686
tcg_gen_or_i64(t0, t0, t1);
1688
tcg_gen_shri_i64(t1, arg, 8);
1689
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1690
tcg_gen_or_i64(t0, t0, t1);
1692
tcg_gen_shri_i64(t1, arg, 24);
1693
tcg_gen_or_i64(ret, t0, t1);
1694
tcg_temp_free_i64(t0);
1695
tcg_temp_free_i64(t1);
1699
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1701
#ifdef TCG_TARGET_HAS_bswap64_i64
1702
tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1704
TCGv_i64 t0 = tcg_temp_new_i64();
1705
TCGv_i64 t1 = tcg_temp_new_i64();
1707
tcg_gen_shli_i64(t0, arg, 56);
1709
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1710
tcg_gen_shli_i64(t1, t1, 40);
1711
tcg_gen_or_i64(t0, t0, t1);
1713
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1714
tcg_gen_shli_i64(t1, t1, 24);
1715
tcg_gen_or_i64(t0, t0, t1);
1717
tcg_gen_andi_i64(t1, arg, 0xff000000);
1718
tcg_gen_shli_i64(t1, t1, 8);
1719
tcg_gen_or_i64(t0, t0, t1);
1721
tcg_gen_shri_i64(t1, arg, 8);
1722
tcg_gen_andi_i64(t1, t1, 0xff000000);
1723
tcg_gen_or_i64(t0, t0, t1);
1725
tcg_gen_shri_i64(t1, arg, 24);
1726
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1727
tcg_gen_or_i64(t0, t0, t1);
1729
tcg_gen_shri_i64(t1, arg, 40);
1730
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1731
tcg_gen_or_i64(t0, t0, t1);
1733
tcg_gen_shri_i64(t1, arg, 56);
1734
tcg_gen_or_i64(ret, t0, t1);
1735
tcg_temp_free_i64(t0);
1736
tcg_temp_free_i64(t1);
1742
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1744
#ifdef TCG_TARGET_HAS_neg_i32
1745
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1747
TCGv_i32 t0 = tcg_const_i32(0);
1748
tcg_gen_sub_i32(ret, t0, arg);
1749
tcg_temp_free_i32(t0);
1753
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1755
#ifdef TCG_TARGET_HAS_neg_i64
1756
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1758
TCGv_i64 t0 = tcg_const_i64(0);
1759
tcg_gen_sub_i64(ret, t0, arg);
1760
tcg_temp_free_i64(t0);
1764
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1766
#ifdef TCG_TARGET_HAS_not_i32
1767
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1769
tcg_gen_xori_i32(ret, arg, -1);
1773
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1775
#ifdef TCG_TARGET_HAS_not_i64
1776
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1777
#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
1778
tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1779
tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1781
tcg_gen_xori_i64(ret, arg, -1);
1785
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1787
tcg_gen_op1_i32(INDEX_op_discard, arg);
1790
#if TCG_TARGET_REG_BITS == 32
1791
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1793
tcg_gen_discard_i32(TCGV_LOW(arg));
1794
tcg_gen_discard_i32(TCGV_HIGH(arg));
1797
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1799
tcg_gen_op1_i64(INDEX_op_discard, arg);
1803
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1805
#if TCG_TARGET_REG_BITS == 32
1806
tcg_gen_mov_i32(TCGV_LOW(dest), low);
1807
tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1809
TCGv_i64 tmp = tcg_temp_new_i64();
1810
/* This extension is only needed for type correctness.
1811
We may be able to do better given target specific information. */
1812
tcg_gen_extu_i32_i64(tmp, high);
1813
tcg_gen_shli_i64(tmp, tmp, 32);
1814
tcg_gen_extu_i32_i64(dest, low);
1815
tcg_gen_or_i64(dest, dest, tmp);
1816
tcg_temp_free_i64(tmp);
1820
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1822
#if TCG_TARGET_REG_BITS == 32
1823
tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1825
TCGv_i64 tmp = tcg_temp_new_i64();
1826
tcg_gen_ext32u_i64(dest, low);
1827
tcg_gen_shli_i64(tmp, high, 32);
1828
tcg_gen_or_i64(dest, dest, tmp);
1829
tcg_temp_free_i64(tmp);
1833
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1835
#ifdef TCG_TARGET_HAS_andc_i32
1836
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1839
t0 = tcg_temp_new_i32();
1840
tcg_gen_not_i32(t0, arg2);
1841
tcg_gen_and_i32(ret, arg1, t0);
1842
tcg_temp_free_i32(t0);
1846
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1848
#ifdef TCG_TARGET_HAS_andc_i64
1849
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1850
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
1851
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1852
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1855
t0 = tcg_temp_new_i64();
1856
tcg_gen_not_i64(t0, arg2);
1857
tcg_gen_and_i64(ret, arg1, t0);
1858
tcg_temp_free_i64(t0);
1862
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1864
#ifdef TCG_TARGET_HAS_eqv_i32
1865
tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1867
tcg_gen_xor_i32(ret, arg1, arg2);
1868
tcg_gen_not_i32(ret, ret);
1872
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1874
#ifdef TCG_TARGET_HAS_eqv_i64
1875
tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1876
#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
1877
tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1878
tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1880
tcg_gen_xor_i64(ret, arg1, arg2);
1881
tcg_gen_not_i64(ret, ret);
1885
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1887
#ifdef TCG_TARGET_HAS_nand_i32
1888
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1890
tcg_gen_and_i32(ret, arg1, arg2);
1891
tcg_gen_not_i32(ret, ret);
1895
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1897
#ifdef TCG_TARGET_HAS_nand_i64
1898
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1899
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
1900
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1901
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1903
tcg_gen_and_i64(ret, arg1, arg2);
1904
tcg_gen_not_i64(ret, ret);
1908
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1910
#ifdef TCG_TARGET_HAS_nor_i32
1911
tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1913
tcg_gen_or_i32(ret, arg1, arg2);
1914
tcg_gen_not_i32(ret, ret);
1918
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1920
#ifdef TCG_TARGET_HAS_nor_i64
1921
tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1922
#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
1923
tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1924
tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1926
tcg_gen_or_i64(ret, arg1, arg2);
1927
tcg_gen_not_i64(ret, ret);
1931
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1933
#ifdef TCG_TARGET_HAS_orc_i32
1934
tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1937
t0 = tcg_temp_new_i32();
1938
tcg_gen_not_i32(t0, arg2);
1939
tcg_gen_or_i32(ret, arg1, t0);
1940
tcg_temp_free_i32(t0);
1944
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1946
#ifdef TCG_TARGET_HAS_orc_i64
1947
tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1948
#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
1949
tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1950
tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1953
t0 = tcg_temp_new_i64();
1954
tcg_gen_not_i64(t0, arg2);
1955
tcg_gen_or_i64(ret, arg1, t0);
1956
tcg_temp_free_i64(t0);
1960
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1962
#ifdef TCG_TARGET_HAS_rot_i32
1963
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1967
t0 = tcg_temp_new_i32();
1968
t1 = tcg_temp_new_i32();
1969
tcg_gen_shl_i32(t0, arg1, arg2);
1970
tcg_gen_subfi_i32(t1, 32, arg2);
1971
tcg_gen_shr_i32(t1, arg1, t1);
1972
tcg_gen_or_i32(ret, t0, t1);
1973
tcg_temp_free_i32(t0);
1974
tcg_temp_free_i32(t1);
1978
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1980
#ifdef TCG_TARGET_HAS_rot_i64
1981
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1985
t0 = tcg_temp_new_i64();
1986
t1 = tcg_temp_new_i64();
1987
tcg_gen_shl_i64(t0, arg1, arg2);
1988
tcg_gen_subfi_i64(t1, 64, arg2);
1989
tcg_gen_shr_i64(t1, arg1, t1);
1990
tcg_gen_or_i64(ret, t0, t1);
1991
tcg_temp_free_i64(t0);
1992
tcg_temp_free_i64(t1);
1996
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1998
/* some cases can be optimized here */
2000
tcg_gen_mov_i32(ret, arg1);
2002
#ifdef TCG_TARGET_HAS_rot_i32
2003
TCGv_i32 t0 = tcg_const_i32(arg2);
2004
tcg_gen_rotl_i32(ret, arg1, t0);
2005
tcg_temp_free_i32(t0);
2008
t0 = tcg_temp_new_i32();
2009
t1 = tcg_temp_new_i32();
2010
tcg_gen_shli_i32(t0, arg1, arg2);
2011
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2012
tcg_gen_or_i32(ret, t0, t1);
2013
tcg_temp_free_i32(t0);
2014
tcg_temp_free_i32(t1);
2019
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2021
/* some cases can be optimized here */
2023
tcg_gen_mov_i64(ret, arg1);
2025
#ifdef TCG_TARGET_HAS_rot_i64
2026
TCGv_i64 t0 = tcg_const_i64(arg2);
2027
tcg_gen_rotl_i64(ret, arg1, t0);
2028
tcg_temp_free_i64(t0);
2031
t0 = tcg_temp_new_i64();
2032
t1 = tcg_temp_new_i64();
2033
tcg_gen_shli_i64(t0, arg1, arg2);
2034
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2035
tcg_gen_or_i64(ret, t0, t1);
2036
tcg_temp_free_i64(t0);
2037
tcg_temp_free_i64(t1);
2042
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2044
#ifdef TCG_TARGET_HAS_rot_i32
2045
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2049
t0 = tcg_temp_new_i32();
2050
t1 = tcg_temp_new_i32();
2051
tcg_gen_shr_i32(t0, arg1, arg2);
2052
tcg_gen_subfi_i32(t1, 32, arg2);
2053
tcg_gen_shl_i32(t1, arg1, t1);
2054
tcg_gen_or_i32(ret, t0, t1);
2055
tcg_temp_free_i32(t0);
2056
tcg_temp_free_i32(t1);
2060
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2062
#ifdef TCG_TARGET_HAS_rot_i64
2063
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2067
t0 = tcg_temp_new_i64();
2068
t1 = tcg_temp_new_i64();
2069
tcg_gen_shr_i64(t0, arg1, arg2);
2070
tcg_gen_subfi_i64(t1, 64, arg2);
2071
tcg_gen_shl_i64(t1, arg1, t1);
2072
tcg_gen_or_i64(ret, t0, t1);
2073
tcg_temp_free_i64(t0);
2074
tcg_temp_free_i64(t1);
2078
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2080
/* some cases can be optimized here */
2082
tcg_gen_mov_i32(ret, arg1);
2084
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2088
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2090
/* some cases can be optimized here */
2092
tcg_gen_mov_i64(ret, arg1);
2094
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2098
static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
2099
TCGv_i32 arg2, unsigned int ofs,
2102
#ifdef TCG_TARGET_HAS_deposit_i32
2103
tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
2105
uint32_t mask = (1u << len) - 1;
2106
TCGv_i32 t1 = tcg_temp_new_i32 ();
2108
tcg_gen_andi_i32(t1, arg2, mask);
2109
tcg_gen_shli_i32(t1, t1, ofs);
2110
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2111
tcg_gen_or_i32(ret, ret, t1);
2113
tcg_temp_free_i32(t1);
2117
static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
2118
TCGv_i64 arg2, unsigned int ofs,
2121
#ifdef TCG_TARGET_HAS_deposit_i64
2122
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2124
uint64_t mask = (1ull << len) - 1;
2125
TCGv_i64 t1 = tcg_temp_new_i64 ();
2127
tcg_gen_andi_i64(t1, arg2, mask);
2128
tcg_gen_shli_i64(t1, t1, ofs);
2129
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2130
tcg_gen_or_i64(ret, ret, t1);
2132
tcg_temp_free_i64(t1);
2136
/***************************************/
2137
/* QEMU specific operations. Their type depend on the QEMU CPU
2139
#ifndef TARGET_LONG_BITS
2140
#error must include QEMU headers
2143
#if TARGET_LONG_BITS == 32
2144
#define TCGv TCGv_i32
2145
#define tcg_temp_new() tcg_temp_new_i32()
2146
#define tcg_global_reg_new tcg_global_reg_new_i32
2147
#define tcg_global_mem_new tcg_global_mem_new_i32
2148
#define tcg_temp_local_new() tcg_temp_local_new_i32()
2149
#define tcg_temp_free tcg_temp_free_i32
2150
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2151
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2152
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2153
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2155
#define TCGv TCGv_i64
2156
#define tcg_temp_new() tcg_temp_new_i64()
2157
#define tcg_global_reg_new tcg_global_reg_new_i64
2158
#define tcg_global_mem_new tcg_global_mem_new_i64
2159
#define tcg_temp_local_new() tcg_temp_local_new_i64()
2160
#define tcg_temp_free tcg_temp_free_i64
2161
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2162
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2163
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2164
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2167
/* debug info: write the PC of the corresponding QEMU CPU instruction */
2168
static inline void tcg_gen_debug_insn_start(uint64_t pc)
2170
/* XXX: must really use a 32 bit size for TCGArg in all cases */
2171
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2172
tcg_gen_op2ii(INDEX_op_debug_insn_start,
2173
(uint32_t)(pc), (uint32_t)(pc >> 32));
2175
tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2179
static inline void tcg_gen_exit_tb(tcg_target_long val)
2181
tcg_gen_op1i(INDEX_op_exit_tb, val);
2184
static inline void tcg_gen_goto_tb(int idx)
2186
tcg_gen_op1i(INDEX_op_goto_tb, idx);
2189
#if TCG_TARGET_REG_BITS == 32
2190
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2192
#if TARGET_LONG_BITS == 32
2193
tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2195
tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2196
TCGV_HIGH(addr), mem_index);
2197
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2201
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2203
#if TARGET_LONG_BITS == 32
2204
tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2206
tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2207
TCGV_HIGH(addr), mem_index);
2208
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2212
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2214
#if TARGET_LONG_BITS == 32
2215
tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2217
tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2218
TCGV_HIGH(addr), mem_index);
2219
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2223
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2225
#if TARGET_LONG_BITS == 32
2226
tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2228
tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2229
TCGV_HIGH(addr), mem_index);
2230
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2234
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2236
#if TARGET_LONG_BITS == 32
2237
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2239
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2240
TCGV_HIGH(addr), mem_index);
2241
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2245
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2247
#if TARGET_LONG_BITS == 32
2248
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2250
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2251
TCGV_HIGH(addr), mem_index);
2252
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2256
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2258
#if TARGET_LONG_BITS == 32
2259
tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2261
tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2262
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2266
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2268
#if TARGET_LONG_BITS == 32
2269
tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2271
tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2272
TCGV_HIGH(addr), mem_index);
2276
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2278
#if TARGET_LONG_BITS == 32
2279
tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2281
tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2282
TCGV_HIGH(addr), mem_index);
2286
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2288
#if TARGET_LONG_BITS == 32
2289
tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2291
tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2292
TCGV_HIGH(addr), mem_index);
2296
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2298
#if TARGET_LONG_BITS == 32
2299
tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2302
tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2303
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2307
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2308
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2310
#else /* TCG_TARGET_REG_BITS == 32 */
2312
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2314
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2317
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2319
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2322
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2324
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2327
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2329
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2332
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2334
#if TARGET_LONG_BITS == 32
2335
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2337
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2341
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2343
#if TARGET_LONG_BITS == 32
2344
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2346
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2350
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2352
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2355
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2357
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2360
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2362
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2365
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2367
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2370
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2372
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2375
#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2376
#define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2378
#endif /* TCG_TARGET_REG_BITS != 32 */
2380
#if TARGET_LONG_BITS == 64
2381
#define tcg_gen_movi_tl tcg_gen_movi_i64
2382
#define tcg_gen_mov_tl tcg_gen_mov_i64
2383
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2384
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2385
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2386
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2387
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2388
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2389
#define tcg_gen_ld_tl tcg_gen_ld_i64
2390
#define tcg_gen_st8_tl tcg_gen_st8_i64
2391
#define tcg_gen_st16_tl tcg_gen_st16_i64
2392
#define tcg_gen_st32_tl tcg_gen_st32_i64
2393
#define tcg_gen_st_tl tcg_gen_st_i64
2394
#define tcg_gen_add_tl tcg_gen_add_i64
2395
#define tcg_gen_addi_tl tcg_gen_addi_i64
2396
#define tcg_gen_sub_tl tcg_gen_sub_i64
2397
#define tcg_gen_neg_tl tcg_gen_neg_i64
2398
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2399
#define tcg_gen_subi_tl tcg_gen_subi_i64
2400
#define tcg_gen_and_tl tcg_gen_and_i64
2401
#define tcg_gen_andi_tl tcg_gen_andi_i64
2402
#define tcg_gen_or_tl tcg_gen_or_i64
2403
#define tcg_gen_ori_tl tcg_gen_ori_i64
2404
#define tcg_gen_xor_tl tcg_gen_xor_i64
2405
#define tcg_gen_xori_tl tcg_gen_xori_i64
2406
#define tcg_gen_not_tl tcg_gen_not_i64
2407
#define tcg_gen_shl_tl tcg_gen_shl_i64
2408
#define tcg_gen_shli_tl tcg_gen_shli_i64
2409
#define tcg_gen_shr_tl tcg_gen_shr_i64
2410
#define tcg_gen_shri_tl tcg_gen_shri_i64
2411
#define tcg_gen_sar_tl tcg_gen_sar_i64
2412
#define tcg_gen_sari_tl tcg_gen_sari_i64
2413
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2414
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2415
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
2416
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2417
#define tcg_gen_mul_tl tcg_gen_mul_i64
2418
#define tcg_gen_muli_tl tcg_gen_muli_i64
2419
#define tcg_gen_div_tl tcg_gen_div_i64
2420
#define tcg_gen_rem_tl tcg_gen_rem_i64
2421
#define tcg_gen_divu_tl tcg_gen_divu_i64
2422
#define tcg_gen_remu_tl tcg_gen_remu_i64
2423
#define tcg_gen_discard_tl tcg_gen_discard_i64
2424
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2425
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2426
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2427
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2428
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2429
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2430
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2431
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2432
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2433
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2434
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2435
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2436
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2437
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2438
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2439
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2440
#define tcg_gen_andc_tl tcg_gen_andc_i64
2441
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2442
#define tcg_gen_nand_tl tcg_gen_nand_i64
2443
#define tcg_gen_nor_tl tcg_gen_nor_i64
2444
#define tcg_gen_orc_tl tcg_gen_orc_i64
2445
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2446
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2447
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2448
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2449
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
2450
#define tcg_const_tl tcg_const_i64
2451
#define tcg_const_local_tl tcg_const_local_i64
2453
#define tcg_gen_movi_tl tcg_gen_movi_i32
2454
#define tcg_gen_mov_tl tcg_gen_mov_i32
2455
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2456
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2457
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2458
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2459
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2460
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2461
#define tcg_gen_ld_tl tcg_gen_ld_i32
2462
#define tcg_gen_st8_tl tcg_gen_st8_i32
2463
#define tcg_gen_st16_tl tcg_gen_st16_i32
2464
#define tcg_gen_st32_tl tcg_gen_st_i32
2465
#define tcg_gen_st_tl tcg_gen_st_i32
2466
#define tcg_gen_add_tl tcg_gen_add_i32
2467
#define tcg_gen_addi_tl tcg_gen_addi_i32
2468
#define tcg_gen_sub_tl tcg_gen_sub_i32
2469
#define tcg_gen_neg_tl tcg_gen_neg_i32
2470
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2471
#define tcg_gen_subi_tl tcg_gen_subi_i32
2472
#define tcg_gen_and_tl tcg_gen_and_i32
2473
#define tcg_gen_andi_tl tcg_gen_andi_i32
2474
#define tcg_gen_or_tl tcg_gen_or_i32
2475
#define tcg_gen_ori_tl tcg_gen_ori_i32
2476
#define tcg_gen_xor_tl tcg_gen_xor_i32
2477
#define tcg_gen_xori_tl tcg_gen_xori_i32
2478
#define tcg_gen_not_tl tcg_gen_not_i32
2479
#define tcg_gen_shl_tl tcg_gen_shl_i32
2480
#define tcg_gen_shli_tl tcg_gen_shli_i32
2481
#define tcg_gen_shr_tl tcg_gen_shr_i32
2482
#define tcg_gen_shri_tl tcg_gen_shri_i32
2483
#define tcg_gen_sar_tl tcg_gen_sar_i32
2484
#define tcg_gen_sari_tl tcg_gen_sari_i32
2485
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2486
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2487
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
2488
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2489
#define tcg_gen_mul_tl tcg_gen_mul_i32
2490
#define tcg_gen_muli_tl tcg_gen_muli_i32
2491
#define tcg_gen_div_tl tcg_gen_div_i32
2492
#define tcg_gen_rem_tl tcg_gen_rem_i32
2493
#define tcg_gen_divu_tl tcg_gen_divu_i32
2494
#define tcg_gen_remu_tl tcg_gen_remu_i32
2495
#define tcg_gen_discard_tl tcg_gen_discard_i32
2496
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2497
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2498
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2499
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2500
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2501
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2502
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2503
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2504
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2505
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2506
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2507
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2508
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2509
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2510
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2511
#define tcg_gen_andc_tl tcg_gen_andc_i32
2512
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2513
#define tcg_gen_nand_tl tcg_gen_nand_i32
2514
#define tcg_gen_nor_tl tcg_gen_nor_i32
2515
#define tcg_gen_orc_tl tcg_gen_orc_i32
2516
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2517
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2518
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2519
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2520
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
2521
#define tcg_const_tl tcg_const_i32
2522
#define tcg_const_local_tl tcg_const_local_i32
2525
#if TCG_TARGET_REG_BITS == 32
2526
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2527
TCGV_PTR_TO_NAT(A), \
2529
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2530
TCGV_PTR_TO_NAT(A), (B))
2531
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2532
#else /* TCG_TARGET_REG_BITS == 32 */
2533
#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2534
TCGV_PTR_TO_NAT(A), \
2536
#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
2537
TCGV_PTR_TO_NAT(A), (B))
2538
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2539
#endif /* TCG_TARGET_REG_BITS != 32 */