2
* QEMU JAZZ RC4030 chipset
4
* Copyright (c) 2007-2009 Herve Poussineau
6
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
* of this software and associated documentation files (the "Software"), to deal
8
* in the Software without restriction, including without limitation the rights
9
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
* copies of the Software, and to permit persons to whom the Software is
11
* furnished to do so, subject to the following conditions:
13
* The above copyright notice and this permission notice shall be included in
14
* all copies or substantial portions of the Software.
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27
#include "qemu-timer.h"
29
/********************************************************/
32
//#define DEBUG_RC4030
33
//#define DEBUG_RC4030_DMA
36
#define DPRINTF(fmt, ...) \
37
do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
38
static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
39
"network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
41
#define DPRINTF(fmt, ...)
44
#define RC4030_ERROR(fmt, ...) \
45
do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
47
/********************************************************/
48
/* rc4030 emulation */
50
typedef struct dma_pagetable_entry {
53
} __attribute__((packed)) dma_pagetable_entry;
55
#define DMA_PAGESIZE 4096
56
#define DMA_REG_ENABLE 1
57
#define DMA_REG_COUNT 2
58
#define DMA_REG_ADDRESS 3
60
#define DMA_FLAG_ENABLE 0x0001
61
#define DMA_FLAG_MEM_TO_DEV 0x0002
62
#define DMA_FLAG_TC_INTR 0x0100
63
#define DMA_FLAG_MEM_INTR 0x0200
64
#define DMA_FLAG_ADDR_INTR 0x0400
66
typedef struct rc4030State
68
uint32_t config; /* 0x0000: RC4030 config register */
69
uint32_t revision; /* 0x0008: RC4030 Revision register */
70
uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
73
uint32_t dma_regs[8][4];
74
uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
75
uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
78
uint32_t cache_maint; /* 0x0030: Cache Maintenance */
79
uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
80
uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
81
uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
82
uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
83
uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
85
uint32_t nmi_interrupt; /* 0x0200: interrupt source */
87
uint32_t nvram_protect; /* 0x0220: NV ram protect register */
88
uint32_t rem_speed[16];
89
uint32_t imr_jazz; /* Local bus int enable mask */
90
uint32_t isr_jazz; /* Local bus int source */
93
QEMUTimer *periodic_timer;
94
uint32_t itr; /* Interval timer reload */
97
qemu_irq jazz_bus_irq;
100
static void set_next_tick(rc4030State *s)
102
qemu_irq_lower(s->timer_irq);
105
tm_hz = 1000 / (s->itr + 1);
107
qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) +
108
get_ticks_per_sec() / tm_hz);
111
/* called for accesses to rc4030 */
112
static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
114
rc4030State *s = opaque;
118
switch (addr & ~0x3) {
119
/* Global config register */
123
/* Revision register */
127
/* Invalid Address register */
129
val = s->invalid_address_register;
131
/* DMA transl. table base */
133
val = s->dma_tl_base;
135
/* DMA transl. table limit */
137
val = s->dma_tl_limit;
139
/* Remote Failed Address */
141
val = s->remote_failed_address;
143
/* Memory Failed Address */
145
val = s->memory_failed_address;
147
/* I/O Cache Byte Mask */
149
val = s->cache_bmask;
151
if (s->cache_bmask == (uint32_t)-1)
154
/* Remote Speed Registers */
171
val = s->rem_speed[(addr - 0x0070) >> 3];
173
/* DMA channel base address */
207
int entry = (addr - 0x0100) >> 5;
208
int idx = (addr & 0x1f) >> 3;
209
val = s->dma_regs[entry][idx];
212
/* Interrupt source */
214
val = s->nmi_interrupt;
224
/* NV ram protect register */
226
val = s->nvram_protect;
228
/* Interval timer count */
231
qemu_irq_lower(s->timer_irq);
235
val = 7; /* FIXME: should be read from EISA controller */
238
RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
243
if ((addr & ~3) != 0x230) {
244
DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
250
static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
252
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
259
static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
261
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
262
return (v >> (8 * (addr & 0x3))) & 0xff;
265
static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
267
rc4030State *s = opaque;
270
DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
272
switch (addr & ~0x3) {
273
/* Global config register */
277
/* DMA transl. table base */
279
s->dma_tl_base = val;
281
/* DMA transl. table limit */
283
s->dma_tl_limit = val;
285
/* DMA transl. table invalidated */
288
/* Cache Maintenance */
290
s->cache_maint = val;
292
/* I/O Cache Physical Tag */
296
/* I/O Cache Logical Tag */
300
/* I/O Cache Byte Mask */
302
s->cache_bmask |= val; /* HACK */
304
/* I/O Cache Buffer Window */
307
if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
308
target_phys_addr_t dest = s->cache_ptag & ~0x1;
309
dest += (s->cache_maint & 0x3) << 3;
310
cpu_physical_memory_write(dest, &val, 4);
313
/* Remote Speed Registers */
330
s->rem_speed[(addr - 0x0070) >> 3] = val;
332
/* DMA channel base address */
366
int entry = (addr - 0x0100) >> 5;
367
int idx = (addr & 0x1f) >> 3;
368
s->dma_regs[entry][idx] = val;
375
/* Interval timer reload */
378
qemu_irq_lower(s->timer_irq);
385
RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
390
static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
392
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
395
val = (val << 16) | (old_val & 0x0000ffff);
397
val = val | (old_val & 0xffff0000);
398
rc4030_writel(opaque, addr & ~0x3, val);
401
static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
403
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
407
val = val | (old_val & 0xffffff00);
410
val = (val << 8) | (old_val & 0xffff00ff);
413
val = (val << 16) | (old_val & 0xff00ffff);
416
val = (val << 24) | (old_val & 0x00ffffff);
419
rc4030_writel(opaque, addr & ~0x3, val);
422
static CPUReadMemoryFunc * const rc4030_read[3] = {
428
static CPUWriteMemoryFunc * const rc4030_write[3] = {
434
static void update_jazz_irq(rc4030State *s)
438
pending = s->isr_jazz & s->imr_jazz;
441
if (s->isr_jazz != 0) {
443
DPRINTF("pending irqs:");
444
for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
445
if (s->isr_jazz & (1 << irq)) {
446
printf(" %s", irq_names[irq]);
447
if (!(s->imr_jazz & (1 << irq))) {
457
qemu_irq_raise(s->jazz_bus_irq);
459
qemu_irq_lower(s->jazz_bus_irq);
462
static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
464
rc4030State *s = opaque;
467
s->isr_jazz |= 1 << irq;
469
s->isr_jazz &= ~(1 << irq);
475
static void rc4030_periodic_timer(void *opaque)
477
rc4030State *s = opaque;
480
qemu_irq_raise(s->timer_irq);
483
static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
485
rc4030State *s = opaque;
491
/* Local bus int source */
493
uint32_t pending = s->isr_jazz & s->imr_jazz;
498
DPRINTF("returning irq %s\n", irq_names[irq]);
499
val = (irq + 1) << 2;
507
/* Local bus int enable mask */
512
RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
516
DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
521
static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
524
v = jazzio_readw(opaque, addr & ~0x1);
525
return (v >> (8 * (addr & 0x1))) & 0xff;
528
static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
531
v = jazzio_readw(opaque, addr);
532
v |= jazzio_readw(opaque, addr + 2) << 16;
536
static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
538
rc4030State *s = opaque;
541
DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
544
/* Local bus int enable mask */
550
RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
555
static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
557
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
561
val = val | (old_val & 0xff00);
564
val = (val << 8) | (old_val & 0x00ff);
567
jazzio_writew(opaque, addr & ~0x1, val);
570
static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
572
jazzio_writew(opaque, addr, val & 0xffff);
573
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
576
static CPUReadMemoryFunc * const jazzio_read[3] = {
582
static CPUWriteMemoryFunc * const jazzio_write[3] = {
588
static void rc4030_reset(void *opaque)
590
rc4030State *s = opaque;
593
s->config = 0x410; /* some boards seem to accept 0x104 too */
595
s->invalid_address_register = 0;
597
memset(s->dma_regs, 0, sizeof(s->dma_regs));
598
s->dma_tl_base = s->dma_tl_limit = 0;
600
s->remote_failed_address = s->memory_failed_address = 0;
602
s->cache_ptag = s->cache_ltag = 0;
605
s->offset210 = 0x18186;
606
s->nvram_protect = 7;
607
for (i = 0; i < 15; i++)
609
s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
614
qemu_irq_lower(s->timer_irq);
615
qemu_irq_lower(s->jazz_bus_irq);
618
static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
620
rc4030State* s = opaque;
626
s->config = qemu_get_be32(f);
627
s->invalid_address_register = qemu_get_be32(f);
628
for (i = 0; i < 8; i++)
629
for (j = 0; j < 4; j++)
630
s->dma_regs[i][j] = qemu_get_be32(f);
631
s->dma_tl_base = qemu_get_be32(f);
632
s->dma_tl_limit = qemu_get_be32(f);
633
s->cache_maint = qemu_get_be32(f);
634
s->remote_failed_address = qemu_get_be32(f);
635
s->memory_failed_address = qemu_get_be32(f);
636
s->cache_ptag = qemu_get_be32(f);
637
s->cache_ltag = qemu_get_be32(f);
638
s->cache_bmask = qemu_get_be32(f);
639
s->offset210 = qemu_get_be32(f);
640
s->nvram_protect = qemu_get_be32(f);
641
for (i = 0; i < 15; i++)
642
s->rem_speed[i] = qemu_get_be32(f);
643
s->imr_jazz = qemu_get_be32(f);
644
s->isr_jazz = qemu_get_be32(f);
645
s->itr = qemu_get_be32(f);
653
static void rc4030_save(QEMUFile *f, void *opaque)
655
rc4030State* s = opaque;
658
qemu_put_be32(f, s->config);
659
qemu_put_be32(f, s->invalid_address_register);
660
for (i = 0; i < 8; i++)
661
for (j = 0; j < 4; j++)
662
qemu_put_be32(f, s->dma_regs[i][j]);
663
qemu_put_be32(f, s->dma_tl_base);
664
qemu_put_be32(f, s->dma_tl_limit);
665
qemu_put_be32(f, s->cache_maint);
666
qemu_put_be32(f, s->remote_failed_address);
667
qemu_put_be32(f, s->memory_failed_address);
668
qemu_put_be32(f, s->cache_ptag);
669
qemu_put_be32(f, s->cache_ltag);
670
qemu_put_be32(f, s->cache_bmask);
671
qemu_put_be32(f, s->offset210);
672
qemu_put_be32(f, s->nvram_protect);
673
for (i = 0; i < 15; i++)
674
qemu_put_be32(f, s->rem_speed[i]);
675
qemu_put_be32(f, s->imr_jazz);
676
qemu_put_be32(f, s->isr_jazz);
677
qemu_put_be32(f, s->itr);
680
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
682
rc4030State *s = opaque;
683
target_phys_addr_t entry_addr;
684
target_phys_addr_t phys_addr;
685
dma_pagetable_entry entry;
695
ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
699
/* Get DMA translation table entry */
700
index = addr / DMA_PAGESIZE;
701
if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
704
entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
705
/* XXX: not sure. should we really use only lowest bits? */
706
entry_addr &= 0x7fffffff;
707
cpu_physical_memory_read(entry_addr, &entry, sizeof(entry));
709
/* Read/write data at right place */
710
phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
711
cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
718
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
720
rc4030State *s = opaque;
721
target_phys_addr_t dma_addr;
724
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
726
/* Check DMA channel consistency */
727
dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
728
if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
729
(is_write != dev_to_mem)) {
730
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
731
s->nmi_interrupt |= 1 << n;
735
/* Get start address and len */
736
if (len > s->dma_regs[n][DMA_REG_COUNT])
737
len = s->dma_regs[n][DMA_REG_COUNT];
738
dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
740
/* Read/write data at right place */
741
rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
743
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
744
s->dma_regs[n][DMA_REG_COUNT] -= len;
746
#ifdef DEBUG_RC4030_DMA
749
printf("rc4030 dma: Copying %d bytes %s host %p\n",
750
len, is_write ? "from" : "to", buf);
751
for (i = 0; i < len; i += 16) {
756
for (j = 0; j < n; j++)
757
printf("%02x ", buf[i + j]);
761
for (j = 0; j < n; j++)
762
printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
769
struct rc4030DMAState {
774
void rc4030_dma_read(void *dma, uint8_t *buf, int len)
777
rc4030_do_dma(s->opaque, s->n, buf, len, 0);
780
void rc4030_dma_write(void *dma, uint8_t *buf, int len)
783
rc4030_do_dma(s->opaque, s->n, buf, len, 1);
786
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
789
struct rc4030DMAState *p;
792
s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
793
p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
794
for (i = 0; i < n; i++) {
803
void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
804
qemu_irq **irqs, rc4030_dma **dmas)
807
int s_chipset, s_jazzio;
809
s = qemu_mallocz(sizeof(rc4030State));
811
*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
812
*dmas = rc4030_allocate_dmas(s, 4);
814
s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s);
815
s->timer_irq = timer;
816
s->jazz_bus_irq = jazz_bus;
818
qemu_register_reset(rc4030_reset, s);
819
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
822
s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s,
823
DEVICE_NATIVE_ENDIAN);
824
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
825
s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s,
826
DEVICE_NATIVE_ENDIAN);
827
cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
added
removed
hw/rc4030.c
