2
* $XFree86: xc/programs/Xserver/hw/kdrive/igs/igsreg.c,v 1.1 2000/05/24 23:52:48 keithp Exp $
4
* Copyright � 2000 Keith Packard
6
* Permission to use, copy, modify, distribute, and sell this software and its
7
* documentation for any purpose is hereby granted without fee, provided that
8
* the above copyright notice appear in all copies and that both that
9
* copyright notice and this permission notice appear in supporting
10
* documentation, and that the name of Keith Packard not be used in
11
* advertising or publicity pertaining to distribution of the software without
12
* specific, written prior permission. Keith Packard makes no
13
* representations about the suitability of this software for any purpose. It
14
* is provided "as is" without express or implied warranty.
16
* KEITH PACKARD DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
17
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
18
* EVENT SHALL KEITH PACKARD BE LIABLE FOR ANY SPECIAL, INDIRECT OR
19
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
20
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
21
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
22
* PERFORMANCE OF THIS SOFTWARE.
28
#define CR00 IGS_CR+0x00
29
#define CR01 IGS_CR+0x01
30
#define CR02 IGS_CR+0x02
31
#define CR03 IGS_CR+0x03
32
#define CR04 IGS_CR+0x04
33
#define CR05 IGS_CR+0x05
34
#define CR06 IGS_CR+0x06
35
#define CR07 IGS_CR+0x07
36
#define CR08 IGS_CR+0x08
37
#define CR09 IGS_CR+0x09
38
#define CR0A IGS_CR+0x0A
39
#define CR0B IGS_CR+0x0B
40
#define CR0C IGS_CR+0x0C
41
#define CR0D IGS_CR+0x0D
42
#define CR0E IGS_CR+0x0E
43
#define CR0F IGS_CR+0x0F
44
#define CR10 IGS_CR+0x10
45
#define CR11 IGS_CR+0x11
46
#define CR12 IGS_CR+0x12
47
#define CR13 IGS_CR+0x13
48
#define CR14 IGS_CR+0x14
49
#define CR15 IGS_CR+0x15
50
#define CR16 IGS_CR+0x16
51
#define CR17 IGS_CR+0x17
52
#define CR18 IGS_CR+0x18
53
#define CR19 IGS_CR+0x19
54
#define CR1A IGS_CR+0x1A
55
#define CR1B IGS_CR+0x1B
56
#define CR1C IGS_CR+0x1C
57
#define CR1D IGS_CR+0x1D
58
#define CR1E IGS_CR+0x1E
59
#define CR1F IGS_CR+0x1F
60
#define CR20 IGS_CR+0x20
61
#define CR21 IGS_CR+0x21
62
#define CR22 IGS_CR+0x22
63
#define CR23 IGS_CR+0x23
64
#define CR24 IGS_CR+0x24
65
#define CR25 IGS_CR+0x25
66
#define CR26 IGS_CR+0x26
67
#define CR27 IGS_CR+0x27
68
#define CR28 IGS_CR+0x28
69
#define CR29 IGS_CR+0x29
70
#define CR2A IGS_CR+0x2A
71
#define CR2B IGS_CR+0x2B
72
#define CR2C IGS_CR+0x2C
73
#define CR2D IGS_CR+0x2D
74
#define CR2E IGS_CR+0x2E
75
#define CR2F IGS_CR+0x2F
76
#define CR30 IGS_CR+0x30
77
#define CR31 IGS_CR+0x31
78
#define CR32 IGS_CR+0x32
79
#define CR33 IGS_CR+0x33
80
#define CR34 IGS_CR+0x34
81
#define CR35 IGS_CR+0x35
82
#define CR36 IGS_CR+0x36
83
#define CR37 IGS_CR+0x37
84
#define CR38 IGS_CR+0x38
85
#define CR39 IGS_CR+0x39
86
#define CR3A IGS_CR+0x3A
87
#define CR3B IGS_CR+0x3B
88
#define CR3C IGS_CR+0x3C
89
#define CR3D IGS_CR+0x3D
90
#define CR3E IGS_CR+0x3E
91
#define CR3F IGS_CR+0x3F
92
#define CR40 IGS_CR+0x40
93
#define CR41 IGS_CR+0x41
94
#define CR42 IGS_CR+0x42
95
#define CR43 IGS_CR+0x43
96
#define CR44 IGS_CR+0x44
97
#define CR45 IGS_CR+0x45
98
#define CR46 IGS_CR+0x46
99
#define CR47 IGS_CR+0x47
100
#define CR48 IGS_CR+0x48
102
#define CR_FIRST CR00
105
#define SR00 IGS_SR+0x00
106
#define SR01 IGS_SR+0x01
107
#define SR02 IGS_SR+0x02
108
#define SR03 IGS_SR+0x03
109
#define SR04 IGS_SR+0x04
111
#define SR_FIRST SR00
114
#define AR00 IGS_AR+0x00
115
#define AR01 IGS_AR+0x01
116
#define AR02 IGS_AR+0x02
117
#define AR03 IGS_AR+0x03
118
#define AR04 IGS_AR+0x04
119
#define AR05 IGS_AR+0x05
120
#define AR06 IGS_AR+0x06
121
#define AR07 IGS_AR+0x07
122
#define AR08 IGS_AR+0x08
123
#define AR09 IGS_AR+0x09
124
#define AR0A IGS_AR+0x0A
125
#define AR0B IGS_AR+0x0B
126
#define AR0C IGS_AR+0x0C
127
#define AR0D IGS_AR+0x0D
128
#define AR0E IGS_AR+0x0E
129
#define AR0F IGS_AR+0x0F
130
#define AR10 IGS_AR+0x10
131
#define AR11 IGS_AR+0x11
132
#define AR12 IGS_AR+0x12
133
#define AR13 IGS_AR+0x13
134
#define AR14 IGS_AR+0x14
136
#define AR_FIRST AR00
139
#define GR00 IGS_GR+0x00
140
#define GR01 IGS_GR+0x01
141
#define GR02 IGS_GR+0x02
142
#define GR03 IGS_GR+0x03
143
#define GR04 IGS_GR+0x04
144
#define GR05 IGS_GR+0x05
145
#define GR06 IGS_GR+0x06
146
#define GR07 IGS_GR+0x07
147
#define GR08 IGS_GR+0x08
148
#define GR09 IGS_GR+0x09
149
#define GR0A IGS_GR+0x0A
150
#define GR0B IGS_GR+0x0B
151
#define GR0C IGS_GR+0x0C
152
#define GR0D IGS_GR+0x0D
153
#define GR0E IGS_GR+0x0E
154
#define GR0F IGS_GR+0x0F
155
#define GR10 IGS_GR+0x10
156
#define GR11 IGS_GR+0x11
157
#define GR12 IGS_GR+0x12
158
#define GR13 IGS_GR+0x13
159
#define GR14 IGS_GR+0x14
160
#define GR15 IGS_GR+0x15
161
#define GR16 IGS_GR+0x16
162
#define GR17 IGS_GR+0x17
163
#define GR18 IGS_GR+0x18
164
#define GR19 IGS_GR+0x19
165
#define GR1A IGS_GR+0x1A
166
#define GR1B IGS_GR+0x1B
167
#define GR1C IGS_GR+0x1C
168
#define GR1D IGS_GR+0x1D
169
#define GR1E IGS_GR+0x1E
170
#define GR1F IGS_GR+0x1F
171
#define GR20 IGS_GR+0x20
172
#define GR21 IGS_GR+0x21
173
#define GR22 IGS_GR+0x22
174
#define GR23 IGS_GR+0x23
175
#define GR24 IGS_GR+0x24
176
#define GR25 IGS_GR+0x25
177
#define GR26 IGS_GR+0x26
178
#define GR27 IGS_GR+0x27
179
#define GR28 IGS_GR+0x28
180
#define GR29 IGS_GR+0x29
181
#define GR2A IGS_GR+0x2A
182
#define GR2B IGS_GR+0x2B
183
#define GR2C IGS_GR+0x2C
184
#define GR2D IGS_GR+0x2D
185
#define GR2E IGS_GR+0x2E
186
#define GR2F IGS_GR+0x2F
187
#define GR30 IGS_GR+0x30
188
#define GR31 IGS_GR+0x31
189
#define GR32 IGS_GR+0x32
190
#define GR33 IGS_GR+0x33
191
#define GR34 IGS_GR+0x34
192
#define GR35 IGS_GR+0x35
193
#define GR36 IGS_GR+0x36
194
#define GR37 IGS_GR+0x37
195
#define GR38 IGS_GR+0x38
196
#define GR39 IGS_GR+0x39
197
#define GR3A IGS_GR+0x3A
198
#define GR3B IGS_GR+0x3B
199
#define GR3C IGS_GR+0x3C
200
#define GR3D IGS_GR+0x3D
201
#define GR3E IGS_GR+0x3E
202
#define GR3F IGS_GR+0x3F
203
#define GR40 IGS_GR+0x40
204
#define GR41 IGS_GR+0x41
205
#define GR42 IGS_GR+0x42
206
#define GR43 IGS_GR+0x43
207
#define GR44 IGS_GR+0x44
208
#define GR45 IGS_GR+0x45
209
#define GR46 IGS_GR+0x46
210
#define GR47 IGS_GR+0x47
211
#define GR48 IGS_GR+0x48
212
#define GR49 IGS_GR+0x49
213
#define GR4A IGS_GR+0x4A
214
#define GR4B IGS_GR+0x4B
215
#define GR4C IGS_GR+0x4C
216
#define GR4D IGS_GR+0x4D
217
#define GR4E IGS_GR+0x4E
218
#define GR4F IGS_GR+0x4F
219
#define GR50 IGS_GR+0x50
220
#define GR51 IGS_GR+0x51
221
#define GR52 IGS_GR+0x52
222
#define GR53 IGS_GR+0x53
223
#define GR54 IGS_GR+0x54
224
#define GR55 IGS_GR+0x55
225
#define GR56 IGS_GR+0x56
226
#define GR57 IGS_GR+0x57
227
#define GR58 IGS_GR+0x58
228
#define GR59 IGS_GR+0x59
229
#define GR5A IGS_GR+0x5A
230
#define GR5B IGS_GR+0x5B
231
#define GR5C IGS_GR+0x5C
232
#define GR5D IGS_GR+0x5D
233
#define GR5E IGS_GR+0x5E
234
#define GR5F IGS_GR+0x5F
235
#define GR60 IGS_GR+0x60
236
#define GR61 IGS_GR+0x61
237
#define GR62 IGS_GR+0x62
238
#define GR63 IGS_GR+0x63
239
#define GR64 IGS_GR+0x64
240
#define GR65 IGS_GR+0x65
241
#define GR66 IGS_GR+0x66
242
#define GR67 IGS_GR+0x67
243
#define GR68 IGS_GR+0x68
244
#define GR69 IGS_GR+0x69
245
#define GR6A IGS_GR+0x6A
246
#define GR6B IGS_GR+0x6B
247
#define GR6C IGS_GR+0x6C
248
#define GR6D IGS_GR+0x6D
249
#define GR6E IGS_GR+0x6E
250
#define GR6F IGS_GR+0x6F
251
#define GR70 IGS_GR+0x70
252
#define GR71 IGS_GR+0x71
253
#define GR72 IGS_GR+0x72
254
#define GR73 IGS_GR+0x73
255
#define GR74 IGS_GR+0x74
256
#define GR75 IGS_GR+0x75
257
#define GR76 IGS_GR+0x76
258
#define GR77 IGS_GR+0x77
259
#define GR78 IGS_GR+0x78
260
#define GR79 IGS_GR+0x79
261
#define GR7A IGS_GR+0x7A
262
#define GR7B IGS_GR+0x7B
263
#define GR7C IGS_GR+0x7C
264
#define GR7D IGS_GR+0x7D
265
#define GR7E IGS_GR+0x7E
266
#define GR7F IGS_GR+0x7F
267
#define GR80 IGS_GR+0x80
268
#define GR81 IGS_GR+0x81
269
#define GR82 IGS_GR+0x82
270
#define GR83 IGS_GR+0x83
271
#define GR84 IGS_GR+0x84
272
#define GR85 IGS_GR+0x85
273
#define GR86 IGS_GR+0x86
274
#define GR87 IGS_GR+0x87
275
#define GR88 IGS_GR+0x88
276
#define GR89 IGS_GR+0x89
277
#define GR8A IGS_GR+0x8A
278
#define GR8B IGS_GR+0x8B
279
#define GR8C IGS_GR+0x8C
280
#define GR8D IGS_GR+0x8D
281
#define GR8E IGS_GR+0x8E
282
#define GR8F IGS_GR+0x8F
283
#define GR90 IGS_GR+0x90
284
#define GR91 IGS_GR+0x91
285
#define GR92 IGS_GR+0x92
286
#define GR93 IGS_GR+0x93
287
#define GR94 IGS_GR+0x94
288
#define GR95 IGS_GR+0x95
289
#define GR96 IGS_GR+0x96
290
#define GR97 IGS_GR+0x97
291
#define GR98 IGS_GR+0x98
292
#define GR99 IGS_GR+0x99
293
#define GR9A IGS_GR+0x9A
294
#define GR9B IGS_GR+0x9B
295
#define GR9C IGS_GR+0x9C
296
#define GR9D IGS_GR+0x9D
297
#define GR9E IGS_GR+0x9E
298
#define GR9F IGS_GR+0x9F
299
#define GRA0 IGS_GR+0xA0
300
#define GRA1 IGS_GR+0xA1
301
#define GRA2 IGS_GR+0xA2
302
#define GRA3 IGS_GR+0xA3
303
#define GRA4 IGS_GR+0xA4
304
#define GRA5 IGS_GR+0xA5
305
#define GRA6 IGS_GR+0xA6
306
#define GRA7 IGS_GR+0xA7
307
#define GRA8 IGS_GR+0xA8
308
#define GRA9 IGS_GR+0xA9
309
#define GRAA IGS_GR+0xAA
310
#define GRAB IGS_GR+0xAB
311
#define GRAC IGS_GR+0xAC
312
#define GRAD IGS_GR+0xAD
313
#define GRAE IGS_GR+0xAE
314
#define GRAF IGS_GR+0xAF
315
#define GRB0 IGS_GR+0xB0
316
#define GRB1 IGS_GR+0xB1
317
#define GRB2 IGS_GR+0xB2
318
#define GRB3 IGS_GR+0xB3
319
#define GRB4 IGS_GR+0xB4
320
#define GRB5 IGS_GR+0xB5
321
#define GRB6 IGS_GR+0xB6
322
#define GRB7 IGS_GR+0xB7
323
#define GRB8 IGS_GR+0xB8
324
#define GRB9 IGS_GR+0xB9
325
#define GRBA IGS_GR+0xBA
326
#define GRBB IGS_GR+0xBB
327
#define GRBC IGS_GR+0xBC
328
#define GRBD IGS_GR+0xBD
329
#define GRBE IGS_GR+0xBE
330
#define GRBF IGS_GR+0xBF
332
#define GR_FIRST GR00
335
#define GREX3C IGS_GREX+(0x3c-IGS_GREXBASE)
337
VgaReg igs_h_total[] = {
342
VgaReg igs_h_de_end[] = {
347
VgaReg igs_h_bstart[] = {
352
VgaReg igs_h_bend[] = {
358
VgaReg igs_de_skew[] = {
363
VgaReg igs_ena_vr_access[] = {
368
VgaReg igs_h_rstart[] = {
373
VgaReg igs_h_rend[] = {
378
VgaReg igs_h_rdelay[] = {
383
VgaReg igs_v_total[] = {
391
VgaReg igs_v_rstart[] = {
399
VgaReg igs_v_rend[] = {
404
VgaReg igs_clear_v_int[] = {
409
VgaReg igs_disable_v_int[] = {
414
VgaReg igs_bandwidth[] = {
419
VgaReg igs_crt_protect[] = {
424
VgaReg igs_v_de_end[] = {
432
VgaReg igs_offset[] = {
438
VgaReg igs_v_bstart[] = {
446
VgaReg igs_v_bend[] = {
451
VgaReg igs_linecomp[] = {
459
VgaReg igs_ivideo[] = {
464
VgaReg igs_num_fetch[] = {
470
VgaReg igs_wcrt0[] = {
475
VgaReg igs_wcrt1[] = {
480
VgaReg igs_rcrts1[] = {
485
VgaReg igs_selwk[] = {
490
VgaReg igs_dot_clock_8[] = {
495
VgaReg igs_screen_off[] = {
500
VgaReg igs_enable_write_plane[] = {
505
VgaReg igs_mexhsyn[] = {
510
VgaReg igs_mexvsyn[] = {
515
VgaReg igs_pci_burst_write[] = {
520
VgaReg igs_pci_burst_read[] = {
525
VgaReg igs_iow_retry[] = {
530
VgaReg igs_mw_retry[] = {
535
VgaReg igs_mr_retry[] = {
542
VgaReg igs_biga22en[] = {
547
VgaReg igs_biga24en[] = {
552
VgaReg igs_biga22force[] = {
557
VgaReg igs_bigswap[] = {
562
/* #define IGS_BIGSWAP_8 0x3f */
563
/* #define IGS_BIGSWAP_16 0x2a */
564
/* #define IGS_BIGSWAP_32 0x00 */
566
VgaReg igs_sprite_x[] = {
572
VgaReg igs_sprite_preset_x[] = {
577
VgaReg igs_sprite_y[] = {
583
VgaReg igs_sprite_preset_y[] = {
588
VgaReg igs_sprite_visible[] = {
593
VgaReg igs_sprite_64x64[] = {
598
VgaReg igs_mgrext[] = {
603
VgaReg igs_hcshf[] = {
608
VgaReg igs_mbpfix[] = {
613
VgaReg igs_overscan_red[] = {
618
VgaReg igs_overscan_green[] = {
623
VgaReg igs_overscan_blue[] = {
628
VgaReg igs_memgopg[] = {
633
VgaReg igs_memr2wpg[] = {
638
VgaReg igs_crtff16[] = {
643
VgaReg igs_fifomust[] = {
648
VgaReg igs_fifogen[] = {
653
VgaReg igs_mode_sel[] = {
658
/* #define IGS_MODE_TEXT 0 */
659
/* #define IGS_MODE_8 1 */
660
/* #define IGS_MODE_565 2 */
661
/* #define IGS_MODE_5551 6 */
662
/* #define IGS_MODE_8888 3 */
663
/* #define IGS_MODE_888 4 */
664
/* #define IGS_MODE_332 9 */
665
/* #define IGS_MODE_4444 10 */
667
VgaReg igs_sprite_addr[] = {
673
VgaReg igs_fastmpie[] = {
678
VgaReg igs_vclk_m[] = {
684
VgaReg igs_vclk_n[] = {
690
VgaReg igs_vfsel[] = {
695
VgaReg igs_vclk_p[] = {
701
VgaReg igs_frqlat[] = {
707
VgaReg igs_dac_mask[] = {
712
VgaReg igs_dac_read_index[] = {
717
VgaReg igs_dac_write_index[] = {
722
VgaReg igs_dac_data[] = {
727
VgaReg igs_rampwdn[] = {
732
VgaReg igs_dac6_8[] = {
737
VgaReg igs_ramdacbypass[] = {
742
VgaReg igs_dacpwdn[] = {
747
VgaReg igs_cursor_read_index[] = {
752
VgaReg igs_cursor_write_index[] = {
757
VgaReg igs_cursor_data[] = {
763
_igsInb (VgaCard *card, VGA16 port)
768
return VgaReadMemb ((VGA32) card->closure + port);
770
return VgaInb (port);
774
_igsOutb (VgaCard *card, VGA8 value, VGA16 port)
777
VgaWriteMemb (value, (VGA32) card->closure + port);
779
VgaOutb (value, port);
783
_igsRegMap (VgaCard *card, VGA16 reg, VgaMap *map, VGABOOL write)
785
if (reg < IGS_SR + IGS_NSR)
787
map->access = VgaAccessIndIo;
791
map->index = reg - IGS_SR;
793
else if (reg < IGS_GR + IGS_NGR)
795
map->access = VgaAccessIndIo;
799
map->index = reg - IGS_GR;
801
else if (reg < IGS_GREX + IGS_NGREX)
805
map->access = VgaAccessDone;
806
_igsOutb (card, 0x33, 0x3ce);
807
gr33 = _igsInb (card, 0x3cf);
808
_igsOutb (card, gr33 | 0x40, 0x3cf);
809
_igsOutb (card, IGS_GREXBASE + reg - IGS_GREX, 0x3ce);
811
_igsOutb (card, map->value, 0x3cf);
813
map->value = _igsInb (card, 0x3cf);
814
_igsOutb (card, 0x33, 0x3ce);
815
_igsOutb (card, gr33, 0x3cf);
818
else if (reg < IGS_AR + IGS_NAR)
821
map->access = VgaAccessDone;
822
/* reset AFF to index */
823
(void) _igsInb (card, 0x3da);
826
_igsOutb (card, reg, 0x3c0);
828
_igsOutb (card, map->value, 0x3c0);
830
map->value = _igsInb (card, 0x3c1);
833
/* enable video display again */
834
(void) _igsInb (card, 0x3da);
835
_igsOutb (card, 0x20, 0x3c0);
839
else if (reg < IGS_CR + IGS_NCR)
841
map->access = VgaAccessIndIo;
845
map->index = reg - IGS_CR;
847
else if (reg < IGS_DAC + IGS_NDAC)
849
map->access = VgaAccessIo;
850
map->port = 0x3c6 + reg - IGS_DAC;
852
else if (reg < IGS_DACEX + IGS_NDACEX)
855
reg = 0x3c6 + reg - IGS_DACEX;
856
map->access = VgaAccessDone;
857
_igsOutb (card, 0x56, 0x3ce);
858
gr56 = _igsInb (card, 0x3cf);
859
_igsOutb (card, gr56 | 4, 0x3cf);
861
_igsOutb (card, map->value, reg);
863
map->value = _igsInb (card, reg);
864
_igsOutb (card, gr56, 0x3cf);
869
map->access = VgaAccessIo;
875
case IGS_INPUT_STATUS_1:
876
map->access = VgaAccessIo;
882
map->port = map->port + (VGA32) card->closure;
883
if (map->access == VgaAccessIo)
884
map->access = VgaAccessMem;
885
if (map->access == VgaAccessIndIo)
886
map->access = VgaAccessIndMem;
890
VgaSave igsSaves[] = {
894
IGS_MISC_OUT, IGS_MISC_OUT,
899
igsRegInit (IgsVga *igsvga, VGAVOL8 *mmio)
901
igsvga->card.map = _igsRegMap;
902
igsvga->card.closure = (void *) mmio;
903
igsvga->card.max = IGS_NREG;
904
igsvga->card.values = igsvga->values;
905
igsvga->card.saves = igsSaves;
909
igsSave (IgsVga *igsvga)
911
igsSetImm (igsvga, igs_wcrt0, 1);
912
igsSetImm (igsvga, igs_wcrt1, 1);
913
igsSetImm (igsvga, igs_rcrts1, 1);
914
igsSetImm (igsvga, igs_selwk, 1);
915
VgaPreserve (&igsvga->card);
919
igsReset (IgsVga *igsvga)
921
VgaRestore (&igsvga->card);
922
igsSetImm (igsvga, igs_frqlat, 0);
923
igsSetImm (igsvga, igs_frqlat, 1);
924
igsSetImm (igsvga, igs_frqlat, 0);
925
VgaFinish (&igsvga->card);
929
igsRegName(char *buf, VGA16 reg)
931
if (reg < IGS_SR + IGS_NSR)
933
sprintf (buf, " SR%02X", reg - IGS_SR);
935
else if (reg < IGS_GR + IGS_NGR)
937
sprintf (buf, " GR%02X", reg - IGS_GR);
939
else if (reg < IGS_GREX + IGS_NGREX)
941
sprintf (buf, " GRX%02X", reg - IGS_GREX + IGS_GREXBASE);
943
else if (reg < IGS_AR + IGS_NAR)
945
sprintf (buf, " AR%02X", reg - IGS_AR);
947
else if (reg < IGS_CR + IGS_NCR)
949
sprintf (buf, " CR%02X", reg - IGS_CR);
951
else if (reg < IGS_DAC + IGS_NDAC)
953
sprintf (buf, " DAC%02X", reg - IGS_DAC);
955
else if (reg < IGS_DACEX + IGS_NDACEX)
957
sprintf (buf, "DACX%02X", reg - IGS_DACEX);
961
sprintf (buf, "MISC_O");
963
case IGS_INPUT_STATUS_1:
964
sprintf (buf, "IN_S_1");