2
* Copyright 1998 by Alan Hourihane, Wigan, England.
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Alan Hourihane not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Alan Hourihane makes no representations
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* about the suitability of this software for any purpose. It is provided
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* "as is" without express or implied warranty.
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* ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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* Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
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* Modified from IBM.c to support TI RAMDAC routines
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* by Jens Owen, <jens@tungstengraphics.com>.
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/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TI.c,v 1.7 2003/02/17 16:08:29 dawes Exp $ */
30
#include "xf86_OSproc.h"
31
#include "xf86_ansic.h"
33
#include "xf86Cursor.h"
35
#define INIT_TI_RAMDAC_INFO
37
#include "xf86RamDacPriv.h"
39
/* The following values are in kHz */
40
#define TI_MIN_VCO_FREQ 110000
41
#define TI_MAX_VCO_FREQ 220000
44
TIramdacCalculateMNPForClock(
45
unsigned long RefClock, /* In 100Hz units */
46
unsigned long ReqClock, /* In 100Hz units */
47
char IsPixClock, /* boolean, is this the pixel or the sys clock */
48
unsigned long MinClock, /* Min VCO rating */
49
unsigned long MaxClock, /* Max VCO rating */
50
unsigned long *rM, /* M Out */
51
unsigned long *rN, /* N Out */
52
unsigned long *rP /* Min P In, P Out */
56
unsigned long best_m = 0, best_n = 0;
57
double VCO, IntRef = (double)RefClock;
58
double m_err, inc_m, calc_m;
59
unsigned long ActualClock;
61
/* Make sure that MinClock <= ReqClock <= MaxClock */
62
if ( ReqClock < MinClock)
64
if ( ReqClock > MaxClock )
68
* ActualClock = VCO / 2 ^ p
69
* Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ
70
* Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
71
* we don't have to bother checking for this maximum limit.
73
VCO = (double)ReqClock;
74
for ( p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
78
* We avoid doing multiplications by ( 65 - n ),
79
* and add an increment instead - this keeps any error small.
81
inc_m = VCO / ( IntRef * 8.0 );
83
/* Initial value of calc_m for the loop */
84
calc_m = inc_m + inc_m + inc_m;
86
/* Initial amount of error for an integer - impossibly large */
89
/* Search for the closest INTEGER value of ( 65 - m ) */
90
for ( n = 3; n <= 25; ( n )++, calc_m += inc_m ) {
92
/* Ignore values of ( 65 - m ) which we can't use */
93
if ( calc_m < 3.0 || calc_m > 64.0 )
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* Pick the closest INTEGER (has smallest fractional part).
98
* The optimizer should clean this up for us.
100
if (( calc_m - ( int ) calc_m ) < m_err ) {
101
m_err = calc_m - ( int ) calc_m;
102
best_m = ( int ) calc_m;
107
/* 65 - ( 65 - x ) = x */
112
/* Now all the calculations can be completed */
113
VCO = 8.0 * IntRef * best_m / best_n;
114
ActualClock = VCO / ( 1 << p );
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ErrorF( "f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
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ActualClock, VCO, *rN, *rM, *rP);
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return (ActualClock);
125
TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
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RamDacRegRecPtr ramdacReg)
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unsigned long status;
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/* Here we pass a short, so that we can evaluate a mask too
132
* So that the mask is the high byte and the data the low byte
135
TIRESTORE(TIDAC_latch_ctrl);
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TIRESTORE(TIDAC_true_color_ctrl);
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TIRESTORE(TIDAC_multiplex_ctrl);
138
TIRESTORE(TIDAC_clock_select);
139
TIRESTORE(TIDAC_palette_page);
140
TIRESTORE(TIDAC_general_ctrl);
141
TIRESTORE(TIDAC_misc_ctrl);
142
/* 0x2A & 0x2B are reserved */
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TIRESTORE(TIDAC_key_over_low);
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TIRESTORE(TIDAC_key_over_high);
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TIRESTORE(TIDAC_key_red_low);
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TIRESTORE(TIDAC_key_red_high);
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TIRESTORE(TIDAC_key_green_low);
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TIRESTORE(TIDAC_key_green_high);
149
TIRESTORE(TIDAC_key_blue_low);
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TIRESTORE(TIDAC_key_blue_high);
151
TIRESTORE(TIDAC_key_ctrl);
152
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x30);
153
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x38);
154
TIRESTORE(TIDAC_clock_ctrl);
155
TIRESTORE(TIDAC_sense_test);
156
TIRESTORE(TIDAC_ind_curs_ctrl);
158
/* only restore clocks if they were valid to begin with */
160
if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
161
/* Reset pixel clock */
162
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
163
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
165
/* Restore N, M & P values for pixel clocks */
166
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
167
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
168
ramdacReg->DacRegs[TIDAC_PIXEL_N]);
169
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
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ramdacReg->DacRegs[TIDAC_PIXEL_M]);
171
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
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ramdacReg->DacRegs[TIDAC_PIXEL_P]);
174
/* wait for pixel clock to lock */
177
status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
178
} while ((!(status & 0x40)) && (--i));
179
if (!(status & 0x40)) {
180
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
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"Pixel clock setup timed out\n");
186
if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
187
/* Reset loop clock */
188
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
189
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
191
/* Restore N, M & P values for pixel clocks */
192
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
193
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
194
ramdacReg->DacRegs[TIDAC_LOOP_N]);
195
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
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ramdacReg->DacRegs[TIDAC_LOOP_M]);
197
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
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ramdacReg->DacRegs[TIDAC_LOOP_P]);
200
/* wait for loop clock to lock */
203
status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
204
} while ((!(status & 0x40)) && (--i));
205
if (!(status & 0x40)) {
206
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
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"Loop clock setup timed out\n");
212
/* restore palette */
213
(*ramdacPtr->WriteAddress)(pScrn, 0);
216
(*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
218
(*ramdacPtr->WriteData)(pScrn, 0);
219
(*ramdacPtr->WriteData)(pScrn, 0);
220
(*ramdacPtr->WriteData)(pScrn, 0);
222
(*ramdacPtr->WriteData)(pScrn, 0xff);
227
TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
228
RamDacRegRecPtr ramdacReg)
232
(*ramdacPtr->ReadAddress)(pScrn, 0);
234
ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
236
/* Read back N,M and P values for pixel clock */
237
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
238
ramdacReg->DacRegs[TIDAC_PIXEL_N] =
239
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
240
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
241
ramdacReg->DacRegs[TIDAC_PIXEL_M] =
242
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
243
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
244
ramdacReg->DacRegs[TIDAC_PIXEL_P] =
245
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
247
/* Read back N,M and P values for loop clock */
248
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
249
ramdacReg->DacRegs[TIDAC_LOOP_N] =
250
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
251
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
252
ramdacReg->DacRegs[TIDAC_LOOP_M] =
253
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
254
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
255
ramdacReg->DacRegs[TIDAC_LOOP_P] =
256
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
258
/* Order is important */
259
TISAVE(TIDAC_latch_ctrl);
260
TISAVE(TIDAC_true_color_ctrl);
261
TISAVE(TIDAC_multiplex_ctrl);
262
TISAVE(TIDAC_clock_select);
263
TISAVE(TIDAC_palette_page);
264
TISAVE(TIDAC_general_ctrl);
265
TISAVE(TIDAC_misc_ctrl);
266
/* 0x2A & 0x2B are reserved */
267
TISAVE(TIDAC_key_over_low);
268
TISAVE(TIDAC_key_over_high);
269
TISAVE(TIDAC_key_red_low);
270
TISAVE(TIDAC_key_red_high);
271
TISAVE(TIDAC_key_green_low);
272
TISAVE(TIDAC_key_green_high);
273
TISAVE(TIDAC_key_blue_low);
274
TISAVE(TIDAC_key_blue_high);
275
TISAVE(TIDAC_key_ctrl);
276
TISAVE(TIDAC_clock_ctrl);
277
TISAVE(TIDAC_sense_test);
278
TISAVE(TIDAC_ind_curs_ctrl);
282
TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
284
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
285
RamDacHelperRecPtr ramdacHelperPtr = NULL;
286
Bool RamDacIsSupported = FALSE;
287
int TIramdac_ID = -1;
289
unsigned char id, rev, rev2, id2;
291
/* read ID and revision */
292
rev = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
293
id = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
295
/* check if ID and revision are read only */
296
(*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, TIDAC_rev);
297
(*ramdacPtr->WriteDAC)(pScrn, ~id, 0, TIDAC_id);
298
rev2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
299
id2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
302
case TIDAC_TVP_3030_ID:
303
if (id == id2 && rev == rev2) /* check for READ ONLY */
304
TIramdac_ID = TI3030_RAMDAC;
306
case TIDAC_TVP_3026_ID:
307
if (id == id2 && rev == rev2) /* check for READ ONLY */
308
TIramdac_ID = TI3026_RAMDAC;
312
(*ramdacPtr->WriteDAC)(pScrn, rev, 0, TIDAC_rev);
313
(*ramdacPtr->WriteDAC)(pScrn, id, 0, TIDAC_id);
315
if (TIramdac_ID == -1) {
316
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
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"Cannot determine TI RAMDAC type, aborting\n");
320
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
321
"Attached RAMDAC is %s\n", TIramdacDeviceInfo[TIramdac_ID&0xFFFF]);
324
for (i=0;ramdacs[i].token != -1;i++) {
325
if (ramdacs[i].token == TIramdac_ID)
326
RamDacIsSupported = TRUE;
329
if (!RamDacIsSupported) {
330
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
331
"This TI RAMDAC is NOT supported by this driver, aborting\n");
335
ramdacHelperPtr = RamDacHelperCreateInfoRec();
336
switch (TIramdac_ID) {
338
ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
339
ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
342
ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
343
ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
346
ramdacPtr->RamDacType = TIramdac_ID;
347
ramdacHelperPtr->RamDacType = TIramdac_ID;
348
ramdacHelperPtr->Save = TIramdacSave;
349
ramdacHelperPtr->Restore = TIramdacRestore;
351
return ramdacHelperPtr;
355
TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
357
switch (pScrn->bitsPerPixel) {
359
/* order is important */
360
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
361
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
362
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
363
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
364
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
365
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
366
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
367
/* 0x2A & 0x2B are reserved */
368
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
369
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
370
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
371
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
372
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
373
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
374
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
375
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
376
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
377
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
378
if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
379
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
380
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
381
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
383
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
386
/* order is important */
387
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
388
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
389
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
390
ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
391
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
392
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
393
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
394
/* 0x2A & 0x2B are reserved */
395
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
396
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
397
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
398
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
399
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
400
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
401
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
402
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
403
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
404
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
405
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
408
/* order is important */
410
/* Matrox driver uses this */
411
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
413
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
415
if (pScrn->depth == 16) {
416
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
418
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
421
/* Matrox driver uses this */
422
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
423
ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
424
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
425
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
427
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
428
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
429
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
430
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
432
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
433
/* 0x2A & 0x2B are reserved */
434
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
435
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
436
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
437
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
438
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
439
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
440
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
441
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
442
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
443
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
444
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
447
/* order is important */
448
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
449
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
450
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
451
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
452
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
453
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
454
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
455
/* 0x2A & 0x2B are reserved */
456
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
457
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
458
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
459
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
460
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
461
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
462
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
463
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
464
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
465
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
466
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
472
TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
474
switch (pScrn->bitsPerPixel) {
476
/* order is important */
477
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
478
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
479
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
480
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
481
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
482
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
483
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
484
/* 0x2A & 0x2B are reserved */
485
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
486
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
487
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
488
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
489
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
490
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
491
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
492
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
493
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
494
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
495
if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
496
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
497
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
498
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
500
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
503
/* order is important */
504
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
505
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
506
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
507
ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
508
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
509
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
510
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
511
/* 0x2A & 0x2B are reserved */
512
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
513
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
514
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
515
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
516
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
517
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
518
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
519
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
520
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
521
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
522
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
525
/* order is important */
527
/* Matrox driver uses this */
528
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
530
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
532
if (pScrn->depth == 16) {
533
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
535
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
538
/* Matrox driver uses this */
539
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
540
ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
541
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
542
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
544
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
545
ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
546
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
547
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
549
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
550
/* 0x2A & 0x2B are reserved */
551
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
552
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
553
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
554
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
555
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
556
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
557
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
558
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
559
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
560
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
561
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
564
/* order is important */
565
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
566
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
567
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
568
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
569
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
570
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
571
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
572
/* 0x2A & 0x2B are reserved */
573
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
574
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
575
ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
576
ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
577
ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
578
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
579
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
580
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
581
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
582
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
583
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
589
TIramdacShowCursor(ScrnInfoPtr pScrn)
591
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
593
/* Enable cursor - X11 mode */
594
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
598
TIramdacHideCursor(ScrnInfoPtr pScrn)
600
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
602
/* Disable cursor - X11 mode */
603
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
607
TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
609
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
614
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
615
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
616
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
617
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
621
TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
623
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
625
/* Background color */
626
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
627
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x00ff0000) >> 16));
628
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x0000ff00) >> 8));
629
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (bg&0x000000ff) );
631
/* Foreground color */
632
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
633
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x00ff0000) >> 16));
634
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x0000ff00) >> 8));
635
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (fg&0x000000ff) );
639
TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
641
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
645
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
646
/* reset cursor RAM load address A7..A0 */
647
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_INDEX, 0x00, 0x00);
650
/* NOT_DONE: might need a delay here */
651
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
656
TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
662
TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
664
infoPtr->MaxWidth = 64;
665
infoPtr->MaxHeight = 64;
666
infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
667
HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
668
HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
669
infoPtr->SetCursorColors = TIramdacSetCursorColors;
670
infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
671
infoPtr->LoadCursorImage = TIramdacLoadCursorImage;
672
infoPtr->HideCursor = TIramdacHideCursor;
673
infoPtr->ShowCursor = TIramdacShowCursor;
674
infoPtr->UseHWCursor = TIramdacUseHWCursor;
677
void TIramdacLoadPalette(
684
RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
687
if (pScrn->depth == 16) {
688
for(i = 0; i < numColors; i++) {
690
(*hwp->WriteAddress)(pScrn, index << 2);
691
(*hwp->WriteData)(pScrn, colors[index >> 1].red);
692
(*hwp->WriteData)(pScrn, colors[index].green);
693
(*hwp->WriteData)(pScrn, colors[index >> 1].blue);
696
(*hwp->WriteAddress)(pScrn, index << 3);
697
(*hwp->WriteData)(pScrn, colors[index].red);
698
(*hwp->WriteData)(pScrn, colors[(index << 1) + 1].green);
699
(*hwp->WriteData)(pScrn, colors[index].blue);
703
shift = (pScrn->depth == 15) ? 3 : 0;
705
for(i = 0; i < numColors; i++) {
707
(*hwp->WriteAddress)(pScrn, index << shift);
708
(*hwp->WriteData)(pScrn, colors[index].red);
709
(*hwp->WriteData)(pScrn, colors[index].green);
710
(*hwp->WriteData)(pScrn, colors[index].blue);