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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.4 2002/10/30 12:52:13 alanh Exp $ */
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
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* VA Linux Systems Inc., Fremont, California.
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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* Kevin E. Martin <martin@xfree86.org>
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* Rickard E. Faith <faith@valinux.com>
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#include "radeon_common.h"
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/* DRI Driver defaults */
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#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
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#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM
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#define RADEON_DEFAULT_AGP_MODE 1
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#define RADEON_DEFAULT_AGP_FAST_WRITE 0
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#define RADEON_DEFAULT_AGP_SIZE 8 /* MB (must be 2^n and > 4MB) */
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#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */
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#define RADEON_AGP_MAX_MODE 4
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#define RADEON_CARD_TYPE_RADEON 1
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/* Buffer are aligned on 4096 byte boundaries */
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#define RADEON_BUFFER_ALIGN 0x00000fff
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#define RADEONCP_USE_RING_BUFFER(m) \
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(((m) == RADEON_CSQ_PRIBM_INDDIS) || \
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((m) == RADEON_CSQ_PRIBM_INDBM))
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/* DRI screen private data */
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int deviceID; /* PCI device ID */
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int width; /* Width in pixels of display */
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int height; /* Height in scanlines of display */
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int depth; /* Depth of display (8, 15, 16, 24) */
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int bpp; /* Bit depth of display (8, 16, 24, 32) */
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int IsPCI; /* Current card is a PCI card */
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int frontOffset; /* Start of front buffer */
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int backOffset; /* Start of shared back buffer */
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int depthOffset; /* Start of shared depth buffer */
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int textureOffset;/* Start of texture data in frame buffer */
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/* MMIO register data */
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drmHandle registerHandle;
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/* CP in-memory status information */
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drmHandle statusHandle;
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/* CP AGP Texture data */
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drmHandle agpTexHandle;
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drmSize agpTexMapSize;
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unsigned int sarea_priv_offset;
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#ifdef PER_CONTEXT_SAREA
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drmSize perctx_sarea_size;
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} RADEONDRIRec, *RADEONDRIPtr;