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Viewing changes to unix/xc/programs/Xserver/hw/xfree86/ramdac/IBM.h

  • Committer: Bazaar Package Importer
  • Author(s): Ola Lundqvist
  • Date: 2006-05-15 20:35:17 UTC
  • mfrom: (1.1.2 upstream)
  • Revision ID: james.westby@ubuntu.com-20060515203517-l4lre1ku942mn26k
Tags: 4.1.1+X4.3.0-10
* Correction of critical security issue. Thanks to Martin Kogler
  <e9925248@student.tuwien.ac.at> that informed me about the issue,
  and provided the patch.
  This flaw was originally found by Steve Wiseman of intelliadmin.com.
* Applied patch from Javier Kohen <jkohen@users.sourceforge.net> that
  inform the user that only 8 first characters of the password will
  actually be used when typing more than 8 characters, closes:
  #355619.

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unix/xc/programs/Xserver/hw/xfree86/ramdac/IBM.h
 
1
/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/IBM.h,v 1.8 2001/10/28 03:34:03 tsi Exp $ */
 
2
 
 
3
#include <xf86RamDac.h>
 
4
 
 
5
RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
 
6
void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
 
7
void IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
 
8
void IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
 
9
void IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
 
10
unsigned long IBMramdac526CalculateMNPCForClock(unsigned long RefClock,
 
11
    unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
 
12
    unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
 
13
    unsigned long *rP, unsigned long *rC);
 
14
unsigned long IBMramdac640CalculateMNPCForClock(unsigned long RefClock,
 
15
    unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
 
16
    unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
 
17
    unsigned long *rP, unsigned long *rC);
 
18
void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr);
 
19
void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr);
 
20
 
 
21
#define IBM524_RAMDAC           ((VENDOR_IBM << 16) | 0x00)
 
22
#define IBM524A_RAMDAC          ((VENDOR_IBM << 16) | 0x01)
 
23
#define IBM525_RAMDAC           ((VENDOR_IBM << 16) | 0x02)
 
24
#define IBM526_RAMDAC           ((VENDOR_IBM << 16) | 0x03)
 
25
#define IBM526DB_RAMDAC         ((VENDOR_IBM << 16) | 0x04)
 
26
#define IBM528_RAMDAC           ((VENDOR_IBM << 16) | 0x05)
 
27
#define IBM528A_RAMDAC          ((VENDOR_IBM << 16) | 0x06)
 
28
#define IBM624_RAMDAC           ((VENDOR_IBM << 16) | 0x07)
 
29
#define IBM624DB_RAMDAC         ((VENDOR_IBM << 16) | 0x08)
 
30
#define IBM640_RAMDAC           ((VENDOR_IBM << 16) | 0x09)
 
31
 
 
32
/*
 
33
 * IBM Ramdac registers
 
34
 */
 
35
 
 
36
#define IBMRGB_REF_FREQ_1       14.31818
 
37
#define IBMRGB_REF_FREQ_2       50.00000
 
38
 
 
39
#define IBMRGB_rev              0x00
 
40
#define IBMRGB_id               0x01
 
41
#define IBMRGB_misc_clock       0x02
 
42
#define IBMRGB_sync             0x03
 
43
#define IBMRGB_hsync_pos        0x04
 
44
#define IBMRGB_pwr_mgmt         0x05
 
45
#define IBMRGB_dac_op           0x06
 
46
#define IBMRGB_pal_ctrl         0x07
 
47
#define IBMRGB_sysclk           0x08  /* not RGB525 */
 
48
#define IBMRGB_pix_fmt          0x0a
 
49
#define IBMRGB_8bpp             0x0b
 
50
#define IBMRGB_16bpp            0x0c
 
51
#define IBMRGB_24bpp            0x0d
 
52
#define IBMRGB_32bpp            0x0e
 
53
#define IBMRGB_pll_ctrl1        0x10
 
54
#define IBMRGB_pll_ctrl2        0x11
 
55
#define IBMRGB_pll_ref_div_fix  0x14
 
56
#define IBMRGB_sysclk_ref_div   0x15  /* not RGB525 */
 
57
#define IBMRGB_sysclk_vco_div   0x16  /* not RGB525 */
 
58
/* #define IBMRGB_f0            0x20 */
 
59
 
 
60
#define IBMRGB_sysclk_n         0x15
 
61
#define IBMRGB_sysclk_m         0x16
 
62
#define IBMRGB_sysclk_p         0x17
 
63
#define IBMRGB_sysclk_c         0x18
 
64
 
 
65
#define IBMRGB_m0               0x20
 
66
#define IBMRGB_n0               0x21
 
67
#define IBMRGB_p0               0x22
 
68
#define IBMRGB_c0               0x23
 
69
#define IBMRGB_m1               0x24
 
70
#define IBMRGB_n1               0x25
 
71
#define IBMRGB_p1               0x26
 
72
#define IBMRGB_c1               0x27
 
73
#define IBMRGB_m2               0x28
 
74
#define IBMRGB_n2               0x29
 
75
#define IBMRGB_p2               0x2a
 
76
#define IBMRGB_c2               0x2b
 
77
#define IBMRGB_m3               0x2c
 
78
#define IBMRGB_n3               0x2d
 
79
#define IBMRGB_p3               0x2e
 
80
#define IBMRGB_c3               0x2f
 
81
 
 
82
#define IBMRGB_curs             0x30
 
83
#define IBMRGB_curs_xl          0x31
 
84
#define IBMRGB_curs_xh          0x32
 
85
#define IBMRGB_curs_yl          0x33
 
86
#define IBMRGB_curs_yh          0x34
 
87
#define IBMRGB_curs_hot_x       0x35
 
88
#define IBMRGB_curs_hot_y       0x36
 
89
#define IBMRGB_curs_col1_r      0x40
 
90
#define IBMRGB_curs_col1_g      0x41
 
91
#define IBMRGB_curs_col1_b      0x42
 
92
#define IBMRGB_curs_col2_r      0x43
 
93
#define IBMRGB_curs_col2_g      0x44
 
94
#define IBMRGB_curs_col2_b      0x45
 
95
#define IBMRGB_curs_col3_r      0x46
 
96
#define IBMRGB_curs_col3_g      0x47
 
97
#define IBMRGB_curs_col3_b      0x48
 
98
#define IBMRGB_border_col_r     0x60
 
99
#define IBMRGB_border_col_g     0x61
 
100
#define IBMRGB_botder_col_b     0x62
 
101
#define IBMRGB_key              0x68
 
102
#define IBMRGB_key_mask         0x6C
 
103
#define IBMRGB_misc1            0x70
 
104
#define IBMRGB_misc2            0x71
 
105
#define IBMRGB_misc3            0x72
 
106
#define IBMRGB_misc4            0x73  /* not RGB525 */
 
107
#define IBMRGB_key_control      0x78
 
108
#define IBMRGB_dac_sense        0x82
 
109
#define IBMRGB_misr_r           0x84
 
110
#define IBMRGB_misr_g           0x86
 
111
#define IBMRGB_misr_b           0x88
 
112
#define IBMRGB_pll_vco_div_in   0x8e
 
113
#define IBMRGB_pll_ref_div_in   0x8f
 
114
#define IBMRGB_vram_mask_0      0x90
 
115
#define IBMRGB_vram_mask_1      0x91
 
116
#define IBMRGB_vram_mask_2      0x92
 
117
#define IBMRGB_vram_mask_3      0x93
 
118
#define IBMRGB_curs_array       0x100
 
119
 
 
120
 
 
121
 
 
122
/* Constants rgb525.h */  
 
123
 
 
124
/* RGB525_REVISION_LEVEL */
 
125
#define RGB525_PRODUCT_REV_LEVEL        0xf0
 
126
 
 
127
/* RGB525_ID */
 
128
#define RGB525_PRODUCT_ID               0x01
 
129
 
 
130
/* RGB525_MISC_CTRL_1 */
 
131
#define MISR_CNTL_ENABLE                0x80
 
132
#define VMSK_CNTL_ENABLE                0x40
 
133
#define PADR_RDMT_RDADDR                0x0
 
134
#define PADR_RDMT_PAL_STATE             0x20
 
135
#define SENS_DSAB_DISABLE               0x10
 
136
#define SENS_SEL_BIT3                   0x0
 
137
#define SENS_SEL_BIT7                   0x08
 
138
#define VRAM_SIZE_32                    0x0
 
139
#define VRAM_SIZE_64                    0x01
 
140
 
 
141
/* RGB525_MISC_CTRL_2 */
 
142
#define PCLK_SEL_LCLK                   0x0
 
143
#define PCLK_SEL_PLL                    0x40
 
144
#define PCLK_SEL_EXT                    0x80
 
145
#define INTL_MODE_ENABLE                0x20
 
146
#define BLANK_CNTL_ENABLE               0x10
 
147
#define COL_RES_6BIT                    0x0
 
148
#define COL_RES_8BIT                    0x04
 
149
#define PORT_SEL_VGA                    0x0
 
150
#define PORT_SEL_VRAM                   0x01
 
151
 
 
152
/* RGB525_MISC_CTRL_3 */
 
153
#define SWAP_RB                         0x80
 
154
#define SWAP_WORD_LOHI                  0x0
 
155
#define SWAP_WORD_HILO                  0x10
 
156
#define SWAP_NIB_HILO                   0x0
 
157
#define SWAP_NIB_LOHI                   0x02
 
158
 
 
159
/* RGB525_MISC_CLK_CTRL */
 
160
#define DDOT_CLK_ENABLE                 0x0
 
161
#define DDOT_CLK_DISABLE                0x80
 
162
#define SCLK_ENABLE                     0x0
 
163
#define SCLK_DISABLE                    0x40
 
164
#define B24P_DDOT_PLL                   0x0
 
165
#define B24P_DDOT_SCLK                  0x20
 
166
#define DDOT_DIV_PLL_1                  0x0
 
167
#define DDOT_DIV_PLL_2                  0x02
 
168
#define DDOT_DIV_PLL_4                  0x04
 
169
#define DDOT_DIV_PLL_8                  0x06
 
170
#define DDOT_DIV_PLL_16                 0x08
 
171
#define PLL_DISABLE                     0x0
 
172
#define PLL_ENABLE                      0x01
 
173
 
 
174
/* RGB525_SYNC_CTRL */
 
175
#define DLY_CNTL_ADD                    0x0
 
176
#define DLY_SYNC_NOADD                  0x80
 
177
#define CSYN_INVT_DISABLE               0x0
 
178
#define CSYN_INVT_ENABLE                0x40
 
179
#define VSYN_INVT_DISABLE               0x0
 
180
#define VSYN_INVT_ENABLE                0x20
 
181
#define HSYN_INVT_DISABLE               0x0
 
182
#define HSYN_INVT_ENABLE                0x10
 
183
#define VSYN_CNTL_NORMAL                0x0
 
184
#define VSYN_CNTL_HIGH                  0x04
 
185
#define VSYN_CNTL_LOW                   0x08
 
186
#define VSYN_CNTL_DISABLE               0x0C
 
187
#define HSYN_CNTL_NORMAL                0x0
 
188
#define HSYN_CNTL_HIGH                  0x01
 
189
#define HSYN_CNTL_LOW                   0x02
 
190
#define HSYN_CNTL_DISABLE               0x03
 
191
 
 
192
/* RGB525_HSYNC_CTRL */
 
193
#define HSYN_POS(n)                     (n)
 
194
 
 
195
/* RGB525_POWER_MANAGEMENT */
 
196
#define SCLK_PWR_NORMAL                 0x0
 
197
#define SCLK_PWR_DISABLE                0x10
 
198
#define DDOT_PWR_NORMAL                 0x0
 
199
#define DDOT_PWR_DISABLE                0x08
 
200
#define SYNC_PWR_NORMAL                 0x0
 
201
#define SYNC_PWR_DISABLE                0x04
 
202
#define ICLK_PWR_NORMAL                 0x0
 
203
#define ICLK_PWR_DISABLE                0x02
 
204
#define DAC_PWR_NORMAL                  0x0
 
205
#define DAC_PWR_DISABLE                 0x01
 
206
 
 
207
/* RGB525_DAC_OPERATION */
 
208
#define SOG_DISABLE                     0x0
 
209
#define SOG_ENABLE                      0x08
 
210
#define BRB_NORMAL                      0x0
 
211
#define BRB_ALWAYS                      0x04
 
212
#define DSR_DAC_SLOW                    0x02
 
213
#define DSR_DAC_FAST                    0x0
 
214
#define DPE_DISABLE                     0x0
 
215
#define DPE_ENABLE                      0x01
 
216
 
 
217
/* RGB525_PALETTE_CTRL */
 
218
#define SIXBIT_LINEAR_ENABLE            0x0
 
219
#define SIXBIT_LINEAR_DISABLE           0x80
 
220
#define PALETTE_PARITION(n)             (n)
 
221
 
 
222
/* RGB525_PIXEL_FORMAT */
 
223
#define PIXEL_FORMAT_4BPP               0x02
 
224
#define PIXEL_FORMAT_8BPP               0x03
 
225
#define PIXEL_FORMAT_16BPP              0x04
 
226
#define PIXEL_FORMAT_24BPP              0x05
 
227
#define PIXEL_FORMAT_32BPP              0x06
 
228
 
 
229
/* RGB525_8BPP_CTRL */
 
230
#define B8_DCOL_INDIRECT                0x0
 
231
#define B8_DCOL_DIRECT                  0x01
 
232
 
 
233
/* RGB525_16BPP_CTRL */
 
234
#define B16_DCOL_INDIRECT               0x0
 
235
#define B16_DCOL_DYNAMIC                0x40
 
236
#define B16_DCOL_DIRECT                 0xC0
 
237
#define B16_POL_FORCE_BYPASS            0x0
 
238
#define B16_POL_FORCE_LOOKUP            0x20
 
239
#define B16_ZIB                         0x0
 
240
#define B16_LINEAR                      0x04
 
241
#define B16_555                         0x0
 
242
#define B16_565                         0x02
 
243
#define B16_SPARSE                      0x0
 
244
#define B16_CONTIGUOUS                  0x01
 
245
 
 
246
/* RGB525_24BPP_CTRL */
 
247
#define B24_DCOL_INDIRECT               0x0
 
248
#define B24_DCOL_DIRECT                 0x01
 
249
 
 
250
/* RGB525_32BPP_CTRL */
 
251
#define B32_POL_FORCE_BYPASS            0x0
 
252
#define B32_POL_FORCE_LOOKUP            0x04
 
253
#define B32_DCOL_INDIRECT               0x0
 
254
#define B32_DCOL_DYNAMIC                0x01
 
255
#define B32_DCOL_DIRECT                 0x03
 
256
 
 
257
/* RGB525_PLL_CTRL_1 */
 
258
#define REF_SRC_REFCLK                  0x0
 
259
#define REF_SRC_EXTCLK                  0x10
 
260
#define PLL_EXT_FS_3_0                  0x0
 
261
#define PLL_EXT_FS_2_0                  0x01
 
262
#define PLL_CNTL2_3_0                   0x02
 
263
#define PLL_CNTL2_2_0                   0x03
 
264
 
 
265
/* RGB525_PLL_CTRL_2 */
 
266
#define PLL_INT_FS_3_0(n)               (n)
 
267
#define PLL_INT_FS_2_0(n)               (n)
 
268
 
 
269
/* RGB525_PLL_REF_DIV_COUNT */
 
270
#define REF_DIV_COUNT(n)                (n)
 
271
 
 
272
/* RGB525_F0 - RGB525_F15 */
 
273
#define VCO_DIV_COUNT(n)                (n)
 
274
 
 
275
/* RGB525_PLL_REFCLK values */
 
276
#define RGB525_PLL_REFCLK_MHz(n)        ((n)/2)
 
277
 
 
278
/* RGB525_CURSOR_CONTROL */
 
279
#define SMLC_PART_0                     0x0
 
280
#define SMLC_PART_1                     0x40
 
281
#define SMLC_PART_2                     0x80
 
282
#define SMLC_PART_3                     0xC0
 
283
#define PIX_ORDER_RL                    0x0
 
284
#define PIX_ORDER_LR                    0x20
 
285
#define LOC_READ_LAST                   0x0
 
286
#define LOC_READ_ACTUAL                 0x10
 
287
#define UPDT_CNTL_DELAYED               0x0
 
288
#define UPDT_CNTL_IMMEDIATE             0x08
 
289
#define CURSOR_SIZE_32                  0x0
 
290
#define CURSOR_SIZE_64                  0x40
 
291
#define CURSOR_MODE_OFF                 0x0
 
292
#define CURSOR_MODE_3_COLOR             0x01
 
293
#define CURSOR_MODE_2_COLOR_HL          0x02
 
294
#define CURSOR_MODE_2_COLOR             0x03
 
295
 
 
296
/* RGB525_REVISION_LEVEL */
 
297
#define REVISION_LEVEL                  0xF0    /* predefined */
 
298
 
 
299
/* RGB525_ID */
 
300
#define ID_CODE                         0x01    /* predefined */
 
301
 
 
302
/* MISR status */
 
303
#define RGB525_MISR_DONE                0x01
 
304
 
 
305
/* the IBMRGB640 is rather different from the rest of the RAMDACs,
 
306
   so we define a completely new set of register names for it */
 
307
#define RGB640_SER_07_00                0x02
 
308
#define RGB640_SER_15_08                0x03
 
309
#define RGB640_SER_23_16                0x04
 
310
#define RGB640_SER_31_24                0x05
 
311
#define RGB640_SER_WID_03_00            0x06
 
312
#define RGB640_SER_WID_07_04            0x07
 
313
#define RGB640_SER_MODE                 0x08
 
314
#define         IBM640_SER_2_1  0x00
 
315
#define         IBM640_SER_4_1  0x01
 
316
#define         IBM640_SER_8_1  0x02
 
317
#define         IBM640_SER_16_1 0x03
 
318
#define         IBM640_SER_16_3 0x05
 
319
#define         IBM640_SER_5_1  0x06
 
320
#define RGB640_PIXEL_INTERLEAVE         0x09
 
321
#define RGB640_MISC_CONF                0x0a
 
322
#define         IBM640_PCLK             0x00
 
323
#define         IBM640_PCLK_2           0x40
 
324
#define         IBM640_PCLK_4           0x80
 
325
#define         IBM640_PCLK_8           0xc0
 
326
#define         IBM640_PSIZE10          0x10
 
327
#define         IBM640_LCI              0x08
 
328
#define         IBM640_WIDCTL_MASK      0x07
 
329
#define RGB640_VGA_CONTROL              0x0b
 
330
#define         IBM640_RDBK     0x04
 
331
#define         IBM640_PSIZE8   0x02
 
332
#define         IBM640_VRAM     0x01
 
333
#define RGB640_DAC_CONTROL              0x0d
 
334
#define         IBM640_MONO     0x08
 
335
#define         IBM640_DACENBL  0x04
 
336
#define         IBM640_SHUNT    0x02
 
337
#define         IBM640_SLOWSLEW 0x01
 
338
#define RGB640_OUTPUT_CONTROL           0x0e
 
339
#define         IBM640_RDAI     0x04
 
340
#define         IBM640_WDAI     0x02
 
341
#define         IBM640_WATCTL   0x01
 
342
#define RGB640_SYNC_CONTROL             0x0f
 
343
#define         IBM640_PWR      0x20
 
344
#define         IBM640_VSP      0x10
 
345
#define         IBM640_HSP      0x08
 
346
#define         IBM640_CSE      0x04
 
347
#define         IBM640_CSG      0x02
 
348
#define         IBM640_BPE      0x01
 
349
#define RGB640_PLL_N                    0x10
 
350
#define RGB640_PLL_M                    0x11
 
351
#define RGB640_PLL_P                    0x12
 
352
#define RGB640_PLL_CTL                  0x13
 
353
#define         IBM640_PLL_EN   0x04
 
354
#define         IBM640_PLL_HIGH 0x10
 
355
#define         IBM640_PLL_LOW  0x01
 
356
#define RGB640_AUX_PLL_CTL              0x17
 
357
#define         IBM640_AUXPLL   0x04
 
358
#define         IBM640_AUX_HI   0x02
 
359
#define         IBM640_AUX_LO   0x01
 
360
#define RGB640_CHROMA_KEY0              0x20
 
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#define RGB640_CHROMA_MASK0             0x21
 
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#define RGB640_CURS_X_LOW               0x40
 
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#define RGB640_CURS_X_HIGH              0x41
 
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#define RGB640_CURS_Y_LOW               0x42
 
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#define RGB640_CURS_Y_HIGH              0x43
 
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#define RGB640_CURS_OFFSETX             0x44
 
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#define RGB640_CURS_OFFSETY             0x45
 
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#define RGB640_CURSOR_CONTROL           0x4B
 
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#define         IBM640_CURS_OFF         0x00
 
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#define         IBM640_CURS_MODE0       0x01
 
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#define         IBM640_CURS_MODE1       0x02
 
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#define         IBM640_CURS_MODE2       0x03
 
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#define         IBM640_CURS_ADV         0x04
 
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#define RGB640_CROSSHAIR_CONTROL        0x57
 
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#define RGB640_VRAM_MASK0               0xf0
 
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#define RGB640_VRAM_MASK1               0xf1
 
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#define RGB640_VRAM_MASK2               0xf2
 
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#define RGB640_DIAGS                    0xfa
 
379
#define RGB640_CURS_WRITE               0x1000
 
380
#define RGB640_CURS_COL0                0x4800
 
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#define RGB640_CURS_COL1                0x4801
 
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#define RGB640_CURS_COL2                0x4802
 
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#define RGB640_CURS_COL3                0x4803