1
Notes on the AGX Server
9
This server currently supports the IIT AGX-016, AGX-015, AGX-014 and XGA-2
10
chipsets. The AGX chipset is based on XGA architecture, but is missing sev-
11
eral features and differs on others. There's also untested support for the
12
XGA-1 and AGX-010 chipsets. Pixel depths of 8bpp, 15bpp, 16bpp are generally
13
supported. Unpacked 24bpp (RGBX 32bpp) is not yet stable enough to release.
15
RAMDACs currently supported are the Brooktree (BT481, BT482, and BT485) and
16
AT&T (20C505) RAMDACs used by the Hercules Graphite series, and Sierra RAM-
17
DACs (15025 and 15021), and Generic VGA RAMDAC. Untested support has been
18
added for the AT&T 20C490 series.
20
The current driver has a number of acceleration routines: solid and dashed
21
zero-width lines (except AGX-014), bitblt fills, tiles, and stipples, solid
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arc and polygon fills, character glyphs and font cache for 8-bit characters.
24
Boards that have had some testing include ISA and VLB versions of most of the
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Hercules Graphite series, Spider Black Widow VLB and Black Widow Plus VLB,
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Boca Vortek VL, CatsEye/X XGA-2, and the PS/2-57 planar XGA-2. The Orchid
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Celsius is very similar to the Spider and Boca boards, except some batches
28
may use one of the AT&T 20C490 series RAMDACs, instead of the Sierra 15025.
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There has also been a report of a generic board that uses a UMC RAMDAC that
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may be an AT&T 20C490 Clone.
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First, to Hercules Customer Support for providing a loaner board to get
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Second, to the XFree86 team, and those who who have contributed to their
38
efforts to the project, for the foundation of work that provided a basis for
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bootstrapping this server.
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o The accelerated line routines don't match lines written by the mi/cfb
44
routines. This is noticeable when switching between virtual consoles
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while running routines that draw and erase lines. Seems to have been
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reduced/fixed in previous releases but need more testing.
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o Some special-case speedup added to cached font rendering in 3.1.1 has
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been disabled as is over-aggressive in some cases. This cuts the perfor-
50
mance on terminal-fonts in half, and font performance is already low for
51
the AGX chips compared to their contemporaries.
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o As in all software, needs more testing.
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o Address the above known problems.
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o Additional acceleration routines and general performance improvements.
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Many existing acceleration routines are Q&D adaptations of existing rou-
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tines from other servers that support graphics chips that differ signif-
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icantly, architecturally, from that XGA and are undoubtedly less than
63
optimal. In particular some of the general per-operation overhead to
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set-up the graphics context should be moved to the ValidateGC() rou-
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o Complete HW cursor support, most of the code is done (or borrowed from
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other servers). There just remains a little setup code and then finding
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a lot of time to debug and test the numerous permutations.
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o Complete support for the Graphite Pro's 84-pin RAMDAC. (the 2MB version
72
of the Graphite Pro has both RAMDACs, the 1Mb only the 44-pin RAMDAC).
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Currently, the 84-pin RAMDAC is only supported in clock-doubled pixmux
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mode, the server will switch between RAMDACs as required by the video
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mode In >8bpp modes this switching does not occur.
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o Implement more HW probing, this will be difficult as it appears some
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(all?) AGX-based vendors don't implement the VESA VXE POS registers,
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although the AGX chip does support it (and some vendors claim VXE com-
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pliance...). There are a few rev/vendor registers in the AGX chip but
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they are not documented. Note: SuperProbe also does not support probing
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for AGX/XGA chips. ISA POS probing is supported for the XGA chips and
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some code for EISA POS is also included but not tested.
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o Micro-optimizations, in particularly reducing processing overhead for
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common special cases that don't require full generality.
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Device Section Entries and Options Currently Supported:
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The minimum that must be specified in the XF86Config device section for the
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AGX-014, AGX-015, AGX-016, and ISA-based XGA-1 and XGA-2 is the Chipset. How-
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ever to get full capability out of the AGX-01[456] chips, the RAMDAC should
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be specified. Other parms may select additional capabilities, or may used to
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override the defaults or reduce start-up time be suppressing probing. XGA
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specific configuration is covered at the end of this document. The XGA
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entries can generally be used to override defaults for the AGX-01[456] as
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Be sure to check the clock rating of the RAMDAC(s) on your video
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board and don't exceed that rating even if the server allows it,
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overclocking RAMDACs will damage them.
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The clock rating generally appears as a suffix to the part num-
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ber, may only have the most significant digit(s), and may be
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mixed with other codes (e.g. package type). For example, an 85MHz
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Bt481 in a plastic J-lead package has a part number of Bt481KPJ85
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and a 135MHz AT&T20C505 has a part number of ATT20C505-13. Sierra
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stamps the rated speed below the part numbers in a dark ink.
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normal VGA style RAMDAC (6-bit DAC), default if none
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specified. Most boards should work with this parm,
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but some capabilities will be unavailable. Only 8bpp
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bt481 RAMDAC (supports 8-bit DAC)
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bt482 RAMDAC (supports 8-bit DAC) The Hercules
124
Graphite HG210 uses the BT481 or BT482, the only dif-
125
ference between these two is the BT482's HW cursor
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(not yet supported). The BT481/2 are limited to
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85Mhz. 8bpp, 15bpp, 16bpp are supported.
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AT&T490 RAMDAC (includes 49[123] - supports 8-bit
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DAC). Limited to 110Mhz at 8bpp. 8bpp, 15bpp, and
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Sierra SC15025 and SC15021 RAMDAC (support 8-bit
136
DAC). The SC15025 is limited to 125Mhz, and the
137
SC15021 135Mhz. Check the RAMDAC's actual rating,
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some SC15025's used in AGX based boards are only
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rated to 110Mhz. 8bpp, 15bpp, and 16bpp are sup-
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Hercules Graphite Pro RAMDAC probe. If the 84-pin
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Big-RAMDAC is installed (2MB models), will use the
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Big RAMDAC, but only clocks-doubled, pixel- multi-
146
plexed modes (higher clock values only!). Lower
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clocks and resolutions in 8bpp mode are supported by
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switching to the Small 44-pin RAMDAC. 15bpp and 16bpp
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There has been one report of the "dac-8-bit" option
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not working with a Graphite Pro equipped with a BT485
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RAMDAC, puzzling since it should be identical to the
154
AT&T20C505 in this regard. No startup messages or
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XF86Config were submitted to aid problem isolation.
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Not supported by the HG210 Graphite.
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Hercules Graphite Pro RAMDAC probe. Forces use of
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only the BT481/482 RAMDAC. 8bpp, 15bpp, 16bpp, and
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unpacked 24/32bpp are supported.
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Not supported by the HG210 Graphite.
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To allow overriding the default VGA style RAMDAC con-
168
trol for the AGX-010.
170
Ramdac related Option Flags:
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Sets RAMDAC to VGA default 6-bit DAC mode (default
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Sets supported RAMDAC's to 8-bit DAC mode (default
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for all but "normal").
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Composite sync on green for RAMDAC's that support
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this feature (BT481/481 and AT&T20c490). However,
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whether any boards have necessary traces and glue
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Must be specified, possible values: "AGX-016", "AGX-015",
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"AGX-014", "AGX-010", "XGA-2", or "XGA-1". Some AGX vendors place
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stickers over the chip, in general, if it's a VLB board it's
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probably an AGX-015 and if it's an ISA board it may be an
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AGX-014. The Hercules Graphite Power Pro and Spider Black Widow
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Plus use the AGX-016 chipset. In general, specifying a lower
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revision in the AGX-0{14,15,16} series does not seem to causes
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problems (except lower performance from the AGX-014's non-accel-
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erated line drawing).
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Note: Only the AGX-016, AGX-015, AGX-014 and XGA-2 have had any
198
testing. Most of the development has been with an AGX-015 based
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2MB Hercules Graphite VL PRO (HG720) and most of testers for pre-
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vious releases had AGX-014 based 1MB Hercules Graphite (HG210).
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The limited documentation I have for the AGX-010 is that is is a
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clone of the XGA architecture with a few additional configuration
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registers. What is not clear is whether to use XGA or extended-
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VGA RAMDAC control registers. The post-3.1.1 default is now VGA
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control registers, but XGA control registers can be forced with
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the XGA RAMDAC parm. Likewise the configuration parms described
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in the XGA section can be used to override the AGX defaults for
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I/O and memory addresses.
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Will be probed if not specified. The startup will be a little
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"wait_state", "no_wait_state"
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Set or clear CPU access wait state,
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default is the POST setting.
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Disable Memory I/O Buffer, AGX-015 and
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AGX-016. MS-Windows driver default.
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Required by some VLB systems with
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`aggressive timing'. The default for
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this server is to disable the buffer.
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Enable the AGX-015/016's Memory I/O
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Enable the AGX-016's extra-large buffer.
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Either option may result in garbage being
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left about the screen, disabled by
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default. A good test is the xbench or
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x11perf dashed lines tests, if random
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dots are drawn, fifo_conserv is required.
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So far, no boards have been reported that
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worked correctly with the buffers
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POST defaults should be ok.
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"vram_delay_latch", "vram delay_ras", "vram_extend_ras"
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"slow_vram", "slow_dram"
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Set all of the vram timing options.
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Set vram latch delay, clear others.
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"fast_dram"" All of the vram timing
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options are cleared. Should be specified
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if directly specifying VRAM options in
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order to clear POST settings.
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These shouldn't generally be required:
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(AGX,XGA) Disable Font Cache.
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(AGX) Force XGA mode CRTC delay.
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AGX-015 only? adds additional VLB wait
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"vram_128", "vram_256"
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Sets VRAM shift frequency, vram_128 is
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for 128Kx8 VRAM. Default is to leave this
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bit unchanged from POST setting.
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"refresh_20", "refresh_25"
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Number of clock cycles between screen
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refreshes. Default is to leave this bit
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unchanged from POST setting.
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Disable screen refresh during non-blanked
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intervals, AGX-016. Default is leave them
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VLB transaction type, default is to leave
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this bit unchanged from POST value.
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The server now accepts any virtual width, however the actual
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usable CRTC line width is restricted when using the graphics
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engine and depends upon the chip revision. The CRTC line width
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and not the virtual width determine the amount of memory used.
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The server currently does not make use of any of the unused CRTC
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line's memory. CRTC line width is restricted by the following
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AGX-014 : 512, 1024 and 2048. (also AGX-010)
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AGX-015 : 512, 1024, 1280, and 2048.
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AGX-016 : 512, 640, 800, 1024, 1280, and 2048.
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XGA,AGX-010 : 512, 640, 800, 1024, 1280, 1152, and
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When panning I occasionally get streaks if the virtual resolution
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is much greater than the physical resolution. Moving the mouse a
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little makes it disappear. The Hercules manual indicates this
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also happens with the MS-Windows drivers.
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The server requires at least a 64KB scratchpad (16KB for XGA's).
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Additional memory is useful for font cache and a larger scratch-
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Probing is supported, but of course the usual warnings and dis-
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claimers apply. Probing may momentarily subject your monitor to
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sweep frequencies in excess of its rating. The cautious may wish
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to turn off the monitor while the probe is running.
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Once clocks are known, they can be entered into XF86Config, then
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subsequent runs won't probe clocks and will be quicker to
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startup. For the clock probe it is recommended that the X server
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be run with the -probeonly option. The values in the clocks
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statement are the hardware input clocks and correspond to the
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pixel clock only at 8bpp in direct-clocking RAMDAC modes. The
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server will divide/multiply those values as appropriate for the
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RAMDAC modes available at the current pixel depth. The available
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pixel clocks will be displayed in the startup messages.
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For the 2MB Hercules Graphites, with the "herc-dual-dac" RAMDAC
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specified, earlier versions of the server generated an additional
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16 clocks with values doubled and some zeroed. Those are no
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longer needed and you should re-probe and re-enter the clock val-
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ues to ensure all clocks are available to you.
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The AGX-015 2MB Hercules Graphite VL Pro with an ICS1494M
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9251-516 clock chip has probed clock values of:
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25.18 28.80 32.70 36.00 40.00 45.00 50.40 64.70
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70.10 76.10 80.60 86.30 90.40 95.90 100.70 109.40
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Actual values according to Hercules are:
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25.175 28.322 32.512 36.000 40.00 44.90 50.35 65.00
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70.00 75.00 80.00 85.00 90.00 95.00 100.0 108.0
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These are the values to be used in the clock statement if speci-
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fying the "normal", "bt481", or "herc_small_dac" RAMDAC in your
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XF86Config and your clockchip matches that above.
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Clock probing assumes that the first clock is 25.175Mhz and uses
363
that to derive the rest. A warning is displayed if the second is
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not near 28.322Mhz. If this warning appears, you should not use
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the probed clock values without additional verification from
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In the case of the AGX-014 and later AGX's, only the external
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clock select lines are used, this means the clock values corre-
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spond to the values of the video board's clock chip.
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For the AGX-010, the first 8 clocks use the standard XGA internal
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clock selects and the second 8 are based on AGX extensions. For
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the XGA-1 only 8 clocks are available. The XGA-2 uses a pro-
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grammable clock and no clocks or clockchip line is required.
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The maximum pixel clock generally allowed is 85MHz, but some RAM-
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DACs support higher values. In any case you, should check your
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RAMDAC, some RAMDACs used on AGX based boards are produced in
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versions rated to lesser values than the server assumes. You
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should check the rating and limit yourself to that value.
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One difference I've noted from the Mach8, is that the AGX's CRTC
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doesn't like the start of the horizontal sync to be equal to
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horiz blank start (vert sync may have the same problem, I need to
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test some more). Interlaced and +/-sync flags are supported but
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have had very little testing. For interlaced modes make sure the
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number of lines is an odd number.
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The doublescan flag is now supported, however the minimum clock
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supported is generally 25MHz, so resolutions of less than 400x300
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are not likely to be supported by most monitors. In creating
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doublescan mode timings, the vertical timings will match the
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apparent resolutions, e.g. for 400x300 the timings should
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describe 300 lines, not 600.
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For the Hercules HG720 (2MB VLB AGX-015, with BT481 and
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AT&T20C5050 RAMDACs), I use the following XF86Config "Device"
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VendorName "Hercules"
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BoardName "Graphite VL Pro"
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Clocks 25.2 28.3 32.5 36.0 40.0 45.0 50.4 65.0
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70.00 75.00 80.00 85.00 90.00 95.00 100.0 108.0
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RamDac "herc_dual_dac"
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Option "no_wait_state"
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For the Spider Black Widow Plus (2MB VLB AGX-016, with Sierra
423
BoardName "Black Widow Plus"
425
Clocks 25.2 28.3 39.9 72.2 50.0 76.9 36.1 44.8
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89.0 119.8 79.9 31.5 110.0 64.9 74.9 94.9
430
Option "no_wait_state"
435
This server now has tested support for XGA-2 compatible boards
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(aka. XGA-NI). The main issue for XGA-1 support is whether clock probing
437
works. At this time probing for board configuration is limited and detailed
438
configuration may need to be done manually.
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By default the ISA POS register will be performed. If the XGA Instance
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number is specified the scope of probing will be narrowed a bit. To override
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or disable probing, a minimum of the Instance, COPbase, and MEMbase must be
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specified in the XF86Config device section for the XGA card. MCA probing is
447
XGA instance number (0-7).
450
The I/O address of the the XGA general control registers. The
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standard, and default, is 0x21i0, where i is the instance number.
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The XGA display memory address (the address the XGA coprocessor
455
uses for video memory). This is also the system memory address of
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the linear aperture on boards that support it.
458
POS register 4 bits 7-1 contains bits 31-25 of the XGA's display
459
memory address. Bits 24-22 of of the display memory address con-
460
tains the XGA instance number. Bit 0 of POS register 4 is not
461
used by this server as the XGA's linear aperture is not used.
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However, the coprocessor must still be configured with this.
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The AGX-01[456] chips have a fixed display memory address.
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Address of the graphics engine's memory mapped control registers.
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0xC1C00 + (ext_mem_addr * 0x2000) + (instance * 0x80)
473
where ext_mem_addr is the high order 4-bits of POS register 2
474
(0-16 the server assumes zero).
476
The AGX-01[456] chips support 0xB1F00 (default) and 0xD1F00.
479
Address of the XGA BIOS (not VGA BIOS). Can be specified as an
480
alternate to COPbase.
484
0xC0000 + (ext_mem_addr * 0x2000)
486
where ext_mem_addr is the high order 4-bits of POS register 2
487
(0-16 -- the server assumes zero).
490
Can be used to override the default 0xA0000 address for the 64KB
491
video memory address used by the server. The only values accept-
492
able are 0xA0000 and 0xB0000. VGA text mode restore does not work
493
under Linux if 0xB0000 is specified.
495
AGX-01[456] also default to 0xA0000.
498
Can be used to specify an alternate POS register probe address
499
base from the ISA default of 0x100. The VESA VXE standard for
500
EISA is 0xzC80, where z is the slot number).
502
A value of zero will disable POS register probing (required for
506
Can be used to override the servers default maximum Pixel Clock
507
for XGA-2 of 80Mhz. The limit can be raised as high as 90Mhz, or
510
An alternate way to determine the POS register values is with the
511
setup/diag programs that should have been included with your video board, or
512
possibly from jumper values.
514
The XGA-2 has programmable clocks up to 90MHz, however at 1024x768, 72MHz is
515
generally the max that will produce a stable display with the CatsEye/XGA-2
516
used for testing (IBM coprocessor and INMOS RAMDAC/serializer). Higher clocks
517
will often generate artifacts at the top and left edges of the screen. Such
518
artifacts can sometimes be tuned out by increasing the vertical and horizon-
519
tal blanking intervals or slightly changing the clock. At pixel clock rates
520
above 80Mhz I have seen the chip lose sync after running for several minutes,
521
so 80Mhz has been set as the default limit for XGA-2 pixel clocks. I don't
522
have specs on actual limits, and as there are a number of different XGA
523
chipsets, you should use the modes documented in your owner's manual as a
524
guide to max refresh rates. No clocks or clockchip parm are required to spec-
525
ify use of programmable clocks for the XGA-2.
527
8bpp and 16bpp are supported for the XGA-2.
529
For XGA-1 cards the clocks must be specified as for the AGX chips, it is not
530
known whether the clockprobing will work. Some XGA-1 chips may support 16bpp.
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Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/agx.sgml,v 3.19 1997/01/25 03:22:19 dawes Exp $
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$XConsortium: agx.sgml /main/9 1996/10/19 18:03:50 kaleb $
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$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.agx,v 3.41 2000/03/01 01:48:18 dawes Exp $