2
* cacheattr.c: MTRR and PAT initialisation.
4
* Copyright (c) 2008, Citrix Systems, Inc.
7
* Keir Fraser <keir.fraser@citrix.com>
9
* This program is free software; you can redistribute it and/or modify it
10
* under the terms and conditions of the GNU General Public License,
11
* version 2, as published by the Free Software Foundation.
13
* This program is distributed in the hope it will be useful, but WITHOUT
14
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18
* You should have received a copy of the GNU General Public License along with
19
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
20
* Place - Suite 330, Boston, MA 02111-1307 USA.
26
#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
27
#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
28
#define MSR_MTRRcap 0x00fe
29
#define MSR_MTRRfix64K_00000 0x0250
30
#define MSR_MTRRfix16K_80000 0x0258
31
#define MSR_MTRRfix16K_A0000 0x0259
32
#define MSR_MTRRfix4K_C0000 0x0268
33
#define MSR_MTRRfix4K_C8000 0x0269
34
#define MSR_MTRRfix4K_D0000 0x026a
35
#define MSR_MTRRfix4K_D8000 0x026b
36
#define MSR_MTRRfix4K_E0000 0x026c
37
#define MSR_MTRRfix4K_E8000 0x026d
38
#define MSR_MTRRfix4K_F0000 0x026e
39
#define MSR_MTRRfix4K_F8000 0x026f
40
#define MSR_PAT 0x0277
41
#define MSR_MTRRdefType 0x02ff
43
void cacheattr_init(void)
45
uint32_t eax, ebx, ecx, edx;
46
uint64_t mtrr_cap, mtrr_def, content, addr_mask;
47
unsigned int i, nr_var_ranges, phys_bits = 36;
49
/* Does the CPU support architectural MTRRs? */
50
cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
51
if ( !(edx & (1u << 12)) )
54
/* Find the physical address size for this CPU. */
55
cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
56
if ( eax >= 0x80000008 )
58
cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
59
phys_bits = (uint8_t)eax;
62
printf("%u-bit phys ... ", phys_bits);
64
addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1);
65
mtrr_cap = rdmsr(MSR_MTRRcap);
66
mtrr_def = (1u << 11) | 6; /* E, default type WB */
68
/* Fixed-range MTRRs supported? */
69
if ( mtrr_cap & (1u << 8) )
71
/* 0x00000-0x9ffff: Write Back (WB) */
72
content = 0x0606060606060606ull;
73
wrmsr(MSR_MTRRfix64K_00000, content);
74
wrmsr(MSR_MTRRfix16K_80000, content);
75
/* 0xa0000-0xbffff: Write Combining (WC) */
76
if ( mtrr_cap & (1u << 10) ) /* WC supported? */
77
content = 0x0101010101010101ull;
78
wrmsr(MSR_MTRRfix16K_A0000, content);
79
/* 0xc0000-0xfffff: Write Back (WB) */
80
content = 0x0606060606060606ull;
81
for ( i = 0; i < 8; i++ )
82
wrmsr(MSR_MTRRfix4K_C0000 + i, content);
83
mtrr_def |= 1u << 10; /* FE */
84
printf("fixed MTRRs ... ");
87
/* Variable-range MTRRs supported? */
88
nr_var_ranges = (uint8_t)mtrr_cap;
89
if ( nr_var_ranges != 0 )
91
unsigned long base = pci_mem_start, size;
94
for ( i = 0; (base != pci_mem_end) && (i < nr_var_ranges); i++ )
97
while ( !(base & size) )
99
while ( ((base + size) < base) || ((base + size) > pci_mem_end) )
102
wrmsr(MSR_MTRRphysBase(i), base);
103
wrmsr(MSR_MTRRphysMask(i),
104
(~(uint64_t)(size-1) & addr_mask) | (1u << 11));
109
printf("var MTRRs [%d/%d] ... ", i, nr_var_ranges);
112
wrmsr(MSR_MTRRdefType, mtrr_def);