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#include <xen/percpu.h>
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#define rdmsr(msr,val1,val2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (val1), "=d" (val2) \
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#define rdmsrl(msr,val) do { unsigned long a__,b__; \
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__asm__ __volatile__("rdmsr" \
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: "=a" (a__), "=d" (b__) \
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val = a__ | ((u64)b__<<32); \
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: "c" (msr), "a" (val1), "d" (val2))
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static inline void wrmsrl(unsigned int msr, __u64 val)
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hi = (__u32)(val >> 32);
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr,val1,val2) ({\
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__asm__ __volatile__( \
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".section .fixup,\"ax\"\n" \
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"3: movl %5,%2\n; jmp 2b\n" \
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".section __ex_table,\"a\"\n" \
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" "__FIXUP_ALIGN"\n" \
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" "__FIXUP_WORD" 1b,3b\n" \
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: "=a" (val1), "=d" (val2), "=&r" (_rc) \
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: "c" (msr), "2" (0), "i" (-EFAULT)); \
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/* wrmsr with exception handling */
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#define wrmsr_safe(msr,val1,val2) ({\
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__asm__ __volatile__( \
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".section .fixup,\"ax\"\n" \
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"3: movl %5,%0\n; jmp 2b\n" \
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".section __ex_table,\"a\"\n" \
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" "__FIXUP_ALIGN"\n" \
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" "__FIXUP_WORD" 1b,3b\n" \
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: "c" (msr), "a" (val1), "d" (val2), "0" (0), "i" (-EFAULT)); \
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#define rdtsc(low,high) \
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
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__asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
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#define rdtscll(val) \
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__asm__ __volatile__("rdtsc" : "=A" (val))
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#elif defined(__x86_64__)
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#define rdtscll(val) do { \
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asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
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(val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
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#define write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
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#define rdpmc(counter,low,high) \
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__asm__ __volatile__("rdpmc" \
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: "=a" (low), "=d" (high) \
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DECLARE_PER_CPU(u64, efer);
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static inline u64 read_efer(void)
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return this_cpu(efer);
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static inline void write_efer(u64 val)
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this_cpu(efer) = val;
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wrmsrl(MSR_EFER, val);
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DECLARE_PER_CPU(u32, ler_msr);
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static inline void ler_enable(void)
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if ( !this_cpu(ler_msr) )
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl | 1);
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_MSR_H */