2
* Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3
* of PCI-SCSI IO processors.
5
* Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7
* This driver is derived from the Linux sym53c8xx driver.
8
* Copyright (C) 1998-2000 Gerard Roudier
10
* The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11
* a port of the FreeBSD ncr driver to Linux-1.2.13.
13
* The original ncr driver has been written for 386bsd and FreeBSD by
14
* Wolfgang Stanglmeier <wolf@cologne.de>
15
* Stefan Esser <se@mi.Uni-Koeln.de>
16
* Copyright (C) 1994 Wolfgang Stanglmeier
18
* Other major contributions:
20
* NVRAM detection and reading.
21
* Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23
*-----------------------------------------------------------------------------
25
* Redistribution and use in source and binary forms, with or without
26
* modification, are permitted provided that the following conditions
28
* 1. Redistributions of source code must retain the above copyright
29
* notice, this list of conditions and the following disclaimer.
30
* 2. The name of the author may not be used to endorse or promote products
31
* derived from this software without specific prior written permission.
33
* Where this Software is combined with software released under the terms of
34
* the GNU Public License ("GPL") and the terms of the GPL would require the
35
* combined work to also be released under the terms of the GPL, the terms
36
* and conditions of this License will apply in addition to those of the
37
* GPL with the exception of any terms or conditions of this License that
38
* conflict with, or are expressly prohibited by, the GPL.
40
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
41
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
44
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59
#define PCI_VENDOR_NCR 0x1000
62
* PCI device identifier of SYMBIOS chips.
64
#define PCI_ID_SYM53C810 1
65
#define PCI_ID_SYM53C810AP 5
66
#define PCI_ID_SYM53C815 4
67
#define PCI_ID_SYM53C820 2
68
#define PCI_ID_SYM53C825 3
69
#define PCI_ID_SYM53C860 6
70
#define PCI_ID_SYM53C875 0xf
71
#define PCI_ID_SYM53C875_2 0x8f
72
#define PCI_ID_SYM53C885 0xd
73
#define PCI_ID_SYM53C895 0xc
74
#define PCI_ID_SYM53C896 0xb
75
#define PCI_ID_SYM53C895A 0x12
76
#define PCI_ID_SYM53C875A 0x13
77
#define PCI_ID_LSI53C1010 0x20
78
#define PCI_ID_LSI53C1010_2 0x21
79
#define PCI_ID_LSI53C1510D 0xa
82
* SYM53C8XX device features descriptor.
88
u_char burst_max; /* log-base-2 of max burst */
93
#define FE_LED0 (1<<0)
94
#define FE_WIDE (1<<1) /* Wide data transfers */
95
#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
96
#define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
97
#define FE_DBLR (1<<4) /* Clock doubler present */
98
#define FE_QUAD (1<<5) /* Clock quadrupler present */
99
#define FE_ERL (1<<6) /* Enable read line */
100
#define FE_CLSE (1<<7) /* Cache line size enable */
101
#define FE_WRIE (1<<8) /* Write & Invalidate enable */
102
#define FE_ERMP (1<<9) /* Enable read multiple */
103
#define FE_BOF (1<<10) /* Burst opcode fetch */
104
#define FE_DFS (1<<11) /* DMA fifo size */
105
#define FE_PFEN (1<<12) /* Prefetch enable */
106
#define FE_LDSTR (1<<13) /* Load/Store supported */
107
#define FE_RAM (1<<14) /* On chip RAM present */
108
#define FE_VARCLK (1<<15) /* Clock frequency may vary */
109
#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
110
#define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */
111
#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
112
#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
113
#define FE_LEDC (1<<20) /* Hardware control of LED */
114
#define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */
115
#define FE_66MHZ (1<<22) /* 66MHz PCI support */
116
#define FE_CRC (1<<23) /* CRC support */
117
#define FE_DIFF (1<<24) /* SCSI HVD support */
118
#define FE_DFBC (1<<25) /* Have DFBC register */
119
#define FE_LCKFRQ (1<<26) /* Have LCKFRQ */
120
#define FE_C10 (1<<27) /* Various C10 core (mis)features */
121
#define FE_U3EN (1<<28) /* U3EN bit usable */
122
#define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */
123
#define FE_ISTAT1 (1<<30) /* Have ISTAT1, MBOX0, MBOX1 registers */
125
#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
126
#define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
130
* Symbios NVRAM data format
132
#define SYMBIOS_NVRAM_SIZE 368
133
#define SYMBIOS_NVRAM_ADDRESS 0x100
135
struct Symbios_nvram {
137
u_short type; /* 0x0000 */
138
u_short byte_count; /* excluding header/trailer */
141
/* Controller set up 20 bytes */
142
u_char v_major; /* 0x00 */
143
u_char v_minor; /* 0x30 */
146
#define SYMBIOS_SCAM_ENABLE (1)
147
#define SYMBIOS_PARITY_ENABLE (1<<1)
148
#define SYMBIOS_VERBOSE_MSGS (1<<2)
149
#define SYMBIOS_CHS_MAPPING (1<<3)
150
#define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
152
#define SYMBIOS_SCAN_HI_LO (1)
154
#define SYMBIOS_TERM_CANT_PROGRAM (0)
155
#define SYMBIOS_TERM_ENABLED (1)
156
#define SYMBIOS_TERM_DISABLED (2)
158
#define SYMBIOS_RMVBL_NO_SUPPORT (0)
159
#define SYMBIOS_RMVBL_BOOT_DEVICE (1)
160
#define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
162
u_char num_hba; /* 0x04 */
163
u_char num_devices; /* 0x10 */
164
u_char max_scam_devices; /* 0x04 */
165
u_char num_valid_scam_devices; /* 0x00 */
167
#define SYMBIOS_AVOID_BUS_RESET (1<<2)
169
/* Boot order 14 bytes * 4 */
171
u_short type; /* 4:8xx / 0:nok */
172
u_short device_id; /* PCI device id */
173
u_short vendor_id; /* PCI vendor id */
174
u_char bus_nr; /* PCI bus number */
175
u_char device_fn; /* PCI device/function number << 3*/
178
#define SYMBIOS_INIT_SCAN_AT_BOOT (1)
179
u_short io_port; /* PCI io_port address */
182
/* Targets 8 bytes * 16 */
183
struct Symbios_target {
185
#define SYMBIOS_DISCONNECT_ENABLE (1)
186
#define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
187
#define SYMBIOS_SCAN_LUNS (1<<2)
188
#define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
190
u_char bus_width; /* 0x08/0x10 */
192
u_short sync_period; /* 4*period factor */
195
/* Scam table 8 bytes * 4 */
196
struct Symbios_scam {
199
#define SYMBIOS_SCAM_DEFAULT_METHOD (0)
200
#define SYMBIOS_SCAM_DONT_ASSIGN (1)
201
#define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
202
#define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
204
#define SYMBIOS_SCAM_UNKNOWN (0)
205
#define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
206
#define SYMBIOS_SCAM_ID_NOT_SET (2)
207
#define SYMBIOS_SCAM_ID_VALID (3)
212
u_char spare_devices[15*8];
213
u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
215
typedef struct Symbios_nvram Symbios_nvram;
216
typedef struct Symbios_host Symbios_host;
217
typedef struct Symbios_target Symbios_target;
218
typedef struct Symbios_scam Symbios_scam;
221
* Tekram NvRAM data format.
223
#define TEKRAM_NVRAM_SIZE 64
224
#define TEKRAM_93C46_NVRAM_ADDRESS 0
225
#define TEKRAM_24C16_NVRAM_ADDRESS 0x40
227
struct Tekram_nvram {
228
struct Tekram_target {
230
#define TEKRAM_PARITY_CHECK (1)
231
#define TEKRAM_SYNC_NEGO (1<<1)
232
#define TEKRAM_DISCONNECT_ENABLE (1<<2)
233
#define TEKRAM_START_CMD (1<<3)
234
#define TEKRAM_TAGGED_COMMANDS (1<<4)
235
#define TEKRAM_WIDE_NEGO (1<<5)
241
#define TEKRAM_MORE_THAN_2_DRIVES (1)
242
#define TEKRAM_DRIVES_SUP_1GB (1<<1)
243
#define TEKRAM_RESET_ON_POWER_ON (1<<2)
244
#define TEKRAM_ACTIVE_NEGATION (1<<3)
245
#define TEKRAM_IMMEDIATE_SEEK (1<<4)
246
#define TEKRAM_SCAN_LUNS (1<<5)
247
#define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; */
248
/* 1: boot device; 2:all */
249
u_char boot_delay_index;
250
u_char max_tags_index;
252
#define TEKRAM_F2_F6_ENABLED (1)
255
typedef struct Tekram_nvram Tekram_nvram;
256
typedef struct Tekram_target Tekram_target;
259
* SYM53C8XX IO register data structure.
262
/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
264
/*01*/ u8 nc_scntl1; /* no reset */
265
#define ISCON 0x10 /* connected to scsi */
266
#define CRST 0x08 /* force reset */
267
#define IARB 0x02 /* immediate arbitration */
269
/*02*/ u8 nc_scntl2; /* no disconnect expected */
270
#define SDU 0x80 /* cmd: disconnect will raise error */
271
#define CHM 0x40 /* sta: chained mode */
272
#define WSS 0x08 /* sta: wide scsi send [W]*/
273
#define WSR 0x01 /* sta: wide scsi received [W]*/
275
/*03*/ u8 nc_scntl3; /* cnf system clock dependent */
276
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
277
#define ULTRA 0x80 /* cmd: ULTRA enable */
278
/* bits 0-2, 7 rsvd for C1010 */
280
/*04*/ u8 nc_scid; /* cnf host adapter scsi address */
281
#define RRE 0x40 /* r/w:e enable response to resel. */
282
#define SRE 0x20 /* r/w:e enable response to select */
284
/*05*/ u8 nc_sxfer; /* ### Sync speed and count */
285
/* bits 6-7 rsvd for C1010 */
287
/*06*/ u8 nc_sdid; /* ### Destination-ID */
289
/*07*/ u8 nc_gpreg; /* ??? IO-Pins */
291
/*08*/ u8 nc_sfbr; /* ### First byte received */
294
#define CREQ 0x80 /* r/w: SCSI-REQ */
295
#define CACK 0x40 /* r/w: SCSI-ACK */
296
#define CBSY 0x20 /* r/w: SCSI-BSY */
297
#define CSEL 0x10 /* r/w: SCSI-SEL */
298
#define CATN 0x08 /* r/w: SCSI-ATN */
299
#define CMSG 0x04 /* r/w: SCSI-MSG */
300
#define CC_D 0x02 /* r/w: SCSI-C_D */
301
#define CI_O 0x01 /* r/w: SCSI-I_O */
308
#define DFE 0x80 /* sta: dma fifo empty */
309
#define MDPE 0x40 /* int: master data parity error */
310
#define BF 0x20 /* int: script: bus fault */
311
#define ABRT 0x10 /* int: script: command aborted */
312
#define SSI 0x08 /* int: script: single step */
313
#define SIR 0x04 /* int: script: interrupt instruct. */
314
#define IID 0x01 /* int: script: illegal instruct. */
317
#define ILF 0x80 /* sta: data in SIDL register lsb */
318
#define ORF 0x40 /* sta: data in SODR register lsb */
319
#define OLF 0x20 /* sta: data in SODL register lsb */
320
#define AIP 0x10 /* sta: arbitration in progress */
321
#define LOA 0x08 /* sta: arbitration lost */
322
#define WOA 0x04 /* sta: arbitration won */
323
#define IRST 0x02 /* sta: scsi reset signal */
324
#define SDP 0x01 /* sta: scsi parity signal */
327
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
330
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
331
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
332
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
333
#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
334
#define LDSC 0x02 /* sta: disconnect & reconnect */
336
/*10*/ u8 nc_dsa; /* --> Base page */
341
/*14*/ u8 nc_istat; /* --> Main Command and status */
342
#define CABRT 0x80 /* cmd: abort current operation */
343
#define SRST 0x40 /* mod: reset chip */
344
#define SIGP 0x20 /* r/w: message from host to script */
345
#define SEM 0x10 /* r/w: message between host + script */
346
#define CON 0x08 /* sta: connected to scsi */
347
#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
348
#define SIP 0x02 /* sta: scsi-interrupt */
349
#define DIP 0x01 /* sta: host/script interrupt */
351
/*15*/ u8 nc_istat1; /* 896 only */
352
#define FLSH 0x04 /* sta: chip is flushing */
353
#define SCRUN 0x02 /* sta: scripts are running */
354
#define SIRQD 0x01 /* r/w: disable INT pin */
356
/*16*/ u8 nc_mbox0; /* 896 only */
357
/*17*/ u8 nc_mbox1; /* 896 only */
364
/* bits 0-2,7 rsvd for C1010 */
367
#define FLF 0x08 /* cmd: flush dma fifo */
368
#define CLF 0x04 /* cmd: clear dma fifo */
369
#define FM 0x02 /* mod: fetch pin mode */
370
#define WRIE 0x01 /* mod: write and invalidate enable */
371
/* bits 4-7 rsvd for C1010 */
373
/*1c*/ u32 nc_temp; /* ### Temporary stack */
377
#define BDIS 0x80 /* mod: burst disable */
378
#define MPEE 0x08 /* mod: master parity error enable */
381
#define DFS 0x20 /* mod: dma fifo size */
382
/* bits 0-1, 3-7 rsvd for C1010 */
386
/*24*/ u32 nc_dbc; /* ### Byte count and command */
387
/*28*/ u32 nc_dnad; /* ### Next command register */
388
/*2c*/ u32 nc_dsp; /* --> Script Pointer */
389
/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
391
/*34*/ u8 nc_scratcha; /* Temporary register a */
392
/*35*/ u8 nc_scratcha1;
393
/*36*/ u8 nc_scratcha2;
394
/*37*/ u8 nc_scratcha3;
397
#define BL_2 0x80 /* mod: burst length shift value +2 */
398
#define BL_1 0x40 /* mod: burst length shift value +1 */
399
#define ERL 0x08 /* mod: enable read line */
400
#define ERMP 0x04 /* mod: enable read multiple */
401
#define BOF 0x02 /* mod: burst op code fetch */
406
/*3b*/ u8 nc_dcntl; /* --> Script execution control */
407
#define CLSE 0x80 /* mod: cache line size enable */
408
#define PFF 0x40 /* cmd: pre-fetch flush */
409
#define PFEN 0x20 /* mod: pre-fetch enable */
410
#define SSM 0x10 /* mod: single step mode */
411
#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
412
#define STD 0x04 /* cmd: start dma mode */
413
#define IRQD 0x02 /* mod: irq disable */
414
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
415
/* bits 0-1 rsvd for C1010 */
419
/*40*/ u16 nc_sien; /* -->: interrupt enable */
420
/*42*/ u16 nc_sist; /* <--: interrupt status */
421
#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
422
#define STO 0x0400/* sta: timeout (select) */
423
#define GEN 0x0200/* sta: timeout (general) */
424
#define HTH 0x0100/* sta: timeout (handshake) */
425
#define MA 0x80 /* sta: phase mismatch */
426
#define CMP 0x40 /* sta: arbitration complete */
427
#define SEL 0x20 /* sta: selected by another device */
428
#define RSL 0x10 /* sta: reselected by another device*/
429
#define SGE 0x08 /* sta: gross error (over/underflow)*/
430
#define UDC 0x04 /* sta: unexpected disconnect */
431
#define RST 0x02 /* sta: scsi bus reset detected */
432
#define PAR 0x01 /* sta: scsi parity error */
438
/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
439
/*49*/ u8 nc_stime1; /* cmd: timeout user defined */
440
/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
445
#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
446
#define DBLEN 0x08 /* clock doubler running */
447
#define DBLSEL 0x04 /* clock doubler selected */
451
#define ROF 0x40 /* reset scsi offset (after gross error!) */
452
#define EXT 0x02 /* extended filtering */
455
#define TE 0x80 /* c: tolerAnt enable */
456
#define HSC 0x20 /* c: Halt SCSI Clock */
457
#define CSF 0x02 /* c: clear scsi fifo */
459
/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
461
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
462
#define SMODE_HVD 0x40 /* High Voltage Differential */
463
#define SMODE_SE 0x80 /* Single Ended */
464
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
465
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
466
/* bits 0-5 rsvd for C1010 */
469
/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
470
/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
471
#define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
472
#define PMJCTL 0x40 /* Phase Mismatch Jump Control */
473
#define ENNDJ 0x20 /* Enable Non Data PM Jump */
474
#define DISFC 0x10 /* Disable Auto FIFO Clear */
475
#define DILS 0x02 /* Disable Internal Load/Store */
476
#define DPR 0x01 /* Disable Pipe Req */
478
/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
479
#define ZMOD 0x80 /* High Impedance Mode */
480
#define DDAC 0x08 /* Disable Dual Address Cycle */
481
#define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
482
#define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
483
#define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
485
/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
488
/*5c*/ u8 nc_scr0; /* Working register B */
493
/*60*/ u8 nc_scrx[64]; /* Working register C-R */
494
/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
495
/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
496
/*a8*/ u32 nc_sfs; /* Script Fetch Selector */
497
/*ac*/ u32 nc_drs; /* DSA Relative Selector */
498
/*b0*/ u32 nc_sbms; /* Static Block Move Selector */
499
/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
500
/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
501
/*bc*/ u16 nc_scntl4; /* C1010 only */
502
#define U3EN 0x80 /* Enable Ultra 3 */
503
#define AIPCKEN 0x40 /* AIP checking enable */
504
/* Also enable AIP generation on C10-33*/
505
#define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
506
#define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
507
#define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
508
#define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
509
/*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
510
/*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */
511
#define DISAIP 0x08 /* Disable AIP generation C10-66 only */
512
/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
513
/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
514
/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
519
/*cc*/ u8 nc_ua; /* Updated Address */
523
/*d0*/ u32 nc_esa; /* Entry Storage Address */
524
/*d4*/ u8 nc_ia; /* Instruction Address */
528
/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
529
/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
530
/* Following for C1010 only */
531
/*e0*/ u16 nc_crcpad; /* CRC Value */
532
/*e2*/ u8 nc_crccntl0; /* CRC control register */
533
#define SNDCRC 0x10 /* Send CRC Request */
534
/*e3*/ u8 nc_crccntl1; /* CRC control register */
535
/*e4*/ u32 nc_crcdata; /* CRC data register */
538
/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
541
/*-----------------------------------------------------------
543
* Utility macros for the script.
545
*-----------------------------------------------------------
548
#define REGJ(p,r) (offsetof(struct sym_reg, p ## r))
549
#define REG(r) REGJ (nc_, r)
551
/*-----------------------------------------------------------
555
*-----------------------------------------------------------
558
#define SCR_DATA_OUT 0x00000000
559
#define SCR_DATA_IN 0x01000000
560
#define SCR_COMMAND 0x02000000
561
#define SCR_STATUS 0x03000000
562
#define SCR_DT_DATA_OUT 0x04000000
563
#define SCR_DT_DATA_IN 0x05000000
564
#define SCR_MSG_OUT 0x06000000
565
#define SCR_MSG_IN 0x07000000
566
/* DT phases are illegal for non Ultra3 mode */
567
#define SCR_ILG_OUT 0x04000000
568
#define SCR_ILG_IN 0x05000000
570
/*-----------------------------------------------------------
572
* Data transfer via SCSI.
574
*-----------------------------------------------------------
585
*-----------------------------------------------------------
588
#define OPC_MOVE 0x08000000
590
#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
591
/* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */
592
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
594
#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
595
/* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */
596
#define SCR_CHMOV_TBL (0x10000000)
598
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
599
/* We steal the `indirect addressing' flag for target mode MOVE in scripts */
601
#define OPC_TCHMOVE 0x08000000
603
#define SCR_TCHMOVE_ABS(l) ((0x20000000 | OPC_TCHMOVE) | (l))
604
#define SCR_TCHMOVE_TBL (0x30000000 | OPC_TCHMOVE)
606
#define SCR_TMOV_ABS(l) ((0x20000000) | (l))
607
#define SCR_TMOV_TBL (0x30000000)
615
/*-----------------------------------------------------------
619
*-----------------------------------------------------------
621
* SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
622
* <<alternate_address>>
624
* SEL_TBL | << dnad_offset>> [ | REL_JMP]
625
* <<alternate_address>>
627
*-----------------------------------------------------------
630
#define SCR_SEL_ABS 0x40000000
631
#define SCR_SEL_ABS_ATN 0x41000000
632
#define SCR_SEL_TBL 0x42000000
633
#define SCR_SEL_TBL_ATN 0x43000000
635
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
636
#define SCR_RESEL_ABS 0x40000000
637
#define SCR_RESEL_ABS_ATN 0x41000000
638
#define SCR_RESEL_TBL 0x42000000
639
#define SCR_RESEL_TBL_ATN 0x43000000
643
u_char sel_scntl4; /* C1010 only */
649
#define SCR_JMP_REL 0x04000000
650
#define SCR_ID(id) (((u32)(id)) << 16)
652
/*-----------------------------------------------------------
654
* Waiting for Disconnect or Reselect
656
*-----------------------------------------------------------
659
* dummy: <<alternate_address>>
662
* <<alternate_address>>
664
*-----------------------------------------------------------
667
#define SCR_WAIT_DISC 0x48000000
668
#define SCR_WAIT_RESEL 0x50000000
670
#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
671
#define SCR_DISCONNECT 0x48000000
674
/*-----------------------------------------------------------
678
*-----------------------------------------------------------
684
*-----------------------------------------------------------
687
#define SCR_SET(f) (0x58000000 | (f))
688
#define SCR_CLR(f) (0x60000000 | (f))
690
#define SCR_CARRY 0x00000400
691
#define SCR_TRG 0x00000200
692
#define SCR_ACK 0x00000040
693
#define SCR_ATN 0x00000008
696
/*-----------------------------------------------------------
698
* Memory to memory move
700
*-----------------------------------------------------------
703
* << source_address >>
704
* << destination_address >>
706
* SCR_COPY sets the NO FLUSH option by default.
707
* SCR_COPY_F does not set this option.
709
* For chips which do not support this option,
710
* sym_fw_bind_script() will remove this bit.
712
*-----------------------------------------------------------
715
#define SCR_NO_FLUSH 0x01000000
717
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
718
#define SCR_COPY_F(n) (0xc0000000 | (n))
720
/*-----------------------------------------------------------
722
* Register move and binary operations
724
*-----------------------------------------------------------
726
* SFBR_REG (reg, op, data) reg = SFBR op data
729
* REG_SFBR (reg, op, data) SFBR = reg op data
732
* REG_REG (reg, op, data) reg = reg op data
735
*-----------------------------------------------------------
737
* On 825A, 875, 895 and 896 chips the content
738
* of SFBR register can be used as data (SCR_SFBR_DATA).
739
* The 896 has additionnal IO registers starting at
740
* offset 0x80. Bit 7 of register offset is stored in
741
* bit 7 of the SCRIPTS instruction first DWORD.
743
*-----------------------------------------------------------
746
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
748
#define SCR_SFBR_REG(reg,op,data) \
749
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
751
#define SCR_REG_SFBR(reg,op,data) \
752
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
754
#define SCR_REG_REG(reg,op,data) \
755
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
758
#define SCR_LOAD 0x00000000
759
#define SCR_SHL 0x01000000
760
#define SCR_OR 0x02000000
761
#define SCR_XOR 0x03000000
762
#define SCR_AND 0x04000000
763
#define SCR_SHR 0x05000000
764
#define SCR_ADD 0x06000000
765
#define SCR_ADDC 0x07000000
767
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
769
/*-----------------------------------------------------------
771
* FROM_REG (reg) SFBR = reg
774
* TO_REG (reg) reg = SFBR
777
* LOAD_REG (reg, data) reg = <data>
780
* LOAD_SFBR(data) SFBR = <data>
783
*-----------------------------------------------------------
786
#define SCR_FROM_REG(reg) \
787
SCR_REG_SFBR(reg,SCR_OR,0)
789
#define SCR_TO_REG(reg) \
790
SCR_SFBR_REG(reg,SCR_OR,0)
792
#define SCR_LOAD_REG(reg,data) \
793
SCR_REG_REG(reg,SCR_LOAD,data)
795
#define SCR_LOAD_SFBR(data) \
796
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
798
/*-----------------------------------------------------------
800
* LOAD from memory to register.
801
* STORE from register to memory.
803
* Only supported by 810A, 860, 825A, 875, 895 and 896.
805
*-----------------------------------------------------------
810
* LOAD_REL (LEN) (DSA relative)
813
*-----------------------------------------------------------
816
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
817
#define SCR_NO_FLUSH2 0x02000000
818
#define SCR_DSA_REL2 0x10000000
820
#define SCR_LOAD_R(reg, how, n) \
821
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
823
#define SCR_STORE_R(reg, how, n) \
824
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
826
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
827
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
828
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
829
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
831
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
832
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
833
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
834
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
837
/*-----------------------------------------------------------
839
* Waiting for Disconnect or Reselect
841
*-----------------------------------------------------------
843
* JUMP [ | IFTRUE/IFFALSE ( ... ) ]
846
* JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
849
* CALL [ | IFTRUE/IFFALSE ( ... ) ]
852
* CALLR [ | IFTRUE/IFFALSE ( ... ) ]
855
* RETURN [ | IFTRUE/IFFALSE ( ... ) ]
858
* INT [ | IFTRUE/IFFALSE ( ... ) ]
861
* INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
870
*-----------------------------------------------------------
873
#define SCR_NO_OP 0x80000000
874
#define SCR_JUMP 0x80080000
875
#define SCR_JUMP64 0x80480000
876
#define SCR_JUMPR 0x80880000
877
#define SCR_CALL 0x88080000
878
#define SCR_CALLR 0x88880000
879
#define SCR_RETURN 0x90080000
880
#define SCR_INT 0x98080000
881
#define SCR_INT_FLY 0x98180000
883
#define IFFALSE(arg) (0x00080000 | (arg))
884
#define IFTRUE(arg) (0x00000000 | (arg))
886
#define WHEN(phase) (0x00030000 | (phase))
887
#define IF(phase) (0x00020000 | (phase))
889
#define DATA(D) (0x00040000 | ((D) & 0xff))
890
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
892
#define CARRYSET (0x00200000)
894
/*-----------------------------------------------------------
898
*-----------------------------------------------------------
905
#define M_COMPLETE (0x00)
906
#define M_EXTENDED (0x01)
907
#define M_SAVE_DP (0x02)
908
#define M_RESTORE_DP (0x03)
909
#define M_DISCONNECT (0x04)
910
#define M_ID_ERROR (0x05)
911
#define M_ABORT (0x06)
912
#define M_REJECT (0x07)
913
#define M_NOOP (0x08)
914
#define M_PARITY (0x09)
915
#define M_LCOMPLETE (0x0a)
916
#define M_FCOMPLETE (0x0b)
917
#define M_RESET (0x0c)
918
#define M_ABORT_TAG (0x0d)
919
#define M_CLEAR_QUEUE (0x0e)
920
#define M_INIT_REC (0x0f)
921
#define M_REL_REC (0x10)
922
#define M_TERMINATE (0x11)
923
#define M_SIMPLE_TAG (0x20)
924
#define M_HEAD_TAG (0x21)
925
#define M_ORDERED_TAG (0x22)
926
#define M_IGN_RESIDUE (0x23)
927
#define M_IDENTIFY (0x80)
929
#define M_X_MODIFY_DP (0x00)
930
#define M_X_SYNC_REQ (0x01)
931
#define M_X_WIDE_REQ (0x03)
932
#define M_X_PPR_REQ (0x04)
935
* PPR protocol options
937
#define PPR_OPT_IU (0x01)
938
#define PPR_OPT_DT (0x02)
939
#define PPR_OPT_QAS (0x04)
940
#define PPR_OPT_MASK (0x07)
946
#define S_GOOD (0x00)
947
#define S_CHECK_COND (0x02)
948
#define S_COND_MET (0x04)
949
#define S_BUSY (0x08)
951
#define S_INT_COND_MET (0x14)
952
#define S_CONFLICT (0x18)
953
#define S_TERMINATED (0x20)
954
#define S_QUEUE_FULL (0x28)
955
#define S_ILLEGAL (0xff)
957
#endif /* defined SYM_DEFS_H */
added
removed
xen/drivers/scsi/sym53c8xx_2/sym_defs.h
