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/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
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* tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
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* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
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* Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
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#define TG3_64BIT_REG_HIGH 0x00UL
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#define TG3_64BIT_REG_LOW 0x04UL
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/* Descriptor block info. */
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#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
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#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
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#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
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#define BDINFO_FLAGS_DISABLED 0x00000002
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#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
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#define BDINFO_FLAGS_MAXLEN_SHIFT 16
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#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
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#define TG3_BDINFO_SIZE 0x10UL
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#define RX_COPY_THRESHOLD 0 /* No CopyBreak for Xen */
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#define RX_STD_MAX_SIZE 1536
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#define RX_STD_MAX_SIZE_5705 512
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#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
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/* First 256 bytes are a mirror of PCI config space. */
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#define TG3PCI_VENDOR 0x00000000
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#define TG3PCI_VENDOR_BROADCOM 0x14e4
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#define TG3PCI_DEVICE 0x00000002
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#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
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#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
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#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
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#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
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#define TG3PCI_COMMAND 0x00000004
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#define TG3PCI_STATUS 0x00000006
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#define TG3PCI_CCREVID 0x00000008
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#define TG3PCI_CACHELINESZ 0x0000000c
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#define TG3PCI_LATTIMER 0x0000000d
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#define TG3PCI_HEADERTYPE 0x0000000e
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#define TG3PCI_BIST 0x0000000f
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#define TG3PCI_BASE0_LOW 0x00000010
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#define TG3PCI_BASE0_HIGH 0x00000014
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/* 0x18 --> 0x2c unused */
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#define TG3PCI_SUBSYSVENID 0x0000002c
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#define TG3PCI_SUBSYSID 0x0000002e
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#define TG3PCI_ROMADDR 0x00000030
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#define TG3PCI_CAPLIST 0x00000034
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/* 0x35 --> 0x3c unused */
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#define TG3PCI_IRQ_LINE 0x0000003c
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#define TG3PCI_IRQ_PIN 0x0000003d
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#define TG3PCI_MIN_GNT 0x0000003e
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#define TG3PCI_MAX_LAT 0x0000003f
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#define TG3PCI_X_CAPS 0x00000040
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#define PCIX_CAPS_RELAXED_ORDERING 0x00020000
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#define PCIX_CAPS_SPLIT_MASK 0x00700000
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#define PCIX_CAPS_SPLIT_SHIFT 20
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#define PCIX_CAPS_BURST_MASK 0x000c0000
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#define PCIX_CAPS_BURST_SHIFT 18
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#define PCIX_CAPS_MAX_BURST_CPIOB 2
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#define TG3PCI_PM_CAP_PTR 0x00000041
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#define TG3PCI_X_COMMAND 0x00000042
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#define TG3PCI_X_STATUS 0x00000044
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#define TG3PCI_PM_CAP_ID 0x00000048
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#define TG3PCI_VPD_CAP_PTR 0x00000049
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#define TG3PCI_PM_CAPS 0x0000004a
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#define TG3PCI_PM_CTRL_STAT 0x0000004c
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#define TG3PCI_BR_SUPP_EXT 0x0000004e
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#define TG3PCI_PM_DATA 0x0000004f
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#define TG3PCI_VPD_CAP_ID 0x00000050
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#define TG3PCI_MSI_CAP_PTR 0x00000051
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#define TG3PCI_VPD_ADDR_FLAG 0x00000052
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#define VPD_ADDR_FLAG_WRITE 0x00008000
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#define TG3PCI_VPD_DATA 0x00000054
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#define TG3PCI_MSI_CAP_ID 0x00000058
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#define TG3PCI_NXT_CAP_PTR 0x00000059
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#define TG3PCI_MSI_CTRL 0x0000005a
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#define TG3PCI_MSI_ADDR_LOW 0x0000005c
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#define TG3PCI_MSI_ADDR_HIGH 0x00000060
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#define TG3PCI_MSI_DATA 0x00000064
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/* 0x66 --> 0x68 unused */
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#define TG3PCI_MISC_HOST_CTRL 0x00000068
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#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
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#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
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#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
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#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
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#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
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#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
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#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
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#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
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#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
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#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
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#define MISC_HOST_CTRL_CHIPREV 0xffff0000
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#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
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#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
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(((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
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MISC_HOST_CTRL_CHIPREV_SHIFT)
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#define CHIPREV_ID_5700_A0 0x7000
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#define CHIPREV_ID_5700_A1 0x7001
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#define CHIPREV_ID_5700_B0 0x7100
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#define CHIPREV_ID_5700_B1 0x7101
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#define CHIPREV_ID_5700_B3 0x7102
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#define CHIPREV_ID_5700_ALTIMA 0x7104
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#define CHIPREV_ID_5700_C0 0x7200
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#define CHIPREV_ID_5701_A0 0x0000
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#define CHIPREV_ID_5701_B0 0x0100
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#define CHIPREV_ID_5701_B2 0x0102
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#define CHIPREV_ID_5701_B5 0x0105
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#define CHIPREV_ID_5703_A0 0x1000
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#define CHIPREV_ID_5703_A1 0x1001
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#define CHIPREV_ID_5703_A2 0x1002
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#define CHIPREV_ID_5703_A3 0x1003
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#define CHIPREV_ID_5704_A0 0x2000
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#define CHIPREV_ID_5704_A1 0x2001
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#define CHIPREV_ID_5704_A2 0x2002
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#define CHIPREV_ID_5705_A0 0x3000
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#define CHIPREV_ID_5705_A1 0x3001
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#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
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#define ASIC_REV_5700 0x07
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#define ASIC_REV_5701 0x00
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#define ASIC_REV_5703 0x01
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#define ASIC_REV_5704 0x02
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#define ASIC_REV_5705 0x03
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#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
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#define CHIPREV_5700_AX 0x70
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#define CHIPREV_5700_BX 0x71
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#define CHIPREV_5700_CX 0x72
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#define CHIPREV_5701_AX 0x00
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#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
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#define METAL_REV_A0 0x00
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#define METAL_REV_A1 0x01
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#define METAL_REV_B0 0x00
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#define METAL_REV_B1 0x01
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#define METAL_REV_B2 0x02
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#define TG3PCI_DMA_RW_CTRL 0x0000006c
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#define DMA_RWCTRL_MIN_DMA 0x000000ff
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#define DMA_RWCTRL_MIN_DMA_SHIFT 0
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#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
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#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
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#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
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#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
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#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
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#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
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#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
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#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
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#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
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#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
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#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
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#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
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#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
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#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
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#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
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#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
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#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
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#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
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#define DMA_RWCTRL_ONE_DMA 0x00004000
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#define DMA_RWCTRL_READ_WATER 0x00070000
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#define DMA_RWCTRL_READ_WATER_SHIFT 16
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#define DMA_RWCTRL_WRITE_WATER 0x00380000
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#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
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#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
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#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
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#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
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#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
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#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
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#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
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#define TG3PCI_PCISTATE 0x00000070
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#define PCISTATE_FORCE_RESET 0x00000001
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#define PCISTATE_INT_NOT_ACTIVE 0x00000002
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#define PCISTATE_CONV_PCI_MODE 0x00000004
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#define PCISTATE_BUS_SPEED_HIGH 0x00000008
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#define PCISTATE_BUS_32BIT 0x00000010
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#define PCISTATE_ROM_ENABLE 0x00000020
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#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
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#define PCISTATE_FLAT_VIEW 0x00000100
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#define PCISTATE_RETRY_SAME_DMA 0x00002000
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#define TG3PCI_CLOCK_CTRL 0x00000074
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#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
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#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
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#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
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#define CLOCK_CTRL_ALTCLK 0x00001000
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#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
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#define CLOCK_CTRL_44MHZ_CORE 0x00040000
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#define CLOCK_CTRL_625_CORE 0x00100000
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#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
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#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
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#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
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#define TG3PCI_REG_BASE_ADDR 0x00000078
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#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
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#define TG3PCI_REG_DATA 0x00000080
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#define TG3PCI_MEM_WIN_DATA 0x00000084
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#define TG3PCI_MODE_CTRL 0x00000088
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#define TG3PCI_MISC_CFG 0x0000008c
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#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
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/* 0x94 --> 0x98 unused */
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#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
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#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
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#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
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/* 0xb0 --> 0x100 unused */
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/* 0x100 --> 0x200 unused */
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/* Mailbox registers */
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#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
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#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
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#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
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#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
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#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
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#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
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#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
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#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
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#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
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#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
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#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
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#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
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#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
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#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
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#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
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#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
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#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
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#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
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#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
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/* MAC control registers */
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#define MAC_MODE 0x00000400
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#define MAC_MODE_RESET 0x00000001
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#define MAC_MODE_HALF_DUPLEX 0x00000002
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#define MAC_MODE_PORT_MODE_MASK 0x0000000c
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#define MAC_MODE_PORT_MODE_TBI 0x0000000c
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#define MAC_MODE_PORT_MODE_GMII 0x00000008
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#define MAC_MODE_PORT_MODE_MII 0x00000004
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#define MAC_MODE_PORT_MODE_NONE 0x00000000
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#define MAC_MODE_PORT_INT_LPBACK 0x00000010
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#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
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#define MAC_MODE_TX_BURSTING 0x00000100
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#define MAC_MODE_MAX_DEFER 0x00000200
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#define MAC_MODE_LINK_POLARITY 0x00000400
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#define MAC_MODE_RXSTAT_ENABLE 0x00000800
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#define MAC_MODE_RXSTAT_CLEAR 0x00001000
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#define MAC_MODE_RXSTAT_FLUSH 0x00002000
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#define MAC_MODE_TXSTAT_ENABLE 0x00004000
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#define MAC_MODE_TXSTAT_CLEAR 0x00008000
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#define MAC_MODE_TXSTAT_FLUSH 0x00010000
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#define MAC_MODE_SEND_CONFIGS 0x00020000
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#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
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#define MAC_MODE_ACPI_ENABLE 0x00080000
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#define MAC_MODE_MIP_ENABLE 0x00100000
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#define MAC_MODE_TDE_ENABLE 0x00200000
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#define MAC_MODE_RDE_ENABLE 0x00400000
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#define MAC_MODE_FHDE_ENABLE 0x00800000
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#define MAC_STATUS 0x00000404
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#define MAC_STATUS_PCS_SYNCED 0x00000001
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#define MAC_STATUS_SIGNAL_DET 0x00000002
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#define MAC_STATUS_RCVD_CFG 0x00000004
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#define MAC_STATUS_CFG_CHANGED 0x00000008
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#define MAC_STATUS_SYNC_CHANGED 0x00000010
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#define MAC_STATUS_PORT_DEC_ERR 0x00000400
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#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
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#define MAC_STATUS_MI_COMPLETION 0x00400000
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#define MAC_STATUS_MI_INTERRUPT 0x00800000
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#define MAC_STATUS_AP_ERROR 0x01000000
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#define MAC_STATUS_ODI_ERROR 0x02000000
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#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
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#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
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#define MAC_EVENT 0x00000408
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#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
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#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
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#define MAC_EVENT_MI_COMPLETION 0x00400000
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#define MAC_EVENT_MI_INTERRUPT 0x00800000
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#define MAC_EVENT_AP_ERROR 0x01000000
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#define MAC_EVENT_ODI_ERROR 0x02000000
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#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
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#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
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#define MAC_LED_CTRL 0x0000040c
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#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
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#define LED_CTRL_1000MBPS_ON 0x00000002
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#define LED_CTRL_100MBPS_ON 0x00000004
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#define LED_CTRL_10MBPS_ON 0x00000008
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#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
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#define LED_CTRL_TRAFFIC_BLINK 0x00000020
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#define LED_CTRL_TRAFFIC_LED 0x00000040
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#define LED_CTRL_1000MBPS_STATUS 0x00000080
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#define LED_CTRL_100MBPS_STATUS 0x00000100
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#define LED_CTRL_10MBPS_STATUS 0x00000200
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#define LED_CTRL_TRAFFIC_STATUS 0x00000400
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#define LED_CTRL_MAC_MODE 0x00000000
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#define LED_CTRL_PHY_MODE_1 0x00000800
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#define LED_CTRL_PHY_MODE_2 0x00001000
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#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
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#define LED_CTRL_BLINK_RATE_SHIFT 19
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#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
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#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
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#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
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#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
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#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
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#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
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#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
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#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
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#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
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#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
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#define MAC_ACPI_MBUF_PTR 0x00000430
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#define MAC_ACPI_LEN_OFFSET 0x00000434
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#define ACPI_LENOFF_LEN_MASK 0x0000ffff
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#define ACPI_LENOFF_LEN_SHIFT 0
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#define ACPI_LENOFF_OFF_MASK 0x0fff0000
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#define ACPI_LENOFF_OFF_SHIFT 16
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#define MAC_TX_BACKOFF_SEED 0x00000438
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#define TX_BACKOFF_SEED_MASK 0x000003ff
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#define MAC_RX_MTU_SIZE 0x0000043c
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#define RX_MTU_SIZE_MASK 0x0000ffff
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#define MAC_PCS_TEST 0x00000440
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#define PCS_TEST_PATTERN_MASK 0x000fffff
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#define PCS_TEST_PATTERN_SHIFT 0
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#define PCS_TEST_ENABLE 0x00100000
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#define MAC_TX_AUTO_NEG 0x00000444
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#define TX_AUTO_NEG_MASK 0x0000ffff
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#define TX_AUTO_NEG_SHIFT 0
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#define MAC_RX_AUTO_NEG 0x00000448
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#define RX_AUTO_NEG_MASK 0x0000ffff
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#define RX_AUTO_NEG_SHIFT 0
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#define MAC_MI_COM 0x0000044c
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#define MI_COM_CMD_MASK 0x0c000000
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#define MI_COM_CMD_WRITE 0x04000000
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#define MI_COM_CMD_READ 0x08000000
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#define MI_COM_READ_FAILED 0x10000000
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#define MI_COM_START 0x20000000
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#define MI_COM_BUSY 0x20000000
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#define MI_COM_PHY_ADDR_MASK 0x03e00000
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#define MI_COM_PHY_ADDR_SHIFT 21
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#define MI_COM_REG_ADDR_MASK 0x001f0000
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#define MI_COM_REG_ADDR_SHIFT 16
380
#define MI_COM_DATA_MASK 0x0000ffff
381
#define MAC_MI_STAT 0x00000450
382
#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
383
#define MAC_MI_MODE 0x00000454
384
#define MAC_MI_MODE_CLK_10MHZ 0x00000001
385
#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
386
#define MAC_MI_MODE_AUTO_POLL 0x00000010
387
#define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
388
#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
389
#define MAC_AUTO_POLL_STATUS 0x00000458
390
#define MAC_AUTO_POLL_ERROR 0x00000001
391
#define MAC_TX_MODE 0x0000045c
392
#define TX_MODE_RESET 0x00000001
393
#define TX_MODE_ENABLE 0x00000002
394
#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
395
#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
396
#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
397
#define MAC_TX_STATUS 0x00000460
398
#define TX_STATUS_XOFFED 0x00000001
399
#define TX_STATUS_SENT_XOFF 0x00000002
400
#define TX_STATUS_SENT_XON 0x00000004
401
#define TX_STATUS_LINK_UP 0x00000008
402
#define TX_STATUS_ODI_UNDERRUN 0x00000010
403
#define TX_STATUS_ODI_OVERRUN 0x00000020
404
#define MAC_TX_LENGTHS 0x00000464
405
#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
406
#define TX_LENGTHS_SLOT_TIME_SHIFT 0
407
#define TX_LENGTHS_IPG_MASK 0x00000f00
408
#define TX_LENGTHS_IPG_SHIFT 8
409
#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
410
#define TX_LENGTHS_IPG_CRS_SHIFT 12
411
#define MAC_RX_MODE 0x00000468
412
#define RX_MODE_RESET 0x00000001
413
#define RX_MODE_ENABLE 0x00000002
414
#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
415
#define RX_MODE_KEEP_MAC_CTRL 0x00000008
416
#define RX_MODE_KEEP_PAUSE 0x00000010
417
#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
418
#define RX_MODE_ACCEPT_RUNTS 0x00000040
419
#define RX_MODE_LEN_CHECK 0x00000080
420
#define RX_MODE_PROMISC 0x00000100
421
#define RX_MODE_NO_CRC_CHECK 0x00000200
422
#define RX_MODE_KEEP_VLAN_TAG 0x00000400
423
#define MAC_RX_STATUS 0x0000046c
424
#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
425
#define RX_STATUS_XOFF_RCVD 0x00000002
426
#define RX_STATUS_XON_RCVD 0x00000004
427
#define MAC_HASH_REG_0 0x00000470
428
#define MAC_HASH_REG_1 0x00000474
429
#define MAC_HASH_REG_2 0x00000478
430
#define MAC_HASH_REG_3 0x0000047c
431
#define MAC_RCV_RULE_0 0x00000480
432
#define MAC_RCV_VALUE_0 0x00000484
433
#define MAC_RCV_RULE_1 0x00000488
434
#define MAC_RCV_VALUE_1 0x0000048c
435
#define MAC_RCV_RULE_2 0x00000490
436
#define MAC_RCV_VALUE_2 0x00000494
437
#define MAC_RCV_RULE_3 0x00000498
438
#define MAC_RCV_VALUE_3 0x0000049c
439
#define MAC_RCV_RULE_4 0x000004a0
440
#define MAC_RCV_VALUE_4 0x000004a4
441
#define MAC_RCV_RULE_5 0x000004a8
442
#define MAC_RCV_VALUE_5 0x000004ac
443
#define MAC_RCV_RULE_6 0x000004b0
444
#define MAC_RCV_VALUE_6 0x000004b4
445
#define MAC_RCV_RULE_7 0x000004b8
446
#define MAC_RCV_VALUE_7 0x000004bc
447
#define MAC_RCV_RULE_8 0x000004c0
448
#define MAC_RCV_VALUE_8 0x000004c4
449
#define MAC_RCV_RULE_9 0x000004c8
450
#define MAC_RCV_VALUE_9 0x000004cc
451
#define MAC_RCV_RULE_10 0x000004d0
452
#define MAC_RCV_VALUE_10 0x000004d4
453
#define MAC_RCV_RULE_11 0x000004d8
454
#define MAC_RCV_VALUE_11 0x000004dc
455
#define MAC_RCV_RULE_12 0x000004e0
456
#define MAC_RCV_VALUE_12 0x000004e4
457
#define MAC_RCV_RULE_13 0x000004e8
458
#define MAC_RCV_VALUE_13 0x000004ec
459
#define MAC_RCV_RULE_14 0x000004f0
460
#define MAC_RCV_VALUE_14 0x000004f4
461
#define MAC_RCV_RULE_15 0x000004f8
462
#define MAC_RCV_VALUE_15 0x000004fc
463
#define RCV_RULE_DISABLE_MASK 0x7fffffff
464
#define MAC_RCV_RULE_CFG 0x00000500
465
#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
466
#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
467
/* 0x508 --> 0x520 unused */
468
#define MAC_HASHREGU_0 0x00000520
469
#define MAC_HASHREGU_1 0x00000524
470
#define MAC_HASHREGU_2 0x00000528
471
#define MAC_HASHREGU_3 0x0000052c
472
#define MAC_EXTADDR_0_HIGH 0x00000530
473
#define MAC_EXTADDR_0_LOW 0x00000534
474
#define MAC_EXTADDR_1_HIGH 0x00000538
475
#define MAC_EXTADDR_1_LOW 0x0000053c
476
#define MAC_EXTADDR_2_HIGH 0x00000540
477
#define MAC_EXTADDR_2_LOW 0x00000544
478
#define MAC_EXTADDR_3_HIGH 0x00000548
479
#define MAC_EXTADDR_3_LOW 0x0000054c
480
#define MAC_EXTADDR_4_HIGH 0x00000550
481
#define MAC_EXTADDR_4_LOW 0x00000554
482
#define MAC_EXTADDR_5_HIGH 0x00000558
483
#define MAC_EXTADDR_5_LOW 0x0000055c
484
#define MAC_EXTADDR_6_HIGH 0x00000560
485
#define MAC_EXTADDR_6_LOW 0x00000564
486
#define MAC_EXTADDR_7_HIGH 0x00000568
487
#define MAC_EXTADDR_7_LOW 0x0000056c
488
#define MAC_EXTADDR_8_HIGH 0x00000570
489
#define MAC_EXTADDR_8_LOW 0x00000574
490
#define MAC_EXTADDR_9_HIGH 0x00000578
491
#define MAC_EXTADDR_9_LOW 0x0000057c
492
#define MAC_EXTADDR_10_HIGH 0x00000580
493
#define MAC_EXTADDR_10_LOW 0x00000584
494
#define MAC_EXTADDR_11_HIGH 0x00000588
495
#define MAC_EXTADDR_11_LOW 0x0000058c
496
#define MAC_SERDES_CFG 0x00000590
497
#define MAC_SERDES_STAT 0x00000594
498
/* 0x598 --> 0x600 unused */
499
#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
500
#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
501
/* 0x624 --> 0x800 unused */
502
#define MAC_TX_STATS_OCTETS 0x00000800
503
#define MAC_TX_STATS_RESV1 0x00000804
504
#define MAC_TX_STATS_COLLISIONS 0x00000808
505
#define MAC_TX_STATS_XON_SENT 0x0000080c
506
#define MAC_TX_STATS_XOFF_SENT 0x00000810
507
#define MAC_TX_STATS_RESV2 0x00000814
508
#define MAC_TX_STATS_MAC_ERRORS 0x00000818
509
#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
510
#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
511
#define MAC_TX_STATS_DEFERRED 0x00000824
512
#define MAC_TX_STATS_RESV3 0x00000828
513
#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
514
#define MAC_TX_STATS_LATE_COL 0x00000830
515
#define MAC_TX_STATS_RESV4_1 0x00000834
516
#define MAC_TX_STATS_RESV4_2 0x00000838
517
#define MAC_TX_STATS_RESV4_3 0x0000083c
518
#define MAC_TX_STATS_RESV4_4 0x00000840
519
#define MAC_TX_STATS_RESV4_5 0x00000844
520
#define MAC_TX_STATS_RESV4_6 0x00000848
521
#define MAC_TX_STATS_RESV4_7 0x0000084c
522
#define MAC_TX_STATS_RESV4_8 0x00000850
523
#define MAC_TX_STATS_RESV4_9 0x00000854
524
#define MAC_TX_STATS_RESV4_10 0x00000858
525
#define MAC_TX_STATS_RESV4_11 0x0000085c
526
#define MAC_TX_STATS_RESV4_12 0x00000860
527
#define MAC_TX_STATS_RESV4_13 0x00000864
528
#define MAC_TX_STATS_RESV4_14 0x00000868
529
#define MAC_TX_STATS_UCAST 0x0000086c
530
#define MAC_TX_STATS_MCAST 0x00000870
531
#define MAC_TX_STATS_BCAST 0x00000874
532
#define MAC_TX_STATS_RESV5_1 0x00000878
533
#define MAC_TX_STATS_RESV5_2 0x0000087c
534
#define MAC_RX_STATS_OCTETS 0x00000880
535
#define MAC_RX_STATS_RESV1 0x00000884
536
#define MAC_RX_STATS_FRAGMENTS 0x00000888
537
#define MAC_RX_STATS_UCAST 0x0000088c
538
#define MAC_RX_STATS_MCAST 0x00000890
539
#define MAC_RX_STATS_BCAST 0x00000894
540
#define MAC_RX_STATS_FCS_ERRORS 0x00000898
541
#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
542
#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
543
#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
544
#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
545
#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
546
#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
547
#define MAC_RX_STATS_JABBERS 0x000008b4
548
#define MAC_RX_STATS_UNDERSIZE 0x000008b8
549
/* 0x8bc --> 0xc00 unused */
551
/* Send data initiator control registers */
552
#define SNDDATAI_MODE 0x00000c00
553
#define SNDDATAI_MODE_RESET 0x00000001
554
#define SNDDATAI_MODE_ENABLE 0x00000002
555
#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
556
#define SNDDATAI_STATUS 0x00000c04
557
#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
558
#define SNDDATAI_STATSCTRL 0x00000c08
559
#define SNDDATAI_SCTRL_ENABLE 0x00000001
560
#define SNDDATAI_SCTRL_FASTUPD 0x00000002
561
#define SNDDATAI_SCTRL_CLEAR 0x00000004
562
#define SNDDATAI_SCTRL_FLUSH 0x00000008
563
#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
564
#define SNDDATAI_STATSENAB 0x00000c0c
565
#define SNDDATAI_STATSINCMASK 0x00000c10
566
/* 0xc14 --> 0xc80 unused */
567
#define SNDDATAI_COS_CNT_0 0x00000c80
568
#define SNDDATAI_COS_CNT_1 0x00000c84
569
#define SNDDATAI_COS_CNT_2 0x00000c88
570
#define SNDDATAI_COS_CNT_3 0x00000c8c
571
#define SNDDATAI_COS_CNT_4 0x00000c90
572
#define SNDDATAI_COS_CNT_5 0x00000c94
573
#define SNDDATAI_COS_CNT_6 0x00000c98
574
#define SNDDATAI_COS_CNT_7 0x00000c9c
575
#define SNDDATAI_COS_CNT_8 0x00000ca0
576
#define SNDDATAI_COS_CNT_9 0x00000ca4
577
#define SNDDATAI_COS_CNT_10 0x00000ca8
578
#define SNDDATAI_COS_CNT_11 0x00000cac
579
#define SNDDATAI_COS_CNT_12 0x00000cb0
580
#define SNDDATAI_COS_CNT_13 0x00000cb4
581
#define SNDDATAI_COS_CNT_14 0x00000cb8
582
#define SNDDATAI_COS_CNT_15 0x00000cbc
583
#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
584
#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
585
#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
586
#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
587
#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
588
#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
589
#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
590
#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
591
/* 0xce0 --> 0x1000 unused */
593
/* Send data completion control registers */
594
#define SNDDATAC_MODE 0x00001000
595
#define SNDDATAC_MODE_RESET 0x00000001
596
#define SNDDATAC_MODE_ENABLE 0x00000002
597
/* 0x1004 --> 0x1400 unused */
599
/* Send BD ring selector */
600
#define SNDBDS_MODE 0x00001400
601
#define SNDBDS_MODE_RESET 0x00000001
602
#define SNDBDS_MODE_ENABLE 0x00000002
603
#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
604
#define SNDBDS_STATUS 0x00001404
605
#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
606
#define SNDBDS_HWDIAG 0x00001408
607
/* 0x140c --> 0x1440 */
608
#define SNDBDS_SEL_CON_IDX_0 0x00001440
609
#define SNDBDS_SEL_CON_IDX_1 0x00001444
610
#define SNDBDS_SEL_CON_IDX_2 0x00001448
611
#define SNDBDS_SEL_CON_IDX_3 0x0000144c
612
#define SNDBDS_SEL_CON_IDX_4 0x00001450
613
#define SNDBDS_SEL_CON_IDX_5 0x00001454
614
#define SNDBDS_SEL_CON_IDX_6 0x00001458
615
#define SNDBDS_SEL_CON_IDX_7 0x0000145c
616
#define SNDBDS_SEL_CON_IDX_8 0x00001460
617
#define SNDBDS_SEL_CON_IDX_9 0x00001464
618
#define SNDBDS_SEL_CON_IDX_10 0x00001468
619
#define SNDBDS_SEL_CON_IDX_11 0x0000146c
620
#define SNDBDS_SEL_CON_IDX_12 0x00001470
621
#define SNDBDS_SEL_CON_IDX_13 0x00001474
622
#define SNDBDS_SEL_CON_IDX_14 0x00001478
623
#define SNDBDS_SEL_CON_IDX_15 0x0000147c
624
/* 0x1480 --> 0x1800 unused */
626
/* Send BD initiator control registers */
627
#define SNDBDI_MODE 0x00001800
628
#define SNDBDI_MODE_RESET 0x00000001
629
#define SNDBDI_MODE_ENABLE 0x00000002
630
#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
631
#define SNDBDI_STATUS 0x00001804
632
#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
633
#define SNDBDI_IN_PROD_IDX_0 0x00001808
634
#define SNDBDI_IN_PROD_IDX_1 0x0000180c
635
#define SNDBDI_IN_PROD_IDX_2 0x00001810
636
#define SNDBDI_IN_PROD_IDX_3 0x00001814
637
#define SNDBDI_IN_PROD_IDX_4 0x00001818
638
#define SNDBDI_IN_PROD_IDX_5 0x0000181c
639
#define SNDBDI_IN_PROD_IDX_6 0x00001820
640
#define SNDBDI_IN_PROD_IDX_7 0x00001824
641
#define SNDBDI_IN_PROD_IDX_8 0x00001828
642
#define SNDBDI_IN_PROD_IDX_9 0x0000182c
643
#define SNDBDI_IN_PROD_IDX_10 0x00001830
644
#define SNDBDI_IN_PROD_IDX_11 0x00001834
645
#define SNDBDI_IN_PROD_IDX_12 0x00001838
646
#define SNDBDI_IN_PROD_IDX_13 0x0000183c
647
#define SNDBDI_IN_PROD_IDX_14 0x00001840
648
#define SNDBDI_IN_PROD_IDX_15 0x00001844
649
/* 0x1848 --> 0x1c00 unused */
651
/* Send BD completion control registers */
652
#define SNDBDC_MODE 0x00001c00
653
#define SNDBDC_MODE_RESET 0x00000001
654
#define SNDBDC_MODE_ENABLE 0x00000002
655
#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
656
/* 0x1c04 --> 0x2000 unused */
658
/* Receive list placement control registers */
659
#define RCVLPC_MODE 0x00002000
660
#define RCVLPC_MODE_RESET 0x00000001
661
#define RCVLPC_MODE_ENABLE 0x00000002
662
#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
663
#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
664
#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
665
#define RCVLPC_STATUS 0x00002004
666
#define RCVLPC_STATUS_CLASS0 0x00000004
667
#define RCVLPC_STATUS_MAPOOR 0x00000008
668
#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
669
#define RCVLPC_LOCK 0x00002008
670
#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
671
#define RCVLPC_LOCK_REQ_SHIFT 0
672
#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
673
#define RCVLPC_LOCK_GRANT_SHIFT 16
674
#define RCVLPC_NON_EMPTY_BITS 0x0000200c
675
#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
676
#define RCVLPC_CONFIG 0x00002010
677
#define RCVLPC_STATSCTRL 0x00002014
678
#define RCVLPC_STATSCTRL_ENABLE 0x00000001
679
#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
680
#define RCVLPC_STATS_ENABLE 0x00002018
681
#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
682
#define RCVLPC_STATS_INCMASK 0x0000201c
683
/* 0x2020 --> 0x2100 unused */
684
#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
685
#define SELLST_TAIL 0x00000004
686
#define SELLST_CONT 0x00000008
687
#define SELLST_UNUSED 0x0000000c
688
#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
689
#define RCVLPC_DROP_FILTER_CNT 0x00002240
690
#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
691
#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
692
#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
693
#define RCVLPC_IN_DISCARDS_CNT 0x00002250
694
#define RCVLPC_IN_ERRORS_CNT 0x00002254
695
#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
696
/* 0x225c --> 0x2400 unused */
698
/* Receive Data and Receive BD Initiator Control */
699
#define RCVDBDI_MODE 0x00002400
700
#define RCVDBDI_MODE_RESET 0x00000001
701
#define RCVDBDI_MODE_ENABLE 0x00000002
702
#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
703
#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
704
#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
705
#define RCVDBDI_STATUS 0x00002404
706
#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
707
#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
708
#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
709
#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
710
/* 0x240c --> 0x2440 unused */
711
#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
712
#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
713
#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
714
#define RCVDBDI_JUMBO_CON_IDX 0x00002470
715
#define RCVDBDI_STD_CON_IDX 0x00002474
716
#define RCVDBDI_MINI_CON_IDX 0x00002478
717
/* 0x247c --> 0x2480 unused */
718
#define RCVDBDI_BD_PROD_IDX_0 0x00002480
719
#define RCVDBDI_BD_PROD_IDX_1 0x00002484
720
#define RCVDBDI_BD_PROD_IDX_2 0x00002488
721
#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
722
#define RCVDBDI_BD_PROD_IDX_4 0x00002490
723
#define RCVDBDI_BD_PROD_IDX_5 0x00002494
724
#define RCVDBDI_BD_PROD_IDX_6 0x00002498
725
#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
726
#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
727
#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
728
#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
729
#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
730
#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
731
#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
732
#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
733
#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
734
#define RCVDBDI_HWDIAG 0x000024c0
735
/* 0x24c4 --> 0x2800 unused */
737
/* Receive Data Completion Control */
738
#define RCVDCC_MODE 0x00002800
739
#define RCVDCC_MODE_RESET 0x00000001
740
#define RCVDCC_MODE_ENABLE 0x00000002
741
#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
742
/* 0x2804 --> 0x2c00 unused */
744
/* Receive BD Initiator Control Registers */
745
#define RCVBDI_MODE 0x00002c00
746
#define RCVBDI_MODE_RESET 0x00000001
747
#define RCVBDI_MODE_ENABLE 0x00000002
748
#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
749
#define RCVBDI_STATUS 0x00002c04
750
#define RCVBDI_STATUS_RCB_ATTN 0x00000004
751
#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
752
#define RCVBDI_STD_PROD_IDX 0x00002c0c
753
#define RCVBDI_MINI_PROD_IDX 0x00002c10
754
#define RCVBDI_MINI_THRESH 0x00002c14
755
#define RCVBDI_STD_THRESH 0x00002c18
756
#define RCVBDI_JUMBO_THRESH 0x00002c1c
757
/* 0x2c20 --> 0x3000 unused */
759
/* Receive BD Completion Control Registers */
760
#define RCVCC_MODE 0x00003000
761
#define RCVCC_MODE_RESET 0x00000001
762
#define RCVCC_MODE_ENABLE 0x00000002
763
#define RCVCC_MODE_ATTN_ENABLE 0x00000004
764
#define RCVCC_STATUS 0x00003004
765
#define RCVCC_STATUS_ERROR_ATTN 0x00000004
766
#define RCVCC_JUMP_PROD_IDX 0x00003008
767
#define RCVCC_STD_PROD_IDX 0x0000300c
768
#define RCVCC_MINI_PROD_IDX 0x00003010
769
/* 0x3014 --> 0x3400 unused */
771
/* Receive list selector control registers */
772
#define RCVLSC_MODE 0x00003400
773
#define RCVLSC_MODE_RESET 0x00000001
774
#define RCVLSC_MODE_ENABLE 0x00000002
775
#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
776
#define RCVLSC_STATUS 0x00003404
777
#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
778
/* 0x3408 --> 0x3800 unused */
780
/* Mbuf cluster free registers */
781
#define MBFREE_MODE 0x00003800
782
#define MBFREE_MODE_RESET 0x00000001
783
#define MBFREE_MODE_ENABLE 0x00000002
784
#define MBFREE_STATUS 0x00003804
785
/* 0x3808 --> 0x3c00 unused */
787
/* Host coalescing control registers */
788
#define HOSTCC_MODE 0x00003c00
789
#define HOSTCC_MODE_RESET 0x00000001
790
#define HOSTCC_MODE_ENABLE 0x00000002
791
#define HOSTCC_MODE_ATTN 0x00000004
792
#define HOSTCC_MODE_NOW 0x00000008
793
#define HOSTCC_MODE_FULL_STATUS 0x00000000
794
#define HOSTCC_MODE_64BYTE 0x00000080
795
#define HOSTCC_MODE_32BYTE 0x00000100
796
#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
797
#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
798
#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
799
#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
800
#define HOSTCC_STATUS 0x00003c04
801
#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
802
#define HOSTCC_RXCOL_TICKS 0x00003c08
803
#define LOW_RXCOL_TICKS 0x00000032
804
#define DEFAULT_RXCOL_TICKS 0x00000048
805
#define HIGH_RXCOL_TICKS 0x00000096
806
#define HOSTCC_TXCOL_TICKS 0x00003c0c
807
#define LOW_TXCOL_TICKS 0x00000096
808
#define DEFAULT_TXCOL_TICKS 0x0000012c
809
#define HIGH_TXCOL_TICKS 0x00000145
810
#define HOSTCC_RXMAX_FRAMES 0x00003c10
811
#define LOW_RXMAX_FRAMES 0x00000005
812
#define DEFAULT_RXMAX_FRAMES 0x00000008
813
#define HIGH_RXMAX_FRAMES 0x00000012
814
#define HOSTCC_TXMAX_FRAMES 0x00003c14
815
#define LOW_TXMAX_FRAMES 0x00000035
816
#define DEFAULT_TXMAX_FRAMES 0x0000004b
817
#define HIGH_TXMAX_FRAMES 0x00000052
818
#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
819
#define DEFAULT_RXCOAL_TICK_INT 0x00000019
820
#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
821
#define DEFAULT_TXCOAL_TICK_INT 0x00000019
822
#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
823
#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
824
#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
825
#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
826
#define HOSTCC_STAT_COAL_TICKS 0x00003c28
827
#define DEFAULT_STAT_COAL_TICKS 0x000f4240
828
/* 0x3c2c --> 0x3c30 unused */
829
#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
830
#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
831
#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
832
#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
833
#define HOSTCC_FLOW_ATTN 0x00003c48
834
/* 0x3c4c --> 0x3c50 unused */
835
#define HOSTCC_JUMBO_CON_IDX 0x00003c50
836
#define HOSTCC_STD_CON_IDX 0x00003c54
837
#define HOSTCC_MINI_CON_IDX 0x00003c58
838
/* 0x3c5c --> 0x3c80 unused */
839
#define HOSTCC_RET_PROD_IDX_0 0x00003c80
840
#define HOSTCC_RET_PROD_IDX_1 0x00003c84
841
#define HOSTCC_RET_PROD_IDX_2 0x00003c88
842
#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
843
#define HOSTCC_RET_PROD_IDX_4 0x00003c90
844
#define HOSTCC_RET_PROD_IDX_5 0x00003c94
845
#define HOSTCC_RET_PROD_IDX_6 0x00003c98
846
#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
847
#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
848
#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
849
#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
850
#define HOSTCC_RET_PROD_IDX_11 0x00003cac
851
#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
852
#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
853
#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
854
#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
855
#define HOSTCC_SND_CON_IDX_0 0x00003cc0
856
#define HOSTCC_SND_CON_IDX_1 0x00003cc4
857
#define HOSTCC_SND_CON_IDX_2 0x00003cc8
858
#define HOSTCC_SND_CON_IDX_3 0x00003ccc
859
#define HOSTCC_SND_CON_IDX_4 0x00003cd0
860
#define HOSTCC_SND_CON_IDX_5 0x00003cd4
861
#define HOSTCC_SND_CON_IDX_6 0x00003cd8
862
#define HOSTCC_SND_CON_IDX_7 0x00003cdc
863
#define HOSTCC_SND_CON_IDX_8 0x00003ce0
864
#define HOSTCC_SND_CON_IDX_9 0x00003ce4
865
#define HOSTCC_SND_CON_IDX_10 0x00003ce8
866
#define HOSTCC_SND_CON_IDX_11 0x00003cec
867
#define HOSTCC_SND_CON_IDX_12 0x00003cf0
868
#define HOSTCC_SND_CON_IDX_13 0x00003cf4
869
#define HOSTCC_SND_CON_IDX_14 0x00003cf8
870
#define HOSTCC_SND_CON_IDX_15 0x00003cfc
871
/* 0x3d00 --> 0x4000 unused */
873
/* Memory arbiter control registers */
874
#define MEMARB_MODE 0x00004000
875
#define MEMARB_MODE_RESET 0x00000001
876
#define MEMARB_MODE_ENABLE 0x00000002
877
#define MEMARB_STATUS 0x00004004
878
#define MEMARB_TRAP_ADDR_LOW 0x00004008
879
#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
880
/* 0x4010 --> 0x4400 unused */
882
/* Buffer manager control registers */
883
#define BUFMGR_MODE 0x00004400
884
#define BUFMGR_MODE_RESET 0x00000001
885
#define BUFMGR_MODE_ENABLE 0x00000002
886
#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
887
#define BUFMGR_MODE_BM_TEST 0x00000008
888
#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
889
#define BUFMGR_STATUS 0x00004404
890
#define BUFMGR_STATUS_ERROR 0x00000004
891
#define BUFMGR_STATUS_MBLOW 0x00000010
892
#define BUFMGR_MB_POOL_ADDR 0x00004408
893
#define BUFMGR_MB_POOL_SIZE 0x0000440c
894
#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
895
#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
896
#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
897
#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
898
#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
899
#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
900
#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
901
#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
902
#define BUFMGR_MB_HIGH_WATER 0x00004418
903
#define DEFAULT_MB_HIGH_WATER 0x00000060
904
#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
905
#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
906
#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
907
#define BUFMGR_MB_ALLOC_BIT 0x10000000
908
#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
909
#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
910
#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
911
#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
912
#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
913
#define BUFMGR_DMA_LOW_WATER 0x00004434
914
#define DEFAULT_DMA_LOW_WATER 0x00000005
915
#define BUFMGR_DMA_HIGH_WATER 0x00004438
916
#define DEFAULT_DMA_HIGH_WATER 0x0000000a
917
#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
918
#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
919
#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
920
#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
921
#define BUFMGR_HWDIAG_0 0x0000444c
922
#define BUFMGR_HWDIAG_1 0x00004450
923
#define BUFMGR_HWDIAG_2 0x00004454
924
/* 0x4458 --> 0x4800 unused */
926
/* Read DMA control registers */
927
#define RDMAC_MODE 0x00004800
928
#define RDMAC_MODE_RESET 0x00000001
929
#define RDMAC_MODE_ENABLE 0x00000002
930
#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
931
#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
932
#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
933
#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
934
#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
935
#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
936
#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
937
#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
938
#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
939
#define RDMAC_MODE_SPLIT_RESET 0x00001000
940
#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
941
#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
942
#define RDMAC_STATUS 0x00004804
943
#define RDMAC_STATUS_TGTABORT 0x00000004
944
#define RDMAC_STATUS_MSTABORT 0x00000008
945
#define RDMAC_STATUS_PARITYERR 0x00000010
946
#define RDMAC_STATUS_ADDROFLOW 0x00000020
947
#define RDMAC_STATUS_FIFOOFLOW 0x00000040
948
#define RDMAC_STATUS_FIFOURUN 0x00000080
949
#define RDMAC_STATUS_FIFOOREAD 0x00000100
950
#define RDMAC_STATUS_LNGREAD 0x00000200
951
/* 0x4808 --> 0x4c00 unused */
953
/* Write DMA control registers */
954
#define WDMAC_MODE 0x00004c00
955
#define WDMAC_MODE_RESET 0x00000001
956
#define WDMAC_MODE_ENABLE 0x00000002
957
#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
958
#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
959
#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
960
#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
961
#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
962
#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
963
#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
964
#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
965
#define WDMAC_MODE_RX_ACCEL 0x00000400
966
#define WDMAC_STATUS 0x00004c04
967
#define WDMAC_STATUS_TGTABORT 0x00000004
968
#define WDMAC_STATUS_MSTABORT 0x00000008
969
#define WDMAC_STATUS_PARITYERR 0x00000010
970
#define WDMAC_STATUS_ADDROFLOW 0x00000020
971
#define WDMAC_STATUS_FIFOOFLOW 0x00000040
972
#define WDMAC_STATUS_FIFOURUN 0x00000080
973
#define WDMAC_STATUS_FIFOOREAD 0x00000100
974
#define WDMAC_STATUS_LNGREAD 0x00000200
975
/* 0x4c08 --> 0x5000 unused */
977
/* Per-cpu register offsets (arm9) */
978
#define CPU_MODE 0x00000000
979
#define CPU_MODE_RESET 0x00000001
980
#define CPU_MODE_HALT 0x00000400
981
#define CPU_STATE 0x00000004
982
#define CPU_EVTMASK 0x00000008
983
/* 0xc --> 0x1c reserved */
984
#define CPU_PC 0x0000001c
985
#define CPU_INSN 0x00000020
986
#define CPU_SPAD_UFLOW 0x00000024
987
#define CPU_WDOG_CLEAR 0x00000028
988
#define CPU_WDOG_VECTOR 0x0000002c
989
#define CPU_WDOG_PC 0x00000030
990
#define CPU_HW_BP 0x00000034
991
/* 0x38 --> 0x44 unused */
992
#define CPU_WDOG_SAVED_STATE 0x00000044
993
#define CPU_LAST_BRANCH_ADDR 0x00000048
994
#define CPU_SPAD_UFLOW_SET 0x0000004c
995
/* 0x50 --> 0x200 unused */
996
#define CPU_R0 0x00000200
997
#define CPU_R1 0x00000204
998
#define CPU_R2 0x00000208
999
#define CPU_R3 0x0000020c
1000
#define CPU_R4 0x00000210
1001
#define CPU_R5 0x00000214
1002
#define CPU_R6 0x00000218
1003
#define CPU_R7 0x0000021c
1004
#define CPU_R8 0x00000220
1005
#define CPU_R9 0x00000224
1006
#define CPU_R10 0x00000228
1007
#define CPU_R11 0x0000022c
1008
#define CPU_R12 0x00000230
1009
#define CPU_R13 0x00000234
1010
#define CPU_R14 0x00000238
1011
#define CPU_R15 0x0000023c
1012
#define CPU_R16 0x00000240
1013
#define CPU_R17 0x00000244
1014
#define CPU_R18 0x00000248
1015
#define CPU_R19 0x0000024c
1016
#define CPU_R20 0x00000250
1017
#define CPU_R21 0x00000254
1018
#define CPU_R22 0x00000258
1019
#define CPU_R23 0x0000025c
1020
#define CPU_R24 0x00000260
1021
#define CPU_R25 0x00000264
1022
#define CPU_R26 0x00000268
1023
#define CPU_R27 0x0000026c
1024
#define CPU_R28 0x00000270
1025
#define CPU_R29 0x00000274
1026
#define CPU_R30 0x00000278
1027
#define CPU_R31 0x0000027c
1028
/* 0x280 --> 0x400 unused */
1030
#define RX_CPU_BASE 0x00005000
1031
#define TX_CPU_BASE 0x00005400
1034
#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1035
#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1036
#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1037
#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1038
#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1039
#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1040
#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1041
#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1042
#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1043
#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1044
#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1045
#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1046
#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1047
#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1048
#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1049
#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1050
#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1051
#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1052
#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1053
#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1054
#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1055
#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1056
#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1057
#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1058
#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1059
#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1060
#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1061
#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1062
#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1063
#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1064
#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1065
#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1066
#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1067
#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1068
#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1069
#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1070
#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1071
#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1072
#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1073
#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1074
#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1075
#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1076
#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1077
#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1078
#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1079
#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1080
#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1081
#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1082
#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1083
#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1084
#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1085
#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1086
#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1087
#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1088
#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1089
#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1090
#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1091
#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1092
#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1093
#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1094
#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1095
#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1096
#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1097
#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1098
#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1099
#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1100
#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1101
#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1102
/* 0x5a10 --> 0x5c00 */
1104
/* Flow Through queues */
1105
#define FTQ_RESET 0x00005c00
1106
/* 0x5c04 --> 0x5c10 unused */
1107
#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1108
#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1109
#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1110
#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1111
#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1112
#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1113
#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1114
#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1115
#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1116
#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1117
#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1118
#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1119
#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1120
#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1121
#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1122
#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1123
#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1124
#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1125
#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1126
#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1127
#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1128
#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1129
#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1130
#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1131
#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1132
#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1133
#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1134
#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1135
#define FTQ_SWTYPE1_CTL 0x00005c80
1136
#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1137
#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1138
#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1139
#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1140
#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1141
#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1142
#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1143
#define FTQ_HOST_COAL_CTL 0x00005ca0
1144
#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1145
#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1146
#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1147
#define FTQ_MAC_TX_CTL 0x00005cb0
1148
#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1149
#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1150
#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1151
#define FTQ_MB_FREE_CTL 0x00005cc0
1152
#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1153
#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1154
#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1155
#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1156
#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1157
#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1158
#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1159
#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1160
#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1161
#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1162
#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1163
#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1164
#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1165
#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1166
#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1167
#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1168
#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1169
#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1170
#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1171
#define FTQ_SWTYPE2_CTL 0x00005d10
1172
#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1173
#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1174
#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1175
/* 0x5d20 --> 0x6000 unused */
1177
/* Message signaled interrupt registers */
1178
#define MSGINT_MODE 0x00006000
1179
#define MSGINT_MODE_RESET 0x00000001
1180
#define MSGINT_MODE_ENABLE 0x00000002
1181
#define MSGINT_STATUS 0x00006004
1182
#define MSGINT_FIFO 0x00006008
1183
/* 0x600c --> 0x6400 unused */
1185
/* DMA completion registers */
1186
#define DMAC_MODE 0x00006400
1187
#define DMAC_MODE_RESET 0x00000001
1188
#define DMAC_MODE_ENABLE 0x00000002
1189
/* 0x6404 --> 0x6800 unused */
1192
#define GRC_MODE 0x00006800
1193
#define GRC_MODE_UPD_ON_COAL 0x00000001
1194
#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1195
#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1196
#define GRC_MODE_BSWAP_DATA 0x00000010
1197
#define GRC_MODE_WSWAP_DATA 0x00000020
1198
#define GRC_MODE_SPLITHDR 0x00000100
1199
#define GRC_MODE_NOFRM_CRACKING 0x00000200
1200
#define GRC_MODE_INCL_CRC 0x00000400
1201
#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1202
#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1203
#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1204
#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1205
#define GRC_MODE_HOST_STACKUP 0x00010000
1206
#define GRC_MODE_HOST_SENDBDS 0x00020000
1207
#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1208
#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1209
#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1210
#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1211
#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1212
#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1213
#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1214
#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1215
#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1216
#define GRC_MISC_CFG 0x00006804
1217
#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1218
#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1219
#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1220
#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1221
#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1222
#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1223
#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1224
#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1225
#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1226
#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1227
#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1228
#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1229
#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1230
#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1231
#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1232
#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1233
#define GRC_LOCAL_CTRL 0x00006808
1234
#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1235
#define GRC_LCLCTRL_CLEARINT 0x00000002
1236
#define GRC_LCLCTRL_SETINT 0x00000004
1237
#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1238
#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1239
#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1240
#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1241
#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1242
#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1243
#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1244
#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1245
#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1246
#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1247
#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1248
#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1249
#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1250
#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1251
#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1252
#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1253
#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1254
#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1255
#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1256
#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1257
#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1258
#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1259
#define GRC_TIMER 0x0000680c
1260
#define GRC_RX_CPU_EVENT 0x00006810
1261
#define GRC_RX_TIMER_REF 0x00006814
1262
#define GRC_RX_CPU_SEM 0x00006818
1263
#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1264
#define GRC_TX_CPU_EVENT 0x00006820
1265
#define GRC_TX_TIMER_REF 0x00006824
1266
#define GRC_TX_CPU_SEM 0x00006828
1267
#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1268
#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1269
#define GRC_EEPROM_ADDR 0x00006838
1270
#define EEPROM_ADDR_WRITE 0x00000000
1271
#define EEPROM_ADDR_READ 0x80000000
1272
#define EEPROM_ADDR_COMPLETE 0x40000000
1273
#define EEPROM_ADDR_FSM_RESET 0x20000000
1274
#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1275
#define EEPROM_ADDR_DEVID_SHIFT 26
1276
#define EEPROM_ADDR_START 0x02000000
1277
#define EEPROM_ADDR_CLKPERD_SHIFT 16
1278
#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1279
#define EEPROM_ADDR_ADDR_SHIFT 0
1280
#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1281
#define EEPROM_CHIP_SIZE (64 * 1024)
1282
#define GRC_EEPROM_DATA 0x0000683c
1283
#define GRC_EEPROM_CTRL 0x00006840
1284
#define GRC_MDI_CTRL 0x00006844
1285
#define GRC_SEEPROM_DELAY 0x00006848
1286
/* 0x684c --> 0x6c00 unused */
1288
/* 0x6c00 --> 0x7000 unused */
1290
/* NVRAM Control registers */
1291
#define NVRAM_CMD 0x00007000
1292
#define NVRAM_CMD_RESET 0x00000001
1293
#define NVRAM_CMD_DONE 0x00000008
1294
#define NVRAM_CMD_GO 0x00000010
1295
#define NVRAM_CMD_WR 0x00000020
1296
#define NVRAM_CMD_RD 0x00000000
1297
#define NVRAM_CMD_ERASE 0x00000040
1298
#define NVRAM_CMD_FIRST 0x00000080
1299
#define NVRAM_CMD_LAST 0x00000100
1300
#define NVRAM_STAT 0x00007004
1301
#define NVRAM_WRDATA 0x00007008
1302
#define NVRAM_ADDR 0x0000700c
1303
#define NVRAM_ADDR_MSK 0x00ffffff
1304
#define NVRAM_RDDATA 0x00007010
1305
#define NVRAM_CFG1 0x00007014
1306
#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1307
#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1308
#define NVRAM_CFG1_PASS_THRU 0x00000004
1309
#define NVRAM_CFG1_BIT_BANG 0x00000008
1310
#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1311
#define NVRAM_CFG2 0x00007018
1312
#define NVRAM_CFG3 0x0000701c
1313
#define NVRAM_SWARB 0x00007020
1314
#define SWARB_REQ_SET0 0x00000001
1315
#define SWARB_REQ_SET1 0x00000002
1316
#define SWARB_REQ_SET2 0x00000004
1317
#define SWARB_REQ_SET3 0x00000008
1318
#define SWARB_REQ_CLR0 0x00000010
1319
#define SWARB_REQ_CLR1 0x00000020
1320
#define SWARB_REQ_CLR2 0x00000040
1321
#define SWARB_REQ_CLR3 0x00000080
1322
#define SWARB_GNT0 0x00000100
1323
#define SWARB_GNT1 0x00000200
1324
#define SWARB_GNT2 0x00000400
1325
#define SWARB_GNT3 0x00000800
1326
#define SWARB_REQ0 0x00001000
1327
#define SWARB_REQ1 0x00002000
1328
#define SWARB_REQ2 0x00004000
1329
#define SWARB_REQ3 0x00008000
1330
#define NVRAM_BUFFERED_PAGE_SIZE 264
1331
#define NVRAM_BUFFERED_PAGE_POS 9
1332
/* 0x7024 --> 0x7400 unused */
1334
/* 0x7400 --> 0x8000 unused */
1336
/* 32K Window into NIC internal memory */
1337
#define NIC_SRAM_WIN_BASE 0x00008000
1339
/* Offsets into first 32k of NIC internal memory. */
1340
#define NIC_SRAM_PAGE_ZERO 0x00000000
1341
#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1342
#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1343
#define NIC_SRAM_STATS_BLK 0x00000300
1344
#define NIC_SRAM_STATUS_BLK 0x00000b00
1346
#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1347
#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1348
#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1350
#define NIC_SRAM_DATA_SIG 0x00000b54
1351
#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1353
#define NIC_SRAM_DATA_CFG 0x00000b58
1354
#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1355
#define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000
1356
#define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004
1357
#define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004
1358
#define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008
1359
#define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008
1360
#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1361
#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1362
#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1363
#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1364
#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1365
#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1366
#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1367
#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1368
#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1370
#define NIC_SRAM_DATA_PHY_ID 0x00000b74
1371
#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1372
#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1374
#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1375
#define FWCMD_NICDRV_ALIVE 0x00000001
1376
#define FWCMD_NICDRV_PAUSE_FW 0x00000002
1377
#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1378
#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1379
#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1380
#define FWCMD_NICDRV_FIX_DMAW 0x00000006
1381
#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1382
#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1383
#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1384
#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1385
#define DRV_STATE_START 0x00000001
1386
#define DRV_STATE_UNLOAD 0x00000002
1387
#define DRV_STATE_WOL 0x00000003
1388
#define DRV_STATE_SUSPEND 0x00000004
1390
#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1392
#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1393
#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1395
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1397
#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1398
#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1399
#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1400
#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1401
#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1402
#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1403
#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1404
#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1405
#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1406
#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1408
/* Currently this is fixed. */
1409
#define PHY_ADDR 0x01
1411
/* Tigon3 specific PHY MII registers. */
1412
#define TG3_BMCR_SPEED1000 0x0040
1414
#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1415
#define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1416
#define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1417
#define MII_TG3_CTRL_AS_MASTER 0x0800
1418
#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1420
#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1421
#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1422
#define MII_TG3_EXT_CTRL_TBI 0x8000
1424
#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1425
#define MII_TG3_EXT_STAT_LPASS 0x0100
1427
#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1429
#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1431
#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1433
#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1434
#define MII_TG3_AUX_STAT_LPASS 0x0004
1435
#define MII_TG3_AUX_STAT_SPDMASK 0x0700
1436
#define MII_TG3_AUX_STAT_10HALF 0x0100
1437
#define MII_TG3_AUX_STAT_10FULL 0x0200
1438
#define MII_TG3_AUX_STAT_100HALF 0x0300
1439
#define MII_TG3_AUX_STAT_100_4 0x0400
1440
#define MII_TG3_AUX_STAT_100FULL 0x0500
1441
#define MII_TG3_AUX_STAT_1000HALF 0x0600
1442
#define MII_TG3_AUX_STAT_1000FULL 0x0700
1444
#define MII_TG3_ISTAT 0x1a /* IRQ status register */
1445
#define MII_TG3_IMASK 0x1b /* IRQ mask register */
1447
/* ISTAT/IMASK event bits */
1448
#define MII_TG3_INT_LINKCHG 0x0002
1449
#define MII_TG3_INT_SPEEDCHG 0x0004
1450
#define MII_TG3_INT_DUPLEXCHG 0x0008
1451
#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1453
/* XXX Add this to mii.h */
1454
#ifndef ADVERTISE_PAUSE
1455
#define ADVERTISE_PAUSE_CAP 0x0400
1457
#ifndef ADVERTISE_PAUSE_ASYM
1458
#define ADVERTISE_PAUSE_ASYM 0x0800
1461
#define LPA_PAUSE_CAP 0x0400
1463
#ifndef LPA_PAUSE_ASYM
1464
#define LPA_PAUSE_ASYM 0x0800
1467
/* There are two ways to manage the TX descriptors on the tigon3.
1468
* Either the descriptors are in host DMA'able memory, or they
1469
* exist only in the cards on-chip SRAM. All 16 send bds are under
1470
* the same mode, they may not be configured individually.
1472
* The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1474
* To use host memory TX descriptors:
1475
* 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1476
* Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1477
* 2) Allocate DMA'able memory.
1478
* 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1479
* a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1480
* obtained in step 2
1481
* b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1482
* c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1483
* of TX descriptors. Leave flags field clear.
1484
* 4) Access TX descriptors via host memory. The chip
1485
* will refetch into local SRAM as needed when producer
1486
* index mailboxes are updated.
1488
* To use on-chip TX descriptors:
1489
* 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1490
* Make sure GRC_MODE_HOST_SENDBDS is clear.
1491
* 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1492
* a) Set TG3_BDINFO_HOST_ADDR to zero.
1493
* b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1494
* c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1495
* 3) Access TX descriptors directly in on-chip SRAM
1496
* using normal {read,write}l(). (and not using
1497
* pointer dereferencing of ioremap()'d memory like
1498
* the broken Broadcom driver does)
1500
* Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1501
* TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1503
struct tg3_tx_buffer_desc {
1508
#define TXD_FLAG_TCPUDP_CSUM 0x0001
1509
#define TXD_FLAG_IP_CSUM 0x0002
1510
#define TXD_FLAG_END 0x0004
1511
#define TXD_FLAG_IP_FRAG 0x0008
1512
#define TXD_FLAG_IP_FRAG_END 0x0010
1513
#define TXD_FLAG_VLAN 0x0040
1514
#define TXD_FLAG_COAL_NOW 0x0080
1515
#define TXD_FLAG_CPU_PRE_DMA 0x0100
1516
#define TXD_FLAG_CPU_POST_DMA 0x0200
1517
#define TXD_FLAG_ADD_SRC_ADDR 0x1000
1518
#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1519
#define TXD_FLAG_NO_CRC 0x8000
1520
#define TXD_LEN_SHIFT 16
1523
#define TXD_VLAN_TAG_SHIFT 0
1524
#define TXD_MSS_SHIFT 16
1527
#define TXD_ADDR 0x00UL /* 64-bit */
1528
#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1529
#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1530
#define TXD_SIZE 0x10UL
1532
struct tg3_rx_buffer_desc {
1537
#define RXD_IDX_MASK 0xffff0000
1538
#define RXD_IDX_SHIFT 16
1539
#define RXD_LEN_MASK 0x0000ffff
1540
#define RXD_LEN_SHIFT 0
1543
#define RXD_TYPE_SHIFT 16
1544
#define RXD_FLAGS_SHIFT 0
1546
#define RXD_FLAG_END 0x0004
1547
#define RXD_FLAG_MINI 0x0800
1548
#define RXD_FLAG_JUMBO 0x0020
1549
#define RXD_FLAG_VLAN 0x0040
1550
#define RXD_FLAG_ERROR 0x0400
1551
#define RXD_FLAG_IP_CSUM 0x1000
1552
#define RXD_FLAG_TCPUDP_CSUM 0x2000
1553
#define RXD_FLAG_IS_TCP 0x4000
1556
#define RXD_IPCSUM_MASK 0xffff0000
1557
#define RXD_IPCSUM_SHIFT 16
1558
#define RXD_TCPCSUM_MASK 0x0000ffff
1559
#define RXD_TCPCSUM_SHIFT 0
1563
#define RXD_VLAN_MASK 0x0000ffff
1565
#define RXD_ERR_BAD_CRC 0x00010000
1566
#define RXD_ERR_COLLISION 0x00020000
1567
#define RXD_ERR_LINK_LOST 0x00040000
1568
#define RXD_ERR_PHY_DECODE 0x00080000
1569
#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1570
#define RXD_ERR_MAC_ABRT 0x00200000
1571
#define RXD_ERR_TOO_SMALL 0x00400000
1572
#define RXD_ERR_NO_RESOURCES 0x00800000
1573
#define RXD_ERR_HUGE_FRAME 0x01000000
1574
#define RXD_ERR_MASK 0xffff0000
1578
#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1579
#define RXD_OPAQUE_INDEX_SHIFT 0
1580
#define RXD_OPAQUE_RING_STD 0x00010000
1581
#define RXD_OPAQUE_RING_JUMBO 0x00020000
1582
#define RXD_OPAQUE_RING_MINI 0x00040000
1583
#define RXD_OPAQUE_RING_MASK 0x00070000
1586
struct tg3_ext_rx_buffer_desc {
1593
struct tg3_rx_buffer_desc std;
1596
/* We only use this when testing out the DMA engine
1597
* at probe time. This is the internal format of buffer
1598
* descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1600
struct tg3_internal_buffer_desc {
1618
#define TG3_HW_STATUS_SIZE 0x50
1619
struct tg3_hw_status {
1621
#define SD_STATUS_UPDATED 0x00000001
1622
#define SD_STATUS_LINK_CHG 0x00000002
1623
#define SD_STATUS_ERROR 0x00000004
1629
u16 rx_jumbo_consumer;
1631
u16 rx_jumbo_consumer;
1637
u16 rx_mini_consumer;
1639
u16 rx_mini_consumer;
1657
struct tg3_hw_stats {
1658
u8 __reserved0[0x400-0x300];
1660
/* Statistics maintained by Receive MAC. */
1661
tg3_stat64_t rx_octets;
1663
tg3_stat64_t rx_fragments;
1664
tg3_stat64_t rx_ucast_packets;
1665
tg3_stat64_t rx_mcast_packets;
1666
tg3_stat64_t rx_bcast_packets;
1667
tg3_stat64_t rx_fcs_errors;
1668
tg3_stat64_t rx_align_errors;
1669
tg3_stat64_t rx_xon_pause_rcvd;
1670
tg3_stat64_t rx_xoff_pause_rcvd;
1671
tg3_stat64_t rx_mac_ctrl_rcvd;
1672
tg3_stat64_t rx_xoff_entered;
1673
tg3_stat64_t rx_frame_too_long_errors;
1674
tg3_stat64_t rx_jabbers;
1675
tg3_stat64_t rx_undersize_packets;
1676
tg3_stat64_t rx_in_length_errors;
1677
tg3_stat64_t rx_out_length_errors;
1678
tg3_stat64_t rx_64_or_less_octet_packets;
1679
tg3_stat64_t rx_65_to_127_octet_packets;
1680
tg3_stat64_t rx_128_to_255_octet_packets;
1681
tg3_stat64_t rx_256_to_511_octet_packets;
1682
tg3_stat64_t rx_512_to_1023_octet_packets;
1683
tg3_stat64_t rx_1024_to_1522_octet_packets;
1684
tg3_stat64_t rx_1523_to_2047_octet_packets;
1685
tg3_stat64_t rx_2048_to_4095_octet_packets;
1686
tg3_stat64_t rx_4096_to_8191_octet_packets;
1687
tg3_stat64_t rx_8192_to_9022_octet_packets;
1691
/* Statistics maintained by Transmit MAC. */
1692
tg3_stat64_t tx_octets;
1694
tg3_stat64_t tx_collisions;
1695
tg3_stat64_t tx_xon_sent;
1696
tg3_stat64_t tx_xoff_sent;
1697
tg3_stat64_t tx_flow_control;
1698
tg3_stat64_t tx_mac_errors;
1699
tg3_stat64_t tx_single_collisions;
1700
tg3_stat64_t tx_mult_collisions;
1701
tg3_stat64_t tx_deferred;
1703
tg3_stat64_t tx_excessive_collisions;
1704
tg3_stat64_t tx_late_collisions;
1705
tg3_stat64_t tx_collide_2times;
1706
tg3_stat64_t tx_collide_3times;
1707
tg3_stat64_t tx_collide_4times;
1708
tg3_stat64_t tx_collide_5times;
1709
tg3_stat64_t tx_collide_6times;
1710
tg3_stat64_t tx_collide_7times;
1711
tg3_stat64_t tx_collide_8times;
1712
tg3_stat64_t tx_collide_9times;
1713
tg3_stat64_t tx_collide_10times;
1714
tg3_stat64_t tx_collide_11times;
1715
tg3_stat64_t tx_collide_12times;
1716
tg3_stat64_t tx_collide_13times;
1717
tg3_stat64_t tx_collide_14times;
1718
tg3_stat64_t tx_collide_15times;
1719
tg3_stat64_t tx_ucast_packets;
1720
tg3_stat64_t tx_mcast_packets;
1721
tg3_stat64_t tx_bcast_packets;
1722
tg3_stat64_t tx_carrier_sense_errors;
1723
tg3_stat64_t tx_discards;
1724
tg3_stat64_t tx_errors;
1728
/* Statistics maintained by Receive List Placement. */
1729
tg3_stat64_t COS_rx_packets[16];
1730
tg3_stat64_t COS_rx_filter_dropped;
1731
tg3_stat64_t dma_writeq_full;
1732
tg3_stat64_t dma_write_prioq_full;
1733
tg3_stat64_t rxbds_empty;
1734
tg3_stat64_t rx_discards;
1735
tg3_stat64_t rx_errors;
1736
tg3_stat64_t rx_threshold_hit;
1740
/* Statistics maintained by Send Data Initiator. */
1741
tg3_stat64_t COS_out_packets[16];
1742
tg3_stat64_t dma_readq_full;
1743
tg3_stat64_t dma_read_prioq_full;
1744
tg3_stat64_t tx_comp_queue_full;
1746
/* Statistics maintained by Host Coalescing. */
1747
tg3_stat64_t ring_set_send_prod_index;
1748
tg3_stat64_t ring_status_update;
1749
tg3_stat64_t nic_irqs;
1750
tg3_stat64_t nic_avoided_irqs;
1751
tg3_stat64_t nic_tx_threshold_hit;
1753
u8 __reserved4[0xb00-0x9c0];
1758
led_mode_three_link,
1762
/* 'mapping' is superfluous as the chip does not write into
1763
* the tx/rx post rings so we could just fetch it from there.
1764
* But the cache behavior is better how we are doing it now.
1767
struct sk_buff *skb;
1768
DECLARE_PCI_UNMAP_ADDR(mapping)
1771
struct tx_ring_info {
1772
struct sk_buff *skb;
1773
DECLARE_PCI_UNMAP_ADDR(mapping)
1777
struct tg3_config_info {
1781
struct tg3_link_config {
1782
/* Describes what we're trying to get. */
1788
/* Describes what we actually have. */
1791
#define SPEED_INVALID 0xffff
1792
#define DUPLEX_INVALID 0xff
1793
#define AUTONEG_INVALID 0xff
1795
/* When we go in and out of low power mode we need
1796
* to swap with this state.
1798
int phy_is_low_power;
1804
struct tg3_bufmgr_config {
1805
u32 mbuf_read_dma_low_water;
1806
u32 mbuf_mac_rx_low_water;
1807
u32 mbuf_high_water;
1809
u32 mbuf_read_dma_low_water_jumbo;
1810
u32 mbuf_mac_rx_low_water_jumbo;
1811
u32 mbuf_high_water_jumbo;
1818
/* begin "general, frequently-used members" cacheline section */
1820
/* SMP locking strategy:
1822
* lock: Held during all operations except TX packet
1825
* tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
1827
* If you want to shut up all asynchronous processing you must
1828
* acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
1829
* be disabled to take 'lock' but only softirq disabling is
1830
* necessary for acquisition of 'tx_lock'.
1833
spinlock_t indirect_lock;
1836
struct net_device *dev;
1837
struct pci_dev *pdev;
1839
struct tg3_hw_status *hw_status;
1840
dma_addr_t status_mapping;
1844
/* begin "tx thread" cacheline section */
1851
/* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
1852
struct tg3_tx_buffer_desc *tx_ring;
1853
struct tx_ring_info *tx_buffers;
1854
dma_addr_t tx_desc_mapping;
1856
/* begin "rx thread" cacheline section */
1861
u32 rx_jumbo_pending;
1862
#if TG3_VLAN_TAG_USED
1863
struct vlan_group *vlgrp;
1866
struct tg3_rx_buffer_desc *rx_std;
1867
struct ring_info *rx_std_buffers;
1868
dma_addr_t rx_std_mapping;
1870
struct tg3_rx_buffer_desc *rx_jumbo;
1871
struct ring_info *rx_jumbo_buffers;
1872
dma_addr_t rx_jumbo_mapping;
1874
struct tg3_rx_buffer_desc *rx_rcb;
1875
dma_addr_t rx_rcb_mapping;
1877
/* begin "everything else" cacheline(s) section */
1878
struct net_device_stats net_stats;
1879
struct net_device_stats net_stats_prev;
1880
unsigned long phy_crc_errors;
1884
#define TG3_FLAG_HOST_TXDS 0x00000001
1885
#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
1886
#define TG3_FLAG_RX_CHECKSUMS 0x00000004
1887
#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
1888
#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
1889
#define TG3_FLAG_ENABLE_ASF 0x00000020
1890
#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
1891
#define TG3_FLAG_POLL_SERDES 0x00000080
1892
#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
1893
#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
1894
#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
1895
#define TG3_FLAG_WOL_ENABLE 0x00000800
1896
#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
1897
#define TG3_FLAG_NVRAM 0x00002000
1898
#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
1899
#define TG3_FLAG_RX_PAUSE 0x00008000
1900
#define TG3_FLAG_TX_PAUSE 0x00010000
1901
#define TG3_FLAG_PCIX_MODE 0x00020000
1902
#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
1903
#define TG3_FLAG_PCI_32BIT 0x00080000
1904
#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
1905
#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
1906
#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
1907
#define TG3_FLAG_JUMBO_ENABLE 0x00800000
1908
#define TG3_FLAG_10_100_ONLY 0x01000000
1909
#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
1910
#define TG3_FLAG_PAUSE_RX 0x04000000
1911
#define TG3_FLAG_PAUSE_TX 0x08000000
1912
#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
1913
#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
1914
#define TG3_FLAG_SPLIT_MODE 0x40000000
1915
#define TG3_FLAG_INIT_COMPLETE 0x80000000
1917
#define TG3_FLG2_RESTART_TIMER 0x00000001
1918
#define TG3_FLG2_SUN_5704 0x00000002
1919
#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
1920
#define TG3_FLG2_IS_5788 0x00000008
1921
#define TG3_FLG2_MAX_RXPEND_64 0x00000010
1922
#define TG3_FLG2_TSO_CAPABLE 0x00000020
1924
u32 split_mode_max_reqs;
1925
#define SPLIT_MODE_5704_MAX_REQ 3
1927
struct timer_list timer;
1929
u16 timer_multiplier;
1934
struct tg3_link_config link_config;
1935
struct tg3_bufmgr_config bufmgr_config;
1937
/* cache h/w values, often passed straight to h/w */
1949
u16 pci_chip_rev_id;
1950
u8 pci_cacheline_sz;
1954
u32 pci_cfg_state[64 / sizeof(u32)];
1960
#define PHY_ID_MASK 0xfffffff0
1961
#define PHY_ID_BCM5400 0x60008040
1962
#define PHY_ID_BCM5401 0x60008050
1963
#define PHY_ID_BCM5411 0x60008070
1964
#define PHY_ID_BCM5701 0x60008110
1965
#define PHY_ID_BCM5703 0x60008160
1966
#define PHY_ID_BCM5704 0x60008190
1967
#define PHY_ID_BCM5705 0x600081a0
1968
#define PHY_ID_BCM8002 0x60010140
1969
#define PHY_ID_SERDES 0xfeedbee0
1970
#define PHY_ID_INVALID 0xffffffff
1971
#define PHY_ID_REV_MASK 0x0000000f
1972
#define PHY_REV_BCM5401_B0 0x1
1973
#define PHY_REV_BCM5401_B2 0x3
1974
#define PHY_REV_BCM5401_C0 0x6
1975
#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
1977
enum phy_led_mode led_mode;
1979
char board_part_number[24];
1980
u32 nic_sram_data_cfg;
1982
struct pci_dev *pdev_peer;
1984
/* This macro assumes the passed PHY ID is already masked
1987
#define KNOWN_PHY_ID(X) \
1988
((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
1989
(X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
1990
(X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
1991
(X) == PHY_ID_BCM5705 || \
1992
(X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
1994
struct tg3_hw_stats *hw_stats;
1995
dma_addr_t stats_mapping;
1996
struct tq_struct reset_task;
1999
#endif /* !(_T3_H) */
added
removed
xen/drivers/net/tg3.h
