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/******************************************************************************
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* A Linux-style configuration list.
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#ifndef __X86_CONFIG_H__
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#define __X86_CONFIG_H__
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#if defined(__x86_64__)
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# define CONFIG_PAGING_LEVELS 4
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# define CONFIG_PAGING_LEVELS 3
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#define CONFIG_X86_HT 1
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#define CONFIG_PAGING_ASSISTANCE 1
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#define CONFIG_X86_LOCAL_APIC 1
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#define CONFIG_X86_GOOD_APIC 1
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#define CONFIG_X86_IO_APIC 1
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#define CONFIG_X86_PM_TIMER 1
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#define CONFIG_HPET_TIMER 1
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#define CONFIG_X86_MCE_THERMAL 1
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#define CONFIG_DISCONTIGMEM 1
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#define CONFIG_NUMA_EMU 1
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#define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER)
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/* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
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#define CONFIG_X86_L1_CACHE_SHIFT 7
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#define CONFIG_ACPI_BOOT 1
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#define CONFIG_ACPI_SLEEP 1
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#define CONFIG_ACPI_NUMA 1
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#define CONFIG_ACPI_SRAT 1
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#define CONFIG_ACPI_CSTATE 1
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#define CONFIG_HOTPLUG 1
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#define CONFIG_HOTPLUG_CPU 1
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#define OPT_CONSOLE_STR "vga"
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#define NR_CPUS MAX_PHYS_CPUS
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/* Maximum number of virtual CPUs in multi-processor guests. */
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#define MAX_VIRT_CPUS XEN_LEGACY_MAX_VCPUS
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/* Maximum we can support with current vLAPIC ID mapping. */
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#define MAX_HVM_VCPUS 128
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#ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
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# define supervisor_mode_kernel (1)
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# define supervisor_mode_kernel (0)
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#define __ALIGN .align 16,0x90
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#define __ALIGN_STR ".align 16,0x90"
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#define ALIGN_STR __ALIGN_STR
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#define NR_hypercalls 64
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#define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
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/* Primary stack is restricted to 8kB by guard pages. */
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#define PRIMARY_STACK_SIZE 8192
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#define BOOT_TRAMPOLINE 0x88000
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#define bootsym_phys(sym) \
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(((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
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#define bootsym(sym) \
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(*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
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BOOT_TRAMPOLINE-__pa(trampoline_start)))
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extern char trampoline_start[], trampoline_end[];
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extern char trampoline_realmode_entry[];
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extern unsigned int trampoline_xen_phys_start;
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extern unsigned char trampoline_cpu_started;
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extern char wakeup_start[];
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extern unsigned int video_mode, video_flags;
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#if defined(__x86_64__)
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#define CONFIG_X86_64 1
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#define CONFIG_COMPAT 1
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#define PML4_ENTRY_BITS 39
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#define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
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#define PML4_ADDR(_slot) \
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((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
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(_slot ## UL << PML4_ENTRY_BITS))
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#define GB(_gb) (_gb ## UL << 30)
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#define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
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#define PML4_ADDR(_slot) \
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(((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
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#define GB(_gb) (_gb << 30)
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* 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
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* Guest-defined use (see below for compatibility mode guests).
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* 0x0000800000000000 - 0xffff7fffffffffff [16EB]
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* Inaccessible: current arch only supports 48-bit sign-extended VAs.
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* 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
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* Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
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* 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
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* Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
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* 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
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* ioremap for PCI mmconfig space
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* 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
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* Guest linear page table.
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* 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
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* Shadow linear page table.
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* 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
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* Per-domain mappings (e.g., GDT, LDT).
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* 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261]
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* Machine-to-phys translation table.
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* 0xffff82c000000000 - 0xffff82c3ffffffff [16GB, 2^34 bytes, PML4:261]
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* ioremap()/fixmap area.
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* 0xffff82c400000000 - 0xffff82c43fffffff [1GB, 2^30 bytes, PML4:261]
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* Compatibility machine-to-phys translation table.
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* 0xffff82c440000000 - 0xffff82c47fffffff [1GB, 2^30 bytes, PML4:261]
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* High read-only compatibility machine-to-phys translation table.
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* 0xffff82c480000000 - 0xffff82c4bfffffff [1GB, 2^30 bytes, PML4:261]
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* Xen text, static data, bss.
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* 0xffff82c4c0000000 - 0xffff82f5ffffffff [197GB, PML4:261]
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* Reserved for future use.
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* 0xffff82f600000000 - 0xffff82ffffffffff [40GB, 2^38 bytes, PML4:261]
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* Page-frame information array.
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* 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271]
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* 1:1 direct mapping of all physical memory.
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* 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
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* Compatibility guest area layout:
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* 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
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* 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
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* Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
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* 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
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* 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
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* Hypercall argument translation area.
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* 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
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* Reserved for future use.
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#define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
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#define ROOT_PAGETABLE_LAST_XEN_SLOT 271
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#define ROOT_PAGETABLE_XEN_SLOTS \
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(ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
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/* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
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#define HYPERVISOR_VIRT_START (PML4_ADDR(256))
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#define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
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/* Slot 256: read-only guest-accessible machine-to-phys translation table. */
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#define RO_MPT_VIRT_START (PML4_ADDR(256))
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#define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2)
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#define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE)
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/* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB)
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* - full 16-bit segment support needs 44 bits
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* - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits)
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#define PCI_MCFG_VIRT_START (PML4_ADDR(257))
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#define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES)
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/* Slot 258: linear page table (guest table). */
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#define LINEAR_PT_VIRT_START (PML4_ADDR(258))
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#define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
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/* Slot 259: linear page table (shadow table). */
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#define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
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#define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
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/* Slot 260: per-domain mappings. */
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#define PERDOMAIN_VIRT_START (PML4_ADDR(260))
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#define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
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#define PERDOMAIN_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER))
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/* Slot 261: machine-to-phys conversion table (256GB). */
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#define RDWR_MPT_VIRT_START (PML4_ADDR(261))
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#define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE)
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/* Slot 261: ioremap()/fixmap area (16GB). */
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#define IOREMAP_VIRT_START RDWR_MPT_VIRT_END
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#define IOREMAP_VIRT_END (IOREMAP_VIRT_START + GB(16))
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/* Slot 261: compatibility machine-to-phys conversion table (1GB). */
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#define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
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#define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1))
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/* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
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#define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
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#define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + GB(1))
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/* Slot 261: xen text, static data and bss (1GB). */
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#define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
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#define XEN_VIRT_END (XEN_VIRT_START + GB(1))
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/* Slot 261: page-frame information array (40GB). */
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#define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START
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#define FRAMETABLE_SIZE ((DIRECTMAP_SIZE >> PAGE_SHIFT) * \
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sizeof(struct page_info))
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#define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
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/* Slot 262-271: A direct 1:1 mapping of all of physical memory. */
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#define DIRECTMAP_VIRT_START (PML4_ADDR(262))
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#define DIRECTMAP_SIZE (PML4_ENTRY_BYTES*10)
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#define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE)
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/* This is not a fixed value, just a lower limit. */
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#define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
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#define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
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#define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
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#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
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#define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
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((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
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#define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
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l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
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#define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
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#define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
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(COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
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#define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS
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#define PGT_base_page_table PGT_l4_page_table
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#define __HYPERVISOR_CS64 0xe008
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#define __HYPERVISOR_CS32 0xe038
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#define __HYPERVISOR_CS __HYPERVISOR_CS64
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#define __HYPERVISOR_DS64 0x0000
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#define __HYPERVISOR_DS32 0xe010
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#define __HYPERVISOR_DS __HYPERVISOR_DS64
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#define SYMBOLS_ORIGIN XEN_VIRT_START
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/* For generic assembly code: use macros to define operation/operand sizes. */
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#define __OS "q" /* Operation Suffix */
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#define __OP "r" /* Operand Prefix */
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#define __FIXUP_ALIGN ".align 8"
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#define __FIXUP_WORD ".quad"
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#elif defined(__i386__)
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#define CONFIG_X86_32 1
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#define CONFIG_DOMAIN_PAGE 1
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#define asmlinkage __attribute__((regparm(0)))
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* Memory layout (high to low): PAE-SIZE
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* I/O remapping area ( 4MB)
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* Direct-map (1:1) area [Xen code/data/heap] (12MB)
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* Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
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* Shadow linear pagetable ( 8MB)
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* Guest linear pagetable ( 8MB)
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* Machine-to-physical translation table [writable] (16MB)
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* Frame-info table (96MB)
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* * Start of guest inaccessible area
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* Machine-to-physical translation table [read-only] (16MB)
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* * Start of guest unmodifiable area
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#define IOREMAP_MBYTES 4
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#define DIRECTMAP_MBYTES 12
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#define MAPCACHE_MBYTES 4
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#define PERDOMAIN_MBYTES 8
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#define LINEARPT_MBYTES 8
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#define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
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#define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
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#define IOREMAP_VIRT_END 0UL
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#define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
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#define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
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#define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
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#define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
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#define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
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#define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
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#define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
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#define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
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#define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
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#define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
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#define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
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#define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
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#define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
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#define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
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#define FRAMETABLE_SIZE (FRAMETABLE_MBYTES<<20)
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#define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
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#define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
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#define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
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#define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
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/* Maximum linear address accessible via guest memory segments. */
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#define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
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/* Hypervisor owns top 168MB of virtual address space. */
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#define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
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#define L2_PAGETABLE_FIRST_XEN_SLOT \
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(HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
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#define L2_PAGETABLE_LAST_XEN_SLOT \
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(~0UL >> L2_PAGETABLE_SHIFT)
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#define L2_PAGETABLE_XEN_SLOTS \
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(L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
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#define PGT_base_page_table PGT_l3_page_table
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#define __HYPERVISOR_CS 0xe008
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#define __HYPERVISOR_DS 0xe010
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/* For generic assembly code: use macros to define operation/operand sizes. */
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#define __OS "l" /* Operation Suffix */
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#define __OP "e" /* Operand Prefix */
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#define __FIXUP_ALIGN ".align 4"
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#define __FIXUP_WORD ".long"
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#endif /* __i386__ */
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extern unsigned long xen_phys_start;
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#if defined(__i386__)
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extern unsigned long xenheap_phys_end;
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/* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
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#define GDT_LDT_VCPU_SHIFT 5
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#define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
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#define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
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#define GDT_LDT_MBYTES PERDOMAIN_MBYTES
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#define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT))
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#define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
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#define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
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/* The address of a particular VCPU's GDT or LDT. */
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#define GDT_VIRT_START(v) \
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(PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
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#define LDT_VIRT_START(v) \
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(GDT_VIRT_START(v) + (64*1024))
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#define PDPT_L1_ENTRIES \
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((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
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#define PDPT_L2_ENTRIES \
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((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
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#if defined(__x86_64__)
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#define ARCH_CRASH_SAVE_VMCOREINFO
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#endif /* __X86_CONFIG_H__ */