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#include <asm/debugger.h>
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#include <public/arch-ia64.h>
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#include <asm/config.h>
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* arch/ia64/kernel/ivt.S
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* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
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* Stephane Eranian <eranian@hpl.hp.com>
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* David Mosberger <davidm@hpl.hp.com>
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* Copyright (C) 2000, 2002-2003 Intel Co
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* Asit Mallick <asit.k.mallick@intel.com>
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* Suresh Siddha <suresh.b.siddha@intel.com>
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* Kenneth Chen <kenneth.w.chen@intel.com>
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* Fenghua Yu <fenghua.yu@intel.com>
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* 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
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* 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now
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* This file defines the interruption vector table used by the CPU.
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* It does not include one entry per possible cause of interruption.
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* The first 20 entries of the table contain 64 bundles each while the
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* remaining 48 entries contain only 16 bundles each.
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* The 64 bundles are used to allow inlining the whole handler for critical
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* interruptions like TLB misses.
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* For each entry, the comment is as follows:
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* // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
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* entry offset ----/ / / / /
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* entry number ---------/ / / /
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* size of the entry -------------/ / /
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* vector name -------------------------------------/ /
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* interruptions triggering this vector ----------------------/
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* The table is 32KB in size and must be aligned on 32KB boundary.
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* (The CPU ignores the 15 lower bits of the address)
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* Table is based upon EAS2.6 (Oct 1999)
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#include <linux/config.h>
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#include <asm/asmmacro.h>
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#include <asm/break.h>
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#include <asm/kregs.h>
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#include <asm/offsets.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#include <xen/errno.h>
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#include <linux/efi.h>
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# define PSR_DEFAULT_BITS psr.ac
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# define PSR_DEFAULT_BITS 0
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* This lets you track the last eight faults that occurred on the CPU.
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* Make sure ar.k2 isn't needed for something else before enabling this...
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# define DBG_FAULT(i) \
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#define MINSTATE_VIRT /* needed by minstate.h */
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mov r19=n; /* prepare to save predicates */ \
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br.sptk.many dispatch_to_fault_handler
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#define FAULT_OR_REFLECT(n) \
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mov r19=n; /* prepare to save predicates */ \
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extr.u r20=r20,IA64_PSR_CPL0_BIT,2;; \
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cmp.ne p6,p0=r0,r20; /* cpl != 0?*/ \
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(p6) br.dptk.many dispatch_reflection; \
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br.sptk.few dispatch_to_fault_handler
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.section .text.ivt,"ax"
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.align 32768 // align on 32KB boundary
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//////////////////////////////////////////////////////////////////////////
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// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
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//////////////////////////////////////////////////////////////////////////
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// 0x0400 Entry 1 (size 64 bundles) ITLB (21)
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/* If address belongs to VMM, go to alt tlb handler */
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cmp.eq p6,p0=0x1e,r17
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(p6) br.cond.spnt late_alt_itlb_miss
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br.cond.sptk fast_tlb_miss_reflect
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//////////////////////////////////////////////////////////////////////////
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// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
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mov r16=cr.ifa // get virtual address
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/* If address belongs to VMM, go to alt tlb handler */
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cmp.eq p6,p0=0x1e,r17
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(p6) br.cond.spnt late_alt_dtlb_miss
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br.cond.sptk fast_tlb_miss_reflect
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//////////////////////////////////////////////////////////////////////////
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// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
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mov r16=cr.ifa // get address that caused the TLB miss
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movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
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extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
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and r19=r19,r16 // clear ed, reserved bits, and PTE ctrl bits
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extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit
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cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
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or r19=r17,r19 // insert PTE control bits into r19
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dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN // clear the key
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dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area.
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mov cr.itir=r20 // set itir with cleared key
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(p8) br.cond.spnt page_fault
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itc.i r19 // insert the TLB entry
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//////////////////////////////////////////////////////////////////////////
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// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
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mov r16=cr.ifa // get address that caused the TLB miss
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mov r29=cr.ipsr // frametable_miss is shared by paravirtual and HVM sides
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// and it assumes ipsr is saved in r29. If change the
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// registers usage here, please check both sides!
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movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
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extr.u r23=r29,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
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and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
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tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
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extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit
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and r19=r19,r16 // clear ed, reserved bits, and
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tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
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(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
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(p8) br.cond.spnt page_fault
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#ifdef CONFIG_VIRTUAL_FRAME_TABLE
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shr r22=r16,56 // Test for the address of virtual frame_table
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cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
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(p8) br.cond.sptk frametable_miss ;;
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// !( (r22 == 0x18 && rr6 == XEN_EFI_RR6) ||
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// (r22 == 0x1c && rr7 == XEN_EFI_RR7) ||
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dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN // clear the key
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cmp.eq p8,p0=0x18,r22 // 0xc...
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cmp.eq p9,p0=0x1c,r22 // 0xe...
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cmp.eq.and p8,p0=r26,r24 // rr6 == XEN_EFI_RR6
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cmp.eq.and p9,p0=r25,r23 // rr7 == XEN_EFI_RR7
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cmp.eq.or p9,p0=0x1e,r22 // 0xf...
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(p8) br.cond.spnt alt_dtlb_miss_identity_map
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(p9) br.cond.spnt alt_dtlb_miss_identity_map
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br.cond.spnt page_fault
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alt_dtlb_miss_identity_map:
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dep r29=-1,r29,IA64_PSR_ED_BIT,1
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or r19=r19,r17 // insert PTE control bits into r19
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mov cr.itir=r20 // set itir with cleared key
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cmp.ne p8,p0=r0,r18 // Xen UC bit set
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cmp.eq.or p8,p0=0x18,r22 // Region 6 is UC for EFI
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(p8) dep r19=-1,r19,4,1 // set bit 4 (uncached) if access to UC area
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(p7) itc.d r19 // insert the TLB entry
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#ifdef CONFIG_VIRTUAL_FRAME_TABLE
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GLOBAL_ENTRY(frametable_miss)
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rsm psr.dt // switch to using physical data addressing
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movl r24=(frametable_pg_dir-PAGE_OFFSET) // r24=__pa(frametable_pg_dir)
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extr.u r17=r16,PGDIR_SHIFT,(PAGE_SHIFT-3)
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shladd r24=r17,3,r24 // r24=&pgd[pgd_offset(addr)]
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ld8 r24=[r24] // r24=pgd[pgd_offset(addr)]
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extr.u r18=r16,PMD_SHIFT,(PAGE_SHIFT-3) // r18=pmd_offset
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cmp.eq p6,p7=0,r24 // pgd present?
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shladd r24=r18,3,r24 // r24=&pmd[pmd_offset(addr)]
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(p7) ld8 r24=[r24] // r24=pmd[pmd_offset(addr)]
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extr.u r19=r16,PAGE_SHIFT,(PAGE_SHIFT-3)// r19=pte_offset
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(p6) br.spnt.few frametable_fault
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cmp.eq p6,p7=0,r24 // pmd present?
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shladd r24=r19,3,r24 // r24=&pte[pte_offset(addr)]
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(p7) ld8 r24=[r24] // r24=pte[pte_offset(addr)]
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mov r25=(PAGE_SHIFT<<IA64_ITIR_PS)
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(p6) br.spnt.few frametable_fault
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ssm psr.dt // switch to using virtual data addressing
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tbit.z p6,p7=r24,_PAGE_P_BIT // pte present?
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(p7) itc.d r24 // install updated PTE
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(p6) br.spnt.few frametable_fault // page present bit cleared?
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mov pr=r31,-1 // restore predicate registers
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ENTRY(frametable_fault) //ipsr saved in r29 before coming here!
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ssm psr.dt // switch to using virtual data addressing
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movl r19=ia64_frametable_probe
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cmp.eq p6,p7=r18,r19 // is faulting addrress ia64_frametable_probe?
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mov r8=0 // assumes that 'probe.r' uses r8
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dep r29=-1,r29,IA64_PSR_RI_BIT+1,1 // return to next instruction in
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mov r19=4 // FAULT(4)
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(p7) br.spnt.few dispatch_to_fault_handler
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END(frametable_fault)
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GLOBAL_ENTRY(ia64_frametable_probe)
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probe.r r8=r32,0 // destination register must be r8
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br.ret.sptk.many b0 // this instruction must be in bundle 2
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END(ia64_frametable_probe)
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#endif /* CONFIG_VIRTUAL_FRAME_TABLE */
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/////////////////////////////////////////////////////////////////////////////////////////
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// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
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ENTRY(nested_dtlb_miss)
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br.sptk.many b0 // return to the continuation point
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END(nested_dtlb_miss)
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GLOBAL_ENTRY(dispatch_reflection)
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* r19: intr type (offset into ivt, see ia64_int.h)
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* r31: contains saved predicates (pr)
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SAVE_MIN_WITH_COVER_R19
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alloc r14=ar.pfs,0,0,5,0
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ssm psr.ic | PSR_DEFAULT_BITS
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srlz.i // guarantee that interruption
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(p15) ssm psr.i // restore psr.i
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adds r3=8,r2 // set up second base pointer
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movl r14=ia64_leave_kernel
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// br.sptk.many ia64_prepare_handle_reflection // TODO: why commented out?
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br.call.sptk.many b6=ia64_handle_reflection
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END(dispatch_reflection)
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//////////////////////////////////////////////////////////////////////////
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// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
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//----------------------------------------------------------------
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// call do_page_fault (predicates are in r31, psr.dt may be off,
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// r16 is faulting address)
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GLOBAL_ENTRY(page_fault)
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alloc r15=ar.pfs,0,0,4,0
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adds r3=8,r2 // set up second base pointer
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ssm psr.ic | PSR_DEFAULT_BITS
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srlz.i // guarantee that interruption
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(p15) ssm psr.i // restore psr.i
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movl r14=ia64_leave_kernel
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adds out2=16,r12 // out2 = pointer to pt_regs
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br.call.sptk.many b6=ia64_do_page_fault // ignore return address
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//////////////////////////////////////////////////////////////////////////
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// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
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//////////////////////////////////////////////////////////////////////////
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// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
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extr.u r20=r20,IA64_PSR_CPL0_BIT,2
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mov r19=8 // prepare to save predicates
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cmp.eq p6,p0=r0,r20 // cpl == 0?
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(p6) br.sptk.few dispatch_to_fault_handler
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// If shadow mode is not enabled, reflect the fault.
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movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
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add r22=IA64_VCPU_SHADOW_BITMAP_OFFSET,r22
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cmp.eq p6,p0=r0,r22 // !shadow_bitmap ?
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(p6) br.dptk.many dispatch_reflection
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alloc r14=ar.pfs,0,0,4,0
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ssm psr.ic | PSR_DEFAULT_BITS
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srlz.i // guarantee that interruption
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(p15) ssm psr.i // restore psr.i
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adds r3=8,r2 // set up second base pointer
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movl r14=ia64_leave_kernel
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br.call.sptk.many b6=ia64_shadow_fault
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//////////////////////////////////////////////////////////////////////////
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// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
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br.sptk.many fast_access_reflect;;
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//////////////////////////////////////////////////////////////////////////
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// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
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extr.u r18=r18,IA64_PSR_CPL0_BIT,2
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cmp.ne p6,p0=r0,r18 /* cpl != 0? */
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(p6) br.sptk.many fast_access_reflect
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/* __domain_get_bundle() may cause this fault. */
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br.sptk.few dispatch_to_fault_handler
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//////////////////////////////////////////////////////////////////////////
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// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
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* The streamlined system call entry/exit paths only save/restore
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* the initial part of pt_regs. This implies that the callers of
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* system-calls must adhere to the normal procedure calling
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* Registers to be saved & restored:
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* CR registers: cr.ipsr, cr.iip, cr.ifs
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* AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore,
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* others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
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* Registers to be restored only:
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* r8-r11: output value from the system call.
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* During system call exit, scratch registers (including r15) are
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* modified/cleared to prevent leaking bits from kernel to user
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(p7) br.spnt.few dispatch_break_fault
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// A panic can occur before domain0 is created. In such cases,
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// referencing XSI_PSR_IC causes nested_dtlb_miss.
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movl r18=CDB_BREAK_NUM
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(p7) br.spnt.few dispatch_break_fault
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movl r18=THIS_CPU(current_psr_ic_addr)
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#ifdef CONFIG_PRIVIFY
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// pseudo-cover are replaced by break.b which (unfortunatly) always
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(p7) br.spnt.many dispatch_privop_fault
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// if (ipsr.cpl == CONFIG_CPL0_EMUL &&
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// (iim - HYPERPRIVOP_START) < HYPERPRIVOP_MAX)
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// this is a hyperprivop. A hyperprivop is hand-coded assembly with
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// psr.ic off which means it can make no calls, cannot use r1-r15,
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// and it can have no memory accesses unless they are to pinned
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mov r20=HYPERPRIVOP_START
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mov r21=HYPERPRIVOP_MAX
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extr.u r19=r19,IA64_PSR_CPL0_BIT,2 // extract cpl field from cr.ipsr
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cmp.gtu p7,p0=r21,r20
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cmp.eq.and p7,p0=CONFIG_CPL0_EMUL,r19 // ipsr.cpl==CONFIG_CPL0_EMUL
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(p7) br.sptk.many fast_hyperprivop
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movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
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adds r23=IA64_VCPU_BREAKIMM_OFFSET,r22
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cmp4.eq p6,p0=r23,r17;; // Xen-reserved breakimm?
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cmp.eq.and p6,p0=CONFIG_CPL0_EMUL,r19
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(p6) br.spnt.many fast_hypercall
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br.sptk.many fast_break_reflect
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(p7) br.spnt.few dispatch_break_fault
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* The streamlined system call entry/exit paths only save/restore the initial part
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* of pt_regs. This implies that the callers of system-calls must adhere to the
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* normal procedure calling conventions.
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* Registers to be saved & restored:
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* CR registers: cr.ipsr, cr.iip, cr.ifs
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* AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
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* others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
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* Registers to be restored only:
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* r8-r11: output value from the system call.
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* During system call exit, scratch registers (including r15) are modified/cleared
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* to prevent leaking bits from kernel to user level.
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// mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
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mov r29=cr.ipsr // M2 (12 cyc)
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// mov r31=pr // I0 (2 cyc)
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// mov r17=cr.iim // M2 (2 cyc)
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mov.m r27=ar.rsc // M2 (12 cyc)
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// mov r18=__IA64_BREAK_SYSCALL // A
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mov.m r21=ar.fpsr // M2 (12 cyc)
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mov r19=b6 // I0 (2 cyc)
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mov.m r23=ar.bspstore // M2 (12 cyc)
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mov.m r24=ar.rnat // M2 (5 cyc)
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mov.i r26=ar.pfs // I0 (2 cyc)
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mov r20=r1 // A save r1
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// movl r30=sys_call_table // X
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movl r30=ia64_hypercall_table // X
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mov r28=cr.iip // M2 (2 cyc)
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// cmp.eq p0,p7=r18,r17 // I0 is this a system call?
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//(p7) br.cond.spnt non_syscall // B no ->
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// From this point on, we are definitely on the syscall-path
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// and we can use (non-banked) scratch registers.
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///////////////////////////////////////////////////////////////////////
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mov r1=r16 // A move task-pointer to "addl"-addressable reg
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mov r2=r16 // A setup r2 for ia64_syscall_setup
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// add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
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// adds r15=-1024,r15 // A subtract 1024 from syscall number
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// mov r3=NR_syscalls - 1
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mov r3=NR_hypercalls - 1
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ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
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// ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
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mov r9=r0 // force flags = 0
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extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
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shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
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addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
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cmp.leu p6,p7=r15,r3 // A syscall number in range?
651
lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
652
(p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
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tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
655
mov.m ar.bspstore=r22 // M2 switch to kernel RBS
656
cmp.eq p8,p9=2,r8 // A isr.ei==2?
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(p8) mov r8=0 // A clear ei to 0
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//(p7) movl r30=sys_ni_syscall // X
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(p7) movl r30=do_ni_hypercall // X
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(p8) adds r28=16,r28 // A switch cr.iip to next bundle
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(p9) adds r8=1,r8 // A increment ei to next slot
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mov.m r25=ar.unat // M2 (5 cyc)
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dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
670
// adds r15=1024,r15 // A restore original syscall number
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// If any of the above loads miss in L1D, we'll stall here until
675
///////////////////////////////////////////////////////////////////////
676
st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
677
mov b6=r30 // I0 setup syscall handler branch reg early
678
cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
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// and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
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mov r18=ar.bsp // M2 (12 cyc)
683
(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
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// cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
685
br.call.sptk.many b7=ia64_syscall_setup // B
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mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
689
bsw.1 // B (6 cyc) regs are saved, switch to bank 1
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PT_REGS_UNWIND_INFO(-48)
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ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
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// movl r3=ia64_ret_from_syscall // X
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srlz.i // M0 ensure interruption collection is on
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// mov rp=r3 // I0 set the real return addr
699
//(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
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(p15) ssm psr.i // M2 restore psr.i
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//(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
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// br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
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br.call.sptk.many b0=b6 // B invoke syscall-handker (ignore return addr)
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// br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
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adds r2=PT(R8)+16,r12
710
br.call.sptk.many b0=do_softirq
712
//restore hypercall argument if continuation
713
adds r2=IA64_VCPU_HYPERCALL_CONTINUATION_OFS,r13
721
(p6) adds r2=PT(R16)+16,r12
722
(p6) adds r3=PT(R17)+16,r12
732
//save ar.bsp before cover
734
add r2=PT(R14)+16,r12
745
adds r2=PT(CR_IFS)+16,r12
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ssm psr.ic | PSR_DEFAULT_BITS
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br.call.sptk.many b0=reflect_event
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adds r2=PT(R14)+16,r12
756
adds r3=PT(R8)+16,r12
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//r16 contains ar.bsp before cover
763
br.sptk.many ia64_ret_from_syscall
768
//////////////////////////////////////////////////////////////////////////
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// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
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mov r31=pr // prepare to save predicates
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mov r30=cr.ivr // pass cr.ivr as first arg
774
// FIXME: this is a hack... use cpuinfo.ksoftirqd because its
775
// not used anywhere else and we need a place to stash ivr and
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// there's no registers available unused by SAVE_MIN/REST
777
movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET
780
movl r28=slow_interrupt
786
br.cond.sptk.many fast_tick_reflect
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SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
791
ssm psr.ic | PSR_DEFAULT_BITS
793
adds r3=8,r2 // set up second base pointer for SAVE_REST
794
srlz.i // ensure everybody knows psr.ic is back on
798
alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
799
movl out0=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
801
add out1=16,sp // pass pointer to pt_regs as second arg
802
movl r14=ia64_leave_kernel
805
br.call.sptk.many b6=ia64_handle_irq
809
//////////////////////////////////////////////////////////////////////////
810
// 0x3400 Entry 13 (size 64 bundles) Reserved
814
// There is no particular reason for this code to be here, other
815
// than that there happens to be space here that would go unused
816
// otherwise. If this fault ever gets "unreserved", simply move
817
// the following code to a more suitable spot...
819
GLOBAL_ENTRY(dispatch_break_fault)
822
dispatch_break_fault_post_save:
823
alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
826
mov out2=cr.isr // FIXME: pity to make this slow access twice
827
mov out3=cr.iim // FIXME: pity to make this slow access twice
829
ssm psr.ic | PSR_DEFAULT_BITS
831
srlz.i // guarantee that interruption collection is on
833
(p15) ssm psr.i // restore psr.i
834
adds r3=8,r2 // set up second base pointer
837
movl r14=ia64_leave_kernel
840
br.call.sptk.many b6=ia64_handle_break
841
END(dispatch_break_fault)
844
//////////////////////////////////////////////////////////////////////////
845
// 0x3800 Entry 14 (size 64 bundles) Reserved
849
// this code segment is from 2.6.16.13
852
* There is no particular reason for this code to be here, other than that
853
* there happens to be space here that would go unused otherwise. If this
854
* fault ever gets "unreserved", simply moved the following code to a more
857
* ia64_syscall_setup() is a separate subroutine so that it can
858
* allocate stacked registers so it can safely demine any
859
* potential NaT values from the input registers.
862
* - executing on bank 0 or bank 1 register set (doesn't matter)
863
* - r1: stack pointer
864
* - r2: current task pointer
866
* - r11: original contents (saved ar.pfs to be saved)
867
* - r12: original contents (sp to be saved)
868
* - r13: original contents (tp to be saved)
869
* - r15: original contents (syscall # to be saved)
870
* - r18: saved bsp (after switching to kernel stack)
872
* - r20: saved r1 (gp)
873
* - r21: saved ar.fpsr
874
* - r22: kernel's register backing store base (krbs_base)
875
* - r23: saved ar.bspstore
876
* - r24: saved ar.rnat
877
* - r25: saved ar.unat
878
* - r26: saved ar.pfs
879
* - r27: saved ar.rsc
880
* - r28: saved cr.iip
881
* - r29: saved cr.ipsr
883
* - b0: original contents (to be saved)
885
* - p10: TRUE if syscall is invoked with more than 8 out
886
* registers or r15's Nat is true
888
* - r3: preserved (same as on entry)
889
* - r8: -EINVAL if p10 is true
890
* - r12: points to kernel stack
891
* - r13: points to current task
892
* - r14: preserved (same as on entry)
894
* - p15: TRUE if interrupts need to be re-enabled
895
* - ar.fpsr: set to kernel settings
896
* - b6: preserved (same as on entry)
898
GLOBAL_ENTRY(ia64_syscall_setup)
900
# error This code assumes that b6 is the first field in pt_regs.
902
st8 [r1]=r19 // save b6
903
add r16=PT(CR_IPSR),r1 // initialize first base pointer
904
add r17=PT(R11),r1 // initialize second base pointer
906
alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
907
st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
910
st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
912
(pKStk) mov r18=r0 // make sure r18 isn't NaT
915
st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
916
st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
917
mov r28=b0 // save b0 (2 cyc)
920
st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
921
dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
925
st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
926
extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
927
and r8=0x7f,r19 // A // get sof of ar.pfs
929
st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
930
tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
934
(pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
938
(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
939
(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
943
tnat.nz p12,p0=in4 // [I0]
946
(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
947
(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
948
shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
950
st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
951
st8 [r17]=r28,PT(R1)-PT(B0) // save b0
952
tnat.nz p13,p0=in5 // [I0]
954
st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
955
st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
959
.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
960
.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
963
st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
965
cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
968
(p9) tnat.nz p10,p0=r15
969
adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
971
st8.spill [r17]=r15 // save r15
975
mov r13=r2 // establish `current'
976
movl r1=__gp // establish kernel global pointer
978
st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
982
cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
983
movl r17=FPSR_DEFAULT
985
mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
988
END(ia64_syscall_setup)
992
//////////////////////////////////////////////////////////////////////////
993
// 0x3c00 Entry 15 (size 64 bundles) Reserved
999
//////////////////////////////////////////////////////////////////////////
1000
// 0x4000 Entry 16 (size 64 bundles) Reserved
1004
// There is no particular reason for this code to be here, other
1005
// than that there happens to be space here that would go unused
1006
// otherwise. If this fault ever gets "unreserved", simply move
1007
// the following code to a more suitable spot...
1009
ENTRY(dispatch_privop_fault)
1012
alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in
1016
mov out2=cr.isr // FIXME: pity to make this slow access twice
1019
ssm psr.ic | PSR_DEFAULT_BITS
1021
srlz.i // guarantee that interruption
1024
(p15) ssm psr.i // restore psr.i
1025
adds r3=8,r2 // set up second base pointer
1028
movl r14=ia64_leave_kernel
1031
br.call.sptk.many b6=ia64_handle_privop
1032
END(dispatch_privop_fault)
1035
.org ia64_ivt+0x4400
1036
//////////////////////////////////////////////////////////////////////////
1037
// 0x4400 Entry 17 (size 64 bundles) Reserved
1042
.org ia64_ivt+0x4800
1043
//////////////////////////////////////////////////////////////////////////
1044
// 0x4800 Entry 18 (size 64 bundles) Reserved
1049
.org ia64_ivt+0x4c00
1050
//////////////////////////////////////////////////////////////////////////
1051
// 0x4c00 Entry 19 (size 64 bundles) Reserved
1056
* There is no particular reason for this code to be here, other
1057
* than that there happens to be space here that would go unused
1058
* otherwise. If this fault ever gets "unreserved", simply move
1059
* the following code to a more suitable spot...
1062
GLOBAL_ENTRY(dispatch_to_fault_handler)
1066
* r19: fault vector number (e.g., 24 for General Exception)
1067
* r31: contains saved predicates (pr)
1069
SAVE_MIN_WITH_COVER_R19
1070
alloc r14=ar.pfs,0,0,5,0
1077
ssm psr.ic | PSR_DEFAULT_BITS
1079
srlz.i // guarantee that interruption
1082
(p15) ssm psr.i // restore psr.i
1083
adds r3=8,r2 // set up second base pointer for
1087
movl r14=ia64_leave_kernel
1090
br.call.sptk.many b6=ia64_fault
1091
END(dispatch_to_fault_handler)
1094
// --- End of long entries, Beginning of short entries
1097
.org ia64_ivt+0x5000
1098
//////////////////////////////////////////////////////////////////////////
1099
// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1100
ENTRY(page_not_present)
1102
FAULT_OR_REFLECT(20)
1103
END(page_not_present)
1105
.org ia64_ivt+0x5100
1106
//////////////////////////////////////////////////////////////////////////
1107
// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1108
ENTRY(key_permission)
1110
FAULT_OR_REFLECT(21)
1113
.org ia64_ivt+0x5200
1114
//////////////////////////////////////////////////////////////////////////
1115
// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1116
ENTRY(iaccess_rights)
1118
FAULT_OR_REFLECT(22)
1121
.org ia64_ivt+0x5300
1122
//////////////////////////////////////////////////////////////////////////
1123
// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1124
ENTRY(daccess_rights)
1131
br.sptk.many fast_access_reflect
1135
.org ia64_ivt+0x5400
1136
//////////////////////////////////////////////////////////////////////////
1137
// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1138
ENTRY(general_exception)
1143
cmp4.ge p6,p0=0x20,r16
1144
(p6) br.sptk.many dispatch_privop_fault
1146
FAULT_OR_REFLECT(24)
1147
END(general_exception)
1149
.org ia64_ivt+0x5500
1150
//////////////////////////////////////////////////////////////////////////
1151
// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1152
ENTRY(disabled_fp_reg)
1154
FAULT_OR_REFLECT(25)
1155
END(disabled_fp_reg)
1157
.org ia64_ivt+0x5600
1158
//////////////////////////////////////////////////////////////////////////
1159
// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1160
ENTRY(nat_consumption)
1162
FAULT_OR_REFLECT(26)
1163
END(nat_consumption)
1165
.org ia64_ivt+0x5700
1166
//////////////////////////////////////////////////////////////////////////
1167
// 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1168
ENTRY(speculation_vector)
1170
// this probably need not reflect...
1171
FAULT_OR_REFLECT(27)
1172
END(speculation_vector)
1174
.org ia64_ivt+0x5800
1175
//////////////////////////////////////////////////////////////////////////
1176
// 0x5800 Entry 28 (size 16 bundles) Reserved
1180
.org ia64_ivt+0x5900
1181
//////////////////////////////////////////////////////////////////////////
1182
// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1185
FAULT_OR_REFLECT(29)
1188
.org ia64_ivt+0x5a00
1189
//////////////////////////////////////////////////////////////////////////
1190
// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1191
ENTRY(unaligned_access)
1193
FAULT_OR_REFLECT(30)
1194
END(unaligned_access)
1196
.org ia64_ivt+0x5b00
1197
//////////////////////////////////////////////////////////////////////////
1198
// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1199
ENTRY(unsupported_data_reference)
1201
FAULT_OR_REFLECT(31)
1202
END(unsupported_data_reference)
1204
.org ia64_ivt+0x5c00
1205
//////////////////////////////////////////////////////////////////////////
1206
// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1207
ENTRY(floating_point_fault)
1209
FAULT_OR_REFLECT(32)
1210
END(floating_point_fault)
1212
.org ia64_ivt+0x5d00
1213
//////////////////////////////////////////////////////////////////////////
1214
// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1215
ENTRY(floating_point_trap)
1217
FAULT_OR_REFLECT(33)
1218
END(floating_point_trap)
1220
.org ia64_ivt+0x5e00
1221
//////////////////////////////////////////////////////////////////////////
1222
// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1223
ENTRY(lower_privilege_trap)
1225
FAULT_OR_REFLECT(34)
1226
END(lower_privilege_trap)
1228
.org ia64_ivt+0x5f00
1229
//////////////////////////////////////////////////////////////////////////
1230
// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1231
ENTRY(taken_branch_trap)
1233
FAULT_OR_REFLECT(35)
1234
END(taken_branch_trap)
1236
.org ia64_ivt+0x6000
1237
//////////////////////////////////////////////////////////////////////////
1238
// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1239
ENTRY(single_step_trap)
1241
FAULT_OR_REFLECT(36)
1242
END(single_step_trap)
1244
.org ia64_ivt+0x6100
1245
//////////////////////////////////////////////////////////////////////////
1246
// 0x6100 Entry 37 (size 16 bundles) Reserved
1250
.org ia64_ivt+0x6200
1251
//////////////////////////////////////////////////////////////////////////
1252
// 0x6200 Entry 38 (size 16 bundles) Reserved
1256
.org ia64_ivt+0x6300
1257
//////////////////////////////////////////////////////////////////////////
1258
// 0x6300 Entry 39 (size 16 bundles) Reserved
1262
.org ia64_ivt+0x6400
1263
//////////////////////////////////////////////////////////////////////////
1264
// 0x6400 Entry 40 (size 16 bundles) Reserved
1268
.org ia64_ivt+0x6500
1269
//////////////////////////////////////////////////////////////////////////
1270
// 0x6500 Entry 41 (size 16 bundles) Reserved
1274
.org ia64_ivt+0x6600
1275
//////////////////////////////////////////////////////////////////////////
1276
// 0x6600 Entry 42 (size 16 bundles) Reserved
1280
.org ia64_ivt+0x6700
1281
//////////////////////////////////////////////////////////////////////////
1282
// 0x6700 Entry 43 (size 16 bundles) Reserved
1286
.org ia64_ivt+0x6800
1287
//////////////////////////////////////////////////////////////////////////
1288
// 0x6800 Entry 44 (size 16 bundles) Reserved
1292
.org ia64_ivt+0x6900
1293
//////////////////////////////////////////////////////////////////////////
1294
// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,
1295
// 44,58,60,61,62,72,
1297
ENTRY(ia32_exception)
1299
FAULT_OR_REFLECT(45)
1302
.org ia64_ivt+0x6a00
1303
//////////////////////////////////////////////////////////////////////////
1304
// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1305
ENTRY(ia32_intercept)
1307
FAULT_OR_REFLECT(46)
1310
.org ia64_ivt+0x6b00
1311
//////////////////////////////////////////////////////////////////////////
1312
// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1313
ENTRY(ia32_interrupt)
1315
FAULT_OR_REFLECT(47)
1318
.org ia64_ivt+0x6c00
1319
//////////////////////////////////////////////////////////////////////////
1320
// 0x6c00 Entry 48 (size 16 bundles) Reserved
1324
.org ia64_ivt+0x6d00
1325
//////////////////////////////////////////////////////////////////////////
1326
// 0x6d00 Entry 49 (size 16 bundles) Reserved
1330
.org ia64_ivt+0x6e00
1331
//////////////////////////////////////////////////////////////////////////
1332
// 0x6e00 Entry 50 (size 16 bundles) Reserved
1336
.org ia64_ivt+0x6f00
1337
//////////////////////////////////////////////////////////////////////////
1338
// 0x6f00 Entry 51 (size 16 bundles) Reserved
1342
.org ia64_ivt+0x7000
1343
//////////////////////////////////////////////////////////////////////////
1344
// 0x7000 Entry 52 (size 16 bundles) Reserved
1348
.org ia64_ivt+0x7100
1349
//////////////////////////////////////////////////////////////////////////
1350
// 0x7100 Entry 53 (size 16 bundles) Reserved
1354
.org ia64_ivt+0x7200
1355
//////////////////////////////////////////////////////////////////////////
1356
// 0x7200 Entry 54 (size 16 bundles) Reserved
1360
.org ia64_ivt+0x7300
1361
//////////////////////////////////////////////////////////////////////////
1362
// 0x7300 Entry 55 (size 16 bundles) Reserved
1366
.org ia64_ivt+0x7400
1367
//////////////////////////////////////////////////////////////////////////
1368
// 0x7400 Entry 56 (size 16 bundles) Reserved
1372
.org ia64_ivt+0x7500
1373
//////////////////////////////////////////////////////////////////////////
1374
// 0x7500 Entry 57 (size 16 bundles) Reserved
1378
.org ia64_ivt+0x7600
1379
//////////////////////////////////////////////////////////////////////////
1380
// 0x7600 Entry 58 (size 16 bundles) Reserved
1384
.org ia64_ivt+0x7700
1385
//////////////////////////////////////////////////////////////////////////
1386
// 0x7700 Entry 59 (size 16 bundles) Reserved
1390
.org ia64_ivt+0x7800
1391
//////////////////////////////////////////////////////////////////////////
1392
// 0x7800 Entry 60 (size 16 bundles) Reserved
1396
.org ia64_ivt+0x7900
1397
//////////////////////////////////////////////////////////////////////////
1398
// 0x7900 Entry 61 (size 16 bundles) Reserved
1402
.org ia64_ivt+0x7a00
1403
//////////////////////////////////////////////////////////////////////////
1404
// 0x7a00 Entry 62 (size 16 bundles) Reserved
1408
.org ia64_ivt+0x7b00
1409
//////////////////////////////////////////////////////////////////////////
1410
// 0x7b00 Entry 63 (size 16 bundles) Reserved
1414
.org ia64_ivt+0x7c00
1415
//////////////////////////////////////////////////////////////////////////
1416
// 0x7c00 Entry 64 (size 16 bundles) Reserved
1420
.org ia64_ivt+0x7d00
1421
//////////////////////////////////////////////////////////////////////////
1422
// 0x7d00 Entry 65 (size 16 bundles) Reserved
1426
.org ia64_ivt+0x7e00
1427
//////////////////////////////////////////////////////////////////////////
1428
// 0x7e00 Entry 66 (size 16 bundles) Reserved
1432
.org ia64_ivt+0x7f00
1433
//////////////////////////////////////////////////////////////////////////
1434
// 0x7f00 Entry 67 (size 16 bundles) Reserved
1438
.org ia64_ivt+0x8000
added
removed
xen/arch/ia64/xen/ivt.S
