1
/*******************************************************************************
4
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
8
Software Foundation; either version 2 of the License, or (at your option)
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16
You should have received a copy of the GNU General Public License along with
17
this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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Linux NICS <linux.nics@intel.com>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
30
* Shared functions for accessing and configuring the MAC
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static int32_t e1000_set_phy_type(struct e1000_hw *hw);
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static void e1000_phy_init_script(struct e1000_hw *hw);
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static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
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static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
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static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
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static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
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static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
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static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
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static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
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static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
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static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
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static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
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static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
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uint16_t words, uint16_t *data);
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static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
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uint16_t offset, uint16_t words,
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static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
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static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
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static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
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static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
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static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
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static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
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static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
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static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
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static void e1000_release_eeprom(struct e1000_hw *hw);
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static void e1000_standby_eeprom(struct e1000_hw *hw);
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static int32_t e1000_id_led_init(struct e1000_hw * hw);
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static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
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/* IGP cable length table */
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uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
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{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
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25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
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40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
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60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
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90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
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100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
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110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
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/******************************************************************************
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* Set the phy type member in the hw struct.
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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e1000_set_phy_type(struct e1000_hw *hw)
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DEBUGFUNC("e1000_set_phy_type");
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case M88E1000_E_PHY_ID:
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case M88E1000_I_PHY_ID:
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case M88E1011_I_PHY_ID:
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hw->phy_type = e1000_phy_m88;
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case IGP01E1000_I_PHY_ID:
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hw->phy_type = e1000_phy_igp;
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/* Should never have loaded on this device */
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hw->phy_type = e1000_phy_undefined;
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return -E1000_ERR_PHY_TYPE;
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return E1000_SUCCESS;
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/******************************************************************************
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* IGP phy init script - initializes the GbE PHY
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
116
e1000_phy_init_script(struct e1000_hw *hw)
118
DEBUGFUNC("e1000_phy_init_script");
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if(hw->phy_init_script) {
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e1000_write_phy_reg(hw,0x0000,0x0140);
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if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
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e1000_write_phy_reg(hw, 0x1F95, 0x0001);
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e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
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e1000_write_phy_reg(hw, 0x1F79, 0x0018);
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e1000_write_phy_reg(hw, 0x1F30, 0x1600);
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e1000_write_phy_reg(hw, 0x1F31, 0x0014);
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e1000_write_phy_reg(hw, 0x1F32, 0x161C);
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e1000_write_phy_reg(hw, 0x1F94, 0x0003);
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e1000_write_phy_reg(hw, 0x1F96, 0x003F);
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e1000_write_phy_reg(hw, 0x2010, 0x0008);
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e1000_write_phy_reg(hw, 0x1F73, 0x0099);
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e1000_write_phy_reg(hw, 0x0000, 0x3300);
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if(hw->mac_type == e1000_82547) {
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uint16_t fused, fine, coarse;
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/* Move to analog registers page */
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e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
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if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
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e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
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fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
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coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
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if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
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coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
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fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
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} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
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fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
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fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
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(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
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(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
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e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
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e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
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IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
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/******************************************************************************
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* Set the mac type member in the hw struct.
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
188
e1000_set_mac_type(struct e1000_hw *hw)
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DEBUGFUNC("e1000_set_mac_type");
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switch (hw->device_id) {
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case E1000_DEV_ID_82542:
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switch (hw->revision_id) {
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case E1000_82542_2_0_REV_ID:
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hw->mac_type = e1000_82542_rev2_0;
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case E1000_82542_2_1_REV_ID:
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hw->mac_type = e1000_82542_rev2_1;
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/* Invalid 82542 revision ID */
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return -E1000_ERR_MAC_TYPE;
206
case E1000_DEV_ID_82543GC_FIBER:
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case E1000_DEV_ID_82543GC_COPPER:
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hw->mac_type = e1000_82543;
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case E1000_DEV_ID_82544EI_COPPER:
211
case E1000_DEV_ID_82544EI_FIBER:
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case E1000_DEV_ID_82544GC_COPPER:
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case E1000_DEV_ID_82544GC_LOM:
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hw->mac_type = e1000_82544;
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case E1000_DEV_ID_82540EM:
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case E1000_DEV_ID_82540EM_LOM:
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case E1000_DEV_ID_82540EP:
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case E1000_DEV_ID_82540EP_LOM:
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case E1000_DEV_ID_82540EP_LP:
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hw->mac_type = e1000_82540;
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case E1000_DEV_ID_82545EM_COPPER:
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case E1000_DEV_ID_82545EM_FIBER:
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hw->mac_type = e1000_82545;
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case E1000_DEV_ID_82545GM_COPPER:
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case E1000_DEV_ID_82545GM_FIBER:
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case E1000_DEV_ID_82545GM_SERDES:
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hw->mac_type = e1000_82545_rev_3;
232
case E1000_DEV_ID_82546EB_COPPER:
233
case E1000_DEV_ID_82546EB_FIBER:
234
case E1000_DEV_ID_82546EB_QUAD_COPPER:
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hw->mac_type = e1000_82546;
237
case E1000_DEV_ID_82546GB_COPPER:
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case E1000_DEV_ID_82546GB_FIBER:
239
case E1000_DEV_ID_82546GB_SERDES:
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hw->mac_type = e1000_82546_rev_3;
242
case E1000_DEV_ID_82541EI:
243
case E1000_DEV_ID_82541EI_MOBILE:
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hw->mac_type = e1000_82541;
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case E1000_DEV_ID_82541ER:
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case E1000_DEV_ID_82541GI:
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case E1000_DEV_ID_82541GI_MOBILE:
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hw->mac_type = e1000_82541_rev_2;
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case E1000_DEV_ID_82547EI:
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hw->mac_type = e1000_82547;
254
case E1000_DEV_ID_82547GI:
255
hw->mac_type = e1000_82547_rev_2;
258
/* Should never have loaded on this device */
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return -E1000_ERR_MAC_TYPE;
262
return E1000_SUCCESS;
265
/*****************************************************************************
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* Set media type and TBI compatibility.
268
* hw - Struct containing variables accessed by shared code
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* **************************************************************************/
271
e1000_set_media_type(struct e1000_hw *hw)
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DEBUGFUNC("e1000_set_media_type");
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if(hw->mac_type != e1000_82543) {
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/* tbi_compatibility is only valid on 82543 */
279
hw->tbi_compatibility_en = FALSE;
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switch (hw->device_id) {
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case E1000_DEV_ID_82545GM_SERDES:
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case E1000_DEV_ID_82546GB_SERDES:
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hw->media_type = e1000_media_type_internal_serdes;
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if(hw->mac_type >= e1000_82543) {
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status = E1000_READ_REG(hw, STATUS);
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if(status & E1000_STATUS_TBIMODE) {
291
hw->media_type = e1000_media_type_fiber;
292
/* tbi_compatibility not valid on fiber */
293
hw->tbi_compatibility_en = FALSE;
295
hw->media_type = e1000_media_type_copper;
298
/* This is an 82542 (fiber only) */
299
hw->media_type = e1000_media_type_fiber;
304
/******************************************************************************
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* Reset the transmit and receive units; mask and clear all interrupts.
307
* hw - Struct containing variables accessed by shared code
308
*****************************************************************************/
310
e1000_reset_hw(struct e1000_hw *hw)
318
DEBUGFUNC("e1000_reset_hw");
320
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
321
if(hw->mac_type == e1000_82542_rev2_0) {
322
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
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e1000_pci_clear_mwi(hw);
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/* Clear interrupt mask to stop board from generating interrupts */
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DEBUGOUT("Masking off all interrupts\n");
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E1000_WRITE_REG(hw, IMC, 0xffffffff);
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/* Disable the Transmit and Receive units. Then delay to allow
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* any pending transactions to complete before we hit the MAC with
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E1000_WRITE_REG(hw, RCTL, 0);
335
E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
336
E1000_WRITE_FLUSH(hw);
338
/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
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hw->tbi_compatibility_on = FALSE;
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/* Delay to allow any outstanding PCI transactions to complete before
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* resetting the device
346
ctrl = E1000_READ_REG(hw, CTRL);
348
/* Must reset the PHY before resetting the MAC */
349
if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
350
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
354
/* Issue a global reset to the MAC. This will reset the chip's
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* transmit, receive, DMA, and link units. It will not effect
356
* the current PCI configuration. The global reset bit is self-
357
* clearing, and should clear within a microsecond.
359
DEBUGOUT("Issuing a global reset to MAC\n");
361
switch(hw->mac_type) {
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case e1000_82541_rev_2:
368
/* These controllers can't ack the 64-bit write when issuing the
369
* reset, so use IO-mapping as a workaround to issue the reset */
370
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
372
case e1000_82545_rev_3:
373
case e1000_82546_rev_3:
374
/* Reset is performed on a shadow of the control register */
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E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
378
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
382
/* After MAC reset, force reload of EEPROM to restore power-on settings to
383
* device. Later controllers reload the EEPROM automatically, so just wait
384
* for reload to complete.
386
switch(hw->mac_type) {
387
case e1000_82542_rev2_0:
388
case e1000_82542_rev2_1:
391
/* Wait for reset to complete */
393
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
394
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
395
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
396
E1000_WRITE_FLUSH(hw);
397
/* Wait for EEPROM reload */
401
case e1000_82541_rev_2:
403
case e1000_82547_rev_2:
404
/* Wait for EEPROM reload */
408
/* Wait for EEPROM reload (it happens automatically) */
413
/* Disable HW ARPs on ASF enabled adapters */
414
if(hw->mac_type >= e1000_82540) {
415
manc = E1000_READ_REG(hw, MANC);
416
manc &= ~(E1000_MANC_ARP_EN);
417
E1000_WRITE_REG(hw, MANC, manc);
420
if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
421
e1000_phy_init_script(hw);
423
/* Configure activity LED after PHY reset */
424
led_ctrl = E1000_READ_REG(hw, LEDCTL);
425
led_ctrl &= IGP_ACTIVITY_LED_MASK;
426
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
427
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
430
/* Clear interrupt mask to stop board from generating interrupts */
431
DEBUGOUT("Masking off all interrupts\n");
432
E1000_WRITE_REG(hw, IMC, 0xffffffff);
434
/* Clear any pending interrupt events. */
435
icr = E1000_READ_REG(hw, ICR);
437
/* If MWI was previously enabled, reenable it. */
438
if(hw->mac_type == e1000_82542_rev2_0) {
439
if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
440
e1000_pci_set_mwi(hw);
443
return E1000_SUCCESS;
446
/******************************************************************************
447
* Performs basic configuration of the adapter.
449
* hw - Struct containing variables accessed by shared code
451
* Assumes that the controller has previously been reset and is in a
452
* post-reset uninitialized state. Initializes the receive address registers,
453
* multicast table, and VLAN filter table. Calls routines to setup link
454
* configuration and flow control settings. Clears all on-chip counters. Leaves
455
* the transmit and receive units disabled and uninitialized.
456
*****************************************************************************/
458
e1000_init_hw(struct e1000_hw *hw)
463
uint16_t pcix_cmd_word;
464
uint16_t pcix_stat_hi_word;
468
DEBUGFUNC("e1000_init_hw");
470
/* Initialize Identification LED */
471
if((ret_val = e1000_id_led_init(hw))) {
472
DEBUGOUT("Error Initializing Identification LED\n");
476
/* Set the media type and TBI compatibility */
477
e1000_set_media_type(hw);
479
/* Disabling VLAN filtering. */
480
DEBUGOUT("Initializing the IEEE VLAN\n");
481
E1000_WRITE_REG(hw, VET, 0);
483
e1000_clear_vfta(hw);
485
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
486
if(hw->mac_type == e1000_82542_rev2_0) {
487
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
488
e1000_pci_clear_mwi(hw);
489
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
490
E1000_WRITE_FLUSH(hw);
494
/* Setup the receive address. This involves initializing all of the Receive
495
* Address Registers (RARs 0 - 15).
497
e1000_init_rx_addrs(hw);
499
/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
500
if(hw->mac_type == e1000_82542_rev2_0) {
501
E1000_WRITE_REG(hw, RCTL, 0);
502
E1000_WRITE_FLUSH(hw);
504
if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
505
e1000_pci_set_mwi(hw);
508
/* Zero out the Multicast HASH table */
509
DEBUGOUT("Zeroing the MTA\n");
510
for(i = 0; i < E1000_MC_TBL_SIZE; i++)
511
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
513
/* Set the PCI priority bit correctly in the CTRL register. This
514
* determines if the adapter gives priority to receives, or if it
515
* gives equal priority to transmits and receives.
517
if(hw->dma_fairness) {
518
ctrl = E1000_READ_REG(hw, CTRL);
519
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
522
switch(hw->mac_type) {
523
case e1000_82545_rev_3:
524
case e1000_82546_rev_3:
527
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
528
if(hw->bus_type == e1000_bus_type_pcix) {
529
e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
530
e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
532
cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
533
PCIX_COMMAND_MMRBC_SHIFT;
534
stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
535
PCIX_STATUS_HI_MMRBC_SHIFT;
536
if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
537
stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
538
if(cmd_mmrbc > stat_mmrbc) {
539
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
540
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
541
e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
548
/* Call a subroutine to configure the link and setup flow control. */
549
ret_val = e1000_setup_link(hw);
551
/* Set the transmit descriptor write-back policy */
552
if(hw->mac_type > e1000_82544) {
553
ctrl = E1000_READ_REG(hw, TXDCTL);
554
ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
555
E1000_WRITE_REG(hw, TXDCTL, ctrl);
558
/* Clear all of the statistics registers (clear on read). It is
559
* important that we do this after we have tried to establish link
560
* because the symbol error count will increment wildly if there
563
e1000_clear_hw_cntrs(hw);
568
/******************************************************************************
569
* Adjust SERDES output amplitude based on EEPROM setting.
571
* hw - Struct containing variables accessed by shared code.
572
*****************************************************************************/
574
e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
576
uint16_t eeprom_data;
579
DEBUGFUNC("e1000_adjust_serdes_amplitude");
581
if(hw->media_type != e1000_media_type_internal_serdes)
582
return E1000_SUCCESS;
584
switch(hw->mac_type) {
585
case e1000_82545_rev_3:
586
case e1000_82546_rev_3:
589
return E1000_SUCCESS;
592
if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
597
if(eeprom_data != EEPROM_RESERVED_WORD) {
598
/* Adjust SERDES output amplitude only. */
599
eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
600
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
605
return E1000_SUCCESS;
608
/******************************************************************************
609
* Configures flow control and link settings.
611
* hw - Struct containing variables accessed by shared code
613
* Determines which flow control settings to use. Calls the apropriate media-
614
* specific link configuration function. Configures the flow control settings.
615
* Assuming the adapter has a valid link partner, a valid link should be
616
* established. Assumes the hardware has previously been reset and the
617
* transmitter and receiver are not enabled.
618
*****************************************************************************/
620
e1000_setup_link(struct e1000_hw *hw)
624
uint16_t eeprom_data;
626
DEBUGFUNC("e1000_setup_link");
628
/* Read and store word 0x0F of the EEPROM. This word contains bits
629
* that determine the hardware's default PAUSE (flow control) mode,
630
* a bit that determines whether the HW defaults to enabling or
631
* disabling auto-negotiation, and the direction of the
632
* SW defined pins. If there is no SW over-ride of the flow
633
* control setting, then the variable hw->fc will
634
* be initialized based on a value in the EEPROM.
636
if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
637
DEBUGOUT("EEPROM Read Error\n");
638
return -E1000_ERR_EEPROM;
641
if(hw->fc == e1000_fc_default) {
642
if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
643
hw->fc = e1000_fc_none;
644
else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
645
EEPROM_WORD0F_ASM_DIR)
646
hw->fc = e1000_fc_tx_pause;
648
hw->fc = e1000_fc_full;
651
/* We want to save off the original Flow Control configuration just
652
* in case we get disconnected and then reconnected into a different
653
* hub or switch with different Flow Control capabilities.
655
if(hw->mac_type == e1000_82542_rev2_0)
656
hw->fc &= (~e1000_fc_tx_pause);
658
if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
659
hw->fc &= (~e1000_fc_rx_pause);
661
hw->original_fc = hw->fc;
663
DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
665
/* Take the 4 bits from EEPROM word 0x0F that determine the initial
666
* polarity value for the SW controlled pins, and setup the
667
* Extended Device Control reg with that info.
668
* This is needed because one of the SW controlled pins is used for
669
* signal detection. So this should be done before e1000_setup_pcs_link()
670
* or e1000_phy_setup() is called.
672
if(hw->mac_type == e1000_82543) {
673
ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
675
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
678
/* Call the necessary subroutine to configure the link. */
679
ret_val = (hw->media_type == e1000_media_type_copper) ?
680
e1000_setup_copper_link(hw) :
681
e1000_setup_fiber_serdes_link(hw);
683
/* Initialize the flow control address, type, and PAUSE timer
684
* registers to their default values. This is done even if flow
685
* control is disabled, because it does not hurt anything to
686
* initialize these registers.
688
DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
690
E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
691
E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
692
E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
693
E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
695
/* Set the flow control receive threshold registers. Normally,
696
* these registers will be set to a default threshold that may be
697
* adjusted later by the driver's runtime code. However, if the
698
* ability to transmit pause frames in not enabled, then these
699
* registers will be set to 0.
701
if(!(hw->fc & e1000_fc_tx_pause)) {
702
E1000_WRITE_REG(hw, FCRTL, 0);
703
E1000_WRITE_REG(hw, FCRTH, 0);
705
/* We need to set up the Receive Threshold high and low water marks
706
* as well as (optionally) enabling the transmission of XON frames.
708
if(hw->fc_send_xon) {
709
E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
710
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
712
E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
713
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
719
/******************************************************************************
720
* Sets up link for a fiber based or serdes based adapter
722
* hw - Struct containing variables accessed by shared code
724
* Manipulates Physical Coding Sublayer functions in order to configure
725
* link. Assumes the hardware has been previously reset and the transmitter
726
* and receiver are not enabled.
727
*****************************************************************************/
729
e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
738
DEBUGFUNC("e1000_setup_fiber_serdes_link");
740
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
741
* set when the optics detect a signal. On older adapters, it will be
742
* cleared when there is a signal. This applies to fiber media only.
743
* If we're on serdes media, adjust the output amplitude to value set in
746
ctrl = E1000_READ_REG(hw, CTRL);
747
if(hw->media_type == e1000_media_type_fiber)
748
signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
750
if((ret_val = e1000_adjust_serdes_amplitude(hw)))
753
/* Take the link out of reset */
754
ctrl &= ~(E1000_CTRL_LRST);
756
/* Adjust VCO speed to improve BER performance */
757
if((ret_val = e1000_set_vco_speed(hw)))
760
e1000_config_collision_dist(hw);
762
/* Check for a software override of the flow control settings, and setup
763
* the device accordingly. If auto-negotiation is enabled, then software
764
* will have to set the "PAUSE" bits to the correct value in the Tranmsit
765
* Config Word Register (TXCW) and re-start auto-negotiation. However, if
766
* auto-negotiation is disabled, then software will have to manually
767
* configure the two flow control enable bits in the CTRL register.
769
* The possible values of the "fc" parameter are:
770
* 0: Flow control is completely disabled
771
* 1: Rx flow control is enabled (we can receive pause frames, but
772
* not send pause frames).
773
* 2: Tx flow control is enabled (we can send pause frames but we do
774
* not support receiving pause frames).
775
* 3: Both Rx and TX flow control (symmetric) are enabled.
779
/* Flow control is completely disabled by a software over-ride. */
780
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
782
case e1000_fc_rx_pause:
783
/* RX Flow control is enabled and TX Flow control is disabled by a
784
* software over-ride. Since there really isn't a way to advertise
785
* that we are capable of RX Pause ONLY, we will advertise that we
786
* support both symmetric and asymmetric RX PAUSE. Later, we will
787
* disable the adapter's ability to send PAUSE frames.
789
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
791
case e1000_fc_tx_pause:
792
/* TX Flow control is enabled, and RX Flow control is disabled, by a
793
* software over-ride.
795
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
798
/* Flow control (both RX and TX) is enabled by a software over-ride. */
799
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
802
DEBUGOUT("Flow control param set incorrectly\n");
803
return -E1000_ERR_CONFIG;
807
/* Since auto-negotiation is enabled, take the link out of reset (the link
808
* will be in reset, because we previously reset the chip). This will
809
* restart auto-negotiation. If auto-neogtiation is successful then the
810
* link-up status bit will be set and the flow control enable bits (RFCE
811
* and TFCE) will be set according to their negotiated value.
813
DEBUGOUT("Auto-negotiation enabled\n");
815
E1000_WRITE_REG(hw, TXCW, txcw);
816
E1000_WRITE_REG(hw, CTRL, ctrl);
817
E1000_WRITE_FLUSH(hw);
822
/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
823
* indication in the Device Status Register. Time-out if a link isn't
824
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
825
* less than 500 milliseconds even if the other end is doing it in SW).
826
* For internal serdes, we just assume a signal is present, then poll.
828
if(hw->media_type == e1000_media_type_internal_serdes ||
829
(E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
830
DEBUGOUT("Looking for Link\n");
831
for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
833
status = E1000_READ_REG(hw, STATUS);
834
if(status & E1000_STATUS_LU) break;
836
if(i == (LINK_UP_TIMEOUT / 10)) {
837
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
838
hw->autoneg_failed = 1;
839
if(hw->media_type == e1000_media_type_fiber) {
840
/* AutoNeg failed to achieve a link, so we'll call
841
* e1000_check_for_link. This routine will force the link up if
842
* we detect a signal. This will allow us to communicate with
843
* non-autonegotiating link partners.
845
if((ret_val = e1000_check_for_link(hw))) {
846
DEBUGOUT("Error while checking for link\n");
849
hw->autoneg_failed = 0;
852
hw->autoneg_failed = 0;
853
DEBUGOUT("Valid Link Found\n");
856
DEBUGOUT("No Signal Detected\n");
858
return E1000_SUCCESS;
861
/******************************************************************************
862
* Detects which PHY is present and the speed and duplex
864
* hw - Struct containing variables accessed by shared code
865
******************************************************************************/
867
e1000_setup_copper_link(struct e1000_hw *hw)
875
DEBUGFUNC("e1000_setup_copper_link");
877
ctrl = E1000_READ_REG(hw, CTRL);
878
/* With 82543, we need to force speed and duplex on the MAC equal to what
879
* the PHY speed and duplex configuration is. In addition, we need to
880
* perform a hardware reset on the PHY to take it out of reset.
882
if(hw->mac_type > e1000_82543) {
883
ctrl |= E1000_CTRL_SLU;
884
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
885
E1000_WRITE_REG(hw, CTRL, ctrl);
887
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
888
E1000_WRITE_REG(hw, CTRL, ctrl);
889
e1000_phy_hw_reset(hw);
892
/* Make sure we have a valid PHY */
893
if((ret_val = e1000_detect_gig_phy(hw))) {
894
DEBUGOUT("Error, did not detect valid phy.\n");
897
DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
899
if(hw->mac_type <= e1000_82543 ||
900
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
901
hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
902
hw->phy_reset_disable = FALSE;
904
if(!hw->phy_reset_disable) {
905
if (hw->phy_type == e1000_phy_igp) {
907
if((ret_val = e1000_phy_reset(hw))) {
908
DEBUGOUT("Error Resetting the PHY\n");
912
/* Wait 10ms for MAC to configure PHY from eeprom settings */
915
/* Configure activity LED after PHY reset */
916
led_ctrl = E1000_READ_REG(hw, LEDCTL);
917
led_ctrl &= IGP_ACTIVITY_LED_MASK;
918
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
919
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
921
/* disable lplu d3 during driver init */
922
if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
923
DEBUGOUT("Error Disabling LPLU D3\n");
927
/* Configure mdi-mdix settings */
928
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
932
if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
933
hw->dsp_config_state = e1000_dsp_config_disabled;
934
/* Force MDI for IGP B-0 PHY */
935
phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
936
IGP01E1000_PSCR_FORCE_MDI_MDIX);
940
hw->dsp_config_state = e1000_dsp_config_enabled;
941
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
945
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
948
phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
952
phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
956
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
960
/* set auto-master slave resolution settings */
962
e1000_ms_type phy_ms_setting = hw->master_slave;
964
if(hw->ffe_config_state == e1000_ffe_config_active)
965
hw->ffe_config_state = e1000_ffe_config_enabled;
967
if(hw->dsp_config_state == e1000_dsp_config_activated)
968
hw->dsp_config_state = e1000_dsp_config_enabled;
970
/* when autonegotiation advertisment is only 1000Mbps then we
971
* should disable SmartSpeed and enable Auto MasterSlave
972
* resolution as hardware default. */
973
if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
974
/* Disable SmartSpeed */
975
if((ret_val = e1000_read_phy_reg(hw,
976
IGP01E1000_PHY_PORT_CONFIG,
979
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
980
if((ret_val = e1000_write_phy_reg(hw,
981
IGP01E1000_PHY_PORT_CONFIG,
984
/* Set auto Master/Slave resolution process */
985
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
988
phy_data &= ~CR_1000T_MS_ENABLE;
989
if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
994
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
998
/* load defaults for future use */
999
hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1000
((phy_data & CR_1000T_MS_VALUE) ?
1001
e1000_ms_force_master :
1002
e1000_ms_force_slave) :
1005
switch (phy_ms_setting) {
1006
case e1000_ms_force_master:
1007
phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1009
case e1000_ms_force_slave:
1010
phy_data |= CR_1000T_MS_ENABLE;
1011
phy_data &= ~(CR_1000T_MS_VALUE);
1014
phy_data &= ~CR_1000T_MS_ENABLE;
1018
if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1023
/* Enable CRS on TX. This must be set for half-duplex operation. */
1024
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1028
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1031
* MDI/MDI-X = 0 (default)
1032
* 0 - Auto for all speeds
1035
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1037
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1041
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1044
phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1047
phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1051
phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1056
* disable_polarity_correction = 0 (default)
1057
* Automatic Correction for Reversed Cable Polarity
1061
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1062
if(hw->disable_polarity_correction == 1)
1063
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1064
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1068
/* Force TX_CLK in the Extended PHY Specific Control Register
1071
if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1075
phy_data |= M88E1000_EPSCR_TX_CLK_25;
1077
if (hw->phy_revision < M88E1011_I_REV_4) {
1078
/* Configure Master and Slave downshift values */
1079
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1080
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1081
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1082
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1083
if((ret_val = e1000_write_phy_reg(hw,
1084
M88E1000_EXT_PHY_SPEC_CTRL,
1089
/* SW Reset the PHY so all changes take effect */
1090
if((ret_val = e1000_phy_reset(hw))) {
1091
DEBUGOUT("Error Resetting the PHY\n");
1097
* autoneg = 1 (default)
1098
* PHY will advertise value(s) parsed from
1099
* autoneg_advertised and fc
1101
* PHY will be set to 10H, 10F, 100H, or 100F
1102
* depending on value parsed from forced_speed_duplex.
1105
/* Is autoneg enabled? This is enabled by default or by software
1106
* override. If so, call e1000_phy_setup_autoneg routine to parse the
1107
* autoneg_advertised and fc options. If autoneg is NOT enabled, then
1108
* the user should have provided a speed/duplex override. If so, then
1109
* call e1000_phy_force_speed_duplex to parse and set this up.
1112
/* Perform some bounds checking on the hw->autoneg_advertised
1113
* parameter. If this variable is zero, then set it to the default.
1115
hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1117
/* If autoneg_advertised is zero, we assume it was not defaulted
1118
* by the calling code so we set to advertise full capability.
1120
if(hw->autoneg_advertised == 0)
1121
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1123
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1124
if((ret_val = e1000_phy_setup_autoneg(hw))) {
1125
DEBUGOUT("Error Setting up Auto-Negotiation\n");
1128
DEBUGOUT("Restarting Auto-Neg\n");
1130
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
1131
* the Auto Neg Restart bit in the PHY control register.
1133
if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1136
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1137
if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1140
/* Does the user want to wait for Auto-Neg to complete here, or
1141
* check at a later time (for example, callback routine).
1143
if(hw->wait_autoneg_complete) {
1144
if((ret_val = e1000_wait_autoneg(hw))) {
1145
DEBUGOUT("Error while waiting for autoneg to complete\n");
1149
hw->get_link_status = TRUE;
1151
DEBUGOUT("Forcing speed and duplex\n");
1152
if((ret_val = e1000_phy_force_speed_duplex(hw))) {
1153
DEBUGOUT("Error Forcing Speed and Duplex\n");
1157
} /* !hw->phy_reset_disable */
1159
/* Check link status. Wait up to 100 microseconds for link to become
1162
for(i = 0; i < 10; i++) {
1163
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1165
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1168
if(phy_data & MII_SR_LINK_STATUS) {
1169
/* We have link, so we need to finish the config process:
1170
* 1) Set up the MAC to the current PHY speed/duplex
1171
* if we are on 82543. If we
1172
* are on newer silicon, we only need to configure
1173
* collision distance in the Transmit Control Register.
1174
* 2) Set up flow control on the MAC to that established with
1177
if(hw->mac_type >= e1000_82544) {
1178
e1000_config_collision_dist(hw);
1180
if((ret_val = e1000_config_mac_to_phy(hw))) {
1181
DEBUGOUT("Error configuring MAC to PHY settings\n");
1185
if((ret_val = e1000_config_fc_after_link_up(hw))) {
1186
DEBUGOUT("Error Configuring Flow Control\n");
1189
DEBUGOUT("Valid link established!!!\n");
1191
if(hw->phy_type == e1000_phy_igp) {
1192
if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1193
DEBUGOUT("Error Configuring DSP after link up\n");
1197
DEBUGOUT("Valid link established!!!\n");
1198
return E1000_SUCCESS;
1203
DEBUGOUT("Unable to establish link!!!\n");
1204
return E1000_SUCCESS;
1207
/******************************************************************************
1208
* Configures PHY autoneg and flow control advertisement settings
1210
* hw - Struct containing variables accessed by shared code
1211
******************************************************************************/
1213
e1000_phy_setup_autoneg(struct e1000_hw *hw)
1216
uint16_t mii_autoneg_adv_reg;
1217
uint16_t mii_1000t_ctrl_reg;
1219
DEBUGFUNC("e1000_phy_setup_autoneg");
1221
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
1222
if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1223
&mii_autoneg_adv_reg)))
1226
/* Read the MII 1000Base-T Control Register (Address 9). */
1227
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1230
/* Need to parse both autoneg_advertised and fc and set up
1231
* the appropriate PHY registers. First we will parse for
1232
* autoneg_advertised software override. Since we can advertise
1233
* a plethora of combinations, we need to check each bit
1237
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
1238
* Advertisement Register (Address 4) and the 1000 mb speed bits in
1239
* the 1000Base-T Control Register (Address 9).
1241
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1242
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1244
DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1246
/* Do we want to advertise 10 Mb Half Duplex? */
1247
if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1248
DEBUGOUT("Advertise 10mb Half duplex\n");
1249
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1252
/* Do we want to advertise 10 Mb Full Duplex? */
1253
if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1254
DEBUGOUT("Advertise 10mb Full duplex\n");
1255
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1258
/* Do we want to advertise 100 Mb Half Duplex? */
1259
if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1260
DEBUGOUT("Advertise 100mb Half duplex\n");
1261
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1264
/* Do we want to advertise 100 Mb Full Duplex? */
1265
if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1266
DEBUGOUT("Advertise 100mb Full duplex\n");
1267
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1270
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1271
if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1272
DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1275
/* Do we want to advertise 1000 Mb Full Duplex? */
1276
if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1277
DEBUGOUT("Advertise 1000mb Full duplex\n");
1278
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1281
/* Check for a software override of the flow control settings, and
1282
* setup the PHY advertisement registers accordingly. If
1283
* auto-negotiation is enabled, then software will have to set the
1284
* "PAUSE" bits to the correct value in the Auto-Negotiation
1285
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1287
* The possible values of the "fc" parameter are:
1288
* 0: Flow control is completely disabled
1289
* 1: Rx flow control is enabled (we can receive pause frames
1290
* but not send pause frames).
1291
* 2: Tx flow control is enabled (we can send pause frames
1292
* but we do not support receiving pause frames).
1293
* 3: Both Rx and TX flow control (symmetric) are enabled.
1294
* other: No software override. The flow control configuration
1295
* in the EEPROM is used.
1298
case e1000_fc_none: /* 0 */
1299
/* Flow control (RX & TX) is completely disabled by a
1300
* software over-ride.
1302
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1304
case e1000_fc_rx_pause: /* 1 */
1305
/* RX Flow control is enabled, and TX Flow control is
1306
* disabled, by a software over-ride.
1308
/* Since there really isn't a way to advertise that we are
1309
* capable of RX Pause ONLY, we will advertise that we
1310
* support both symmetric and asymmetric RX PAUSE. Later
1311
* (in e1000_config_fc_after_link_up) we will disable the
1312
*hw's ability to send PAUSE frames.
1314
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1316
case e1000_fc_tx_pause: /* 2 */
1317
/* TX Flow control is enabled, and RX Flow control is
1318
* disabled, by a software over-ride.
1320
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1321
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1323
case e1000_fc_full: /* 3 */
1324
/* Flow control (both RX and TX) is enabled by a software
1327
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1330
DEBUGOUT("Flow control param set incorrectly\n");
1331
return -E1000_ERR_CONFIG;
1334
if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
1335
mii_autoneg_adv_reg)))
1338
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1340
if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1343
return E1000_SUCCESS;
1346
/******************************************************************************
1347
* Force PHY speed and duplex settings to hw->forced_speed_duplex
1349
* hw - Struct containing variables accessed by shared code
1350
******************************************************************************/
1352
e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1356
uint16_t mii_ctrl_reg;
1357
uint16_t mii_status_reg;
1361
DEBUGFUNC("e1000_phy_force_speed_duplex");
1363
/* Turn off Flow control if we are forcing speed and duplex. */
1364
hw->fc = e1000_fc_none;
1366
DEBUGOUT1("hw->fc = %d\n", hw->fc);
1368
/* Read the Device Control Register. */
1369
ctrl = E1000_READ_REG(hw, CTRL);
1371
/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1372
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1373
ctrl &= ~(DEVICE_SPEED_MASK);
1375
/* Clear the Auto Speed Detect Enable bit. */
1376
ctrl &= ~E1000_CTRL_ASDE;
1378
/* Read the MII Control Register. */
1379
if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
1382
/* We need to disable autoneg in order to force link and duplex. */
1384
mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1386
/* Are we forcing Full or Half Duplex? */
1387
if(hw->forced_speed_duplex == e1000_100_full ||
1388
hw->forced_speed_duplex == e1000_10_full) {
1389
/* We want to force full duplex so we SET the full duplex bits in the
1390
* Device and MII Control Registers.
1392
ctrl |= E1000_CTRL_FD;
1393
mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1394
DEBUGOUT("Full Duplex\n");
1396
/* We want to force half duplex so we CLEAR the full duplex bits in
1397
* the Device and MII Control Registers.
1399
ctrl &= ~E1000_CTRL_FD;
1400
mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1401
DEBUGOUT("Half Duplex\n");
1404
/* Are we forcing 100Mbps??? */
1405
if(hw->forced_speed_duplex == e1000_100_full ||
1406
hw->forced_speed_duplex == e1000_100_half) {
1407
/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1408
ctrl |= E1000_CTRL_SPD_100;
1409
mii_ctrl_reg |= MII_CR_SPEED_100;
1410
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1411
DEBUGOUT("Forcing 100mb ");
1413
/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1414
ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1415
mii_ctrl_reg |= MII_CR_SPEED_10;
1416
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1417
DEBUGOUT("Forcing 10mb ");
1420
e1000_config_collision_dist(hw);
1422
/* Write the configured values back to the Device Control Reg. */
1423
E1000_WRITE_REG(hw, CTRL, ctrl);
1425
if (hw->phy_type == e1000_phy_m88) {
1426
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1430
/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1431
* forced whenever speed are duplex are forced.
1433
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1434
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1438
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1440
/* Need to reset the PHY or these changes will be ignored */
1441
mii_ctrl_reg |= MII_CR_RESET;
1443
/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1444
* forced whenever speed or duplex are forced.
1446
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1450
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1451
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1453
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1458
/* Write back the modified PHY MII control register. */
1459
if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
1464
/* The wait_autoneg_complete flag may be a little misleading here.
1465
* Since we are forcing speed and duplex, Auto-Neg is not enabled.
1466
* But we do want to delay for a period while forcing only so we
1467
* don't generate false No Link messages. So we will wait here
1468
* only if the user has set wait_autoneg_complete to 1, which is
1471
if(hw->wait_autoneg_complete) {
1472
/* We will wait for autoneg to complete. */
1473
DEBUGOUT("Waiting for forced speed/duplex link.\n");
1476
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
1477
for(i = PHY_FORCE_TIME; i > 0; i--) {
1478
/* Read the MII Status Register and wait for Auto-Neg Complete bit
1481
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1484
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1487
if(mii_status_reg & MII_SR_LINK_STATUS) break;
1490
if(i == 0) { /* We didn't get link */
1491
/* Reset the DSP and wait again for link. */
1492
if((ret_val = e1000_phy_reset_dsp(hw))) {
1493
DEBUGOUT("Error Resetting PHY DSP\n");
1497
/* This loop will early-out if the link condition has been met. */
1498
for(i = PHY_FORCE_TIME; i > 0; i--) {
1499
if(mii_status_reg & MII_SR_LINK_STATUS) break;
1501
/* Read the MII Status Register and wait for Auto-Neg Complete bit
1504
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1507
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1512
if (hw->phy_type == e1000_phy_m88) {
1513
/* Because we reset the PHY above, we need to re-force TX_CLK in the
1514
* Extended PHY Specific Control Register to 25MHz clock. This value
1515
* defaults back to a 2.5MHz clock when the PHY is reset.
1517
if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1521
phy_data |= M88E1000_EPSCR_TX_CLK_25;
1522
if((ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1526
/* In addition, because of the s/w reset above, we need to enable CRS on
1527
* TX. This must be set for both full and half duplex operation.
1529
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1533
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1534
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1539
return E1000_SUCCESS;
1542
/******************************************************************************
1543
* Sets the collision distance in the Transmit Control register
1545
* hw - Struct containing variables accessed by shared code
1547
* Link should have been established previously. Reads the speed and duplex
1548
* information from the Device Status register.
1549
******************************************************************************/
1551
e1000_config_collision_dist(struct e1000_hw *hw)
1555
DEBUGFUNC("e1000_config_collision_dist");
1557
tctl = E1000_READ_REG(hw, TCTL);
1559
tctl &= ~E1000_TCTL_COLD;
1560
tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1562
E1000_WRITE_REG(hw, TCTL, tctl);
1563
E1000_WRITE_FLUSH(hw);
1566
/******************************************************************************
1567
* Sets MAC speed and duplex settings to reflect the those in the PHY
1569
* hw - Struct containing variables accessed by shared code
1570
* mii_reg - data to write to the MII control register
1572
* The contents of the PHY register containing the needed information need to
1574
******************************************************************************/
1576
e1000_config_mac_to_phy(struct e1000_hw *hw)
1582
DEBUGFUNC("e1000_config_mac_to_phy");
1584
/* Read the Device Control Register and set the bits to Force Speed
1587
ctrl = E1000_READ_REG(hw, CTRL);
1588
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1589
ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1591
/* Set up duplex in the Device Control and Transmit Control
1592
* registers depending on negotiated values.
1594
if (hw->phy_type == e1000_phy_igp) {
1595
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1599
if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1600
else ctrl &= ~E1000_CTRL_FD;
1602
e1000_config_collision_dist(hw);
1604
/* Set up speed in the Device Control register depending on
1605
* negotiated values.
1607
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1608
IGP01E1000_PSSR_SPEED_1000MBPS)
1609
ctrl |= E1000_CTRL_SPD_1000;
1610
else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1611
IGP01E1000_PSSR_SPEED_100MBPS)
1612
ctrl |= E1000_CTRL_SPD_100;
1614
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1618
if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1619
else ctrl &= ~E1000_CTRL_FD;
1621
e1000_config_collision_dist(hw);
1623
/* Set up speed in the Device Control register depending on
1624
* negotiated values.
1626
if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1627
ctrl |= E1000_CTRL_SPD_1000;
1628
else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1629
ctrl |= E1000_CTRL_SPD_100;
1631
/* Write the configured values back to the Device Control Reg. */
1632
E1000_WRITE_REG(hw, CTRL, ctrl);
1633
return E1000_SUCCESS;
1636
/******************************************************************************
1637
* Forces the MAC's flow control settings.
1639
* hw - Struct containing variables accessed by shared code
1641
* Sets the TFCE and RFCE bits in the device control register to reflect
1642
* the adapter settings. TFCE and RFCE need to be explicitly set by
1643
* software when a Copper PHY is used because autonegotiation is managed
1644
* by the PHY rather than the MAC. Software must also configure these
1645
* bits when link is forced on a fiber connection.
1646
*****************************************************************************/
1648
e1000_force_mac_fc(struct e1000_hw *hw)
1652
DEBUGFUNC("e1000_force_mac_fc");
1654
/* Get the current configuration of the Device Control Register */
1655
ctrl = E1000_READ_REG(hw, CTRL);
1657
/* Because we didn't get link via the internal auto-negotiation
1658
* mechanism (we either forced link or we got link via PHY
1659
* auto-neg), we have to manually enable/disable transmit an
1660
* receive flow control.
1662
* The "Case" statement below enables/disable flow control
1663
* according to the "hw->fc" parameter.
1665
* The possible values of the "fc" parameter are:
1666
* 0: Flow control is completely disabled
1667
* 1: Rx flow control is enabled (we can receive pause
1668
* frames but not send pause frames).
1669
* 2: Tx flow control is enabled (we can send pause frames
1670
* frames but we do not receive pause frames).
1671
* 3: Both Rx and TX flow control (symmetric) is enabled.
1672
* other: No other values should be possible at this point.
1677
ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1679
case e1000_fc_rx_pause:
1680
ctrl &= (~E1000_CTRL_TFCE);
1681
ctrl |= E1000_CTRL_RFCE;
1683
case e1000_fc_tx_pause:
1684
ctrl &= (~E1000_CTRL_RFCE);
1685
ctrl |= E1000_CTRL_TFCE;
1688
ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1691
DEBUGOUT("Flow control param set incorrectly\n");
1692
return -E1000_ERR_CONFIG;
1695
/* Disable TX Flow Control for 82542 (rev 2.0) */
1696
if(hw->mac_type == e1000_82542_rev2_0)
1697
ctrl &= (~E1000_CTRL_TFCE);
1699
E1000_WRITE_REG(hw, CTRL, ctrl);
1700
return E1000_SUCCESS;
1703
/******************************************************************************
1704
* Configures flow control settings after link is established
1706
* hw - Struct containing variables accessed by shared code
1708
* Should be called immediately after a valid link has been established.
1709
* Forces MAC flow control settings if link was forced. When in MII/GMII mode
1710
* and autonegotiation is enabled, the MAC flow control settings will be set
1711
* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1712
* and RFCE bits will be automaticaly set to the negotiated flow control mode.
1713
*****************************************************************************/
1715
e1000_config_fc_after_link_up(struct e1000_hw *hw)
1718
uint16_t mii_status_reg;
1719
uint16_t mii_nway_adv_reg;
1720
uint16_t mii_nway_lp_ability_reg;
1724
DEBUGFUNC("e1000_config_fc_after_link_up");
1726
/* Check for the case where we have fiber media and auto-neg failed
1727
* so we had to force link. In this case, we need to force the
1728
* configuration of the MAC to match the "fc" parameter.
1730
if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1731
((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1732
((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1733
if((ret_val = e1000_force_mac_fc(hw))) {
1734
DEBUGOUT("Error forcing flow control settings\n");
1739
/* Check for the case where we have copper media and auto-neg is
1740
* enabled. In this case, we need to check and see if Auto-Neg
1741
* has completed, and if so, how the PHY and link partner has
1742
* flow control configured.
1744
if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1745
/* Read the MII Status Register and check to see if AutoNeg
1746
* has completed. We read this twice because this reg has
1747
* some "sticky" (latched) bits.
1749
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1751
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1754
if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1755
/* The AutoNeg process has completed, so we now need to
1756
* read both the Auto Negotiation Advertisement Register
1757
* (Address 4) and the Auto_Negotiation Base Page Ability
1758
* Register (Address 5) to determine how flow control was
1761
if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1762
&mii_nway_adv_reg)))
1764
if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1765
&mii_nway_lp_ability_reg)))
1768
/* Two bits in the Auto Negotiation Advertisement Register
1769
* (Address 4) and two bits in the Auto Negotiation Base
1770
* Page Ability Register (Address 5) determine flow control
1771
* for both the PHY and the link partner. The following
1772
* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1773
* 1999, describes these PAUSE resolution bits and how flow
1774
* control is determined based upon these settings.
1775
* NOTE: DC = Don't Care
1777
* LOCAL DEVICE | LINK PARTNER
1778
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1779
*-------|---------|-------|---------|--------------------
1780
* 0 | 0 | DC | DC | e1000_fc_none
1781
* 0 | 1 | 0 | DC | e1000_fc_none
1782
* 0 | 1 | 1 | 0 | e1000_fc_none
1783
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1784
* 1 | 0 | 0 | DC | e1000_fc_none
1785
* 1 | DC | 1 | DC | e1000_fc_full
1786
* 1 | 1 | 0 | 0 | e1000_fc_none
1787
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1790
/* Are both PAUSE bits set to 1? If so, this implies
1791
* Symmetric Flow Control is enabled at both ends. The
1792
* ASM_DIR bits are irrelevant per the spec.
1794
* For Symmetric Flow Control:
1796
* LOCAL DEVICE | LINK PARTNER
1797
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1798
*-------|---------|-------|---------|--------------------
1799
* 1 | DC | 1 | DC | e1000_fc_full
1802
if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1803
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1804
/* Now we need to check if the user selected RX ONLY
1805
* of pause frames. In this case, we had to advertise
1806
* FULL flow control because we could not advertise RX
1807
* ONLY. Hence, we must now check to see if we need to
1808
* turn OFF the TRANSMISSION of PAUSE frames.
1810
if(hw->original_fc == e1000_fc_full) {
1811
hw->fc = e1000_fc_full;
1812
DEBUGOUT("Flow Control = FULL.\r\n");
1814
hw->fc = e1000_fc_rx_pause;
1815
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1818
/* For receiving PAUSE frames ONLY.
1820
* LOCAL DEVICE | LINK PARTNER
1821
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1822
*-------|---------|-------|---------|--------------------
1823
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1826
else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1827
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1828
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1829
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1830
hw->fc = e1000_fc_tx_pause;
1831
DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1833
/* For transmitting PAUSE frames ONLY.
1835
* LOCAL DEVICE | LINK PARTNER
1836
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1837
*-------|---------|-------|---------|--------------------
1838
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1841
else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1842
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1843
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1844
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1845
hw->fc = e1000_fc_rx_pause;
1846
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1848
/* Per the IEEE spec, at this point flow control should be
1849
* disabled. However, we want to consider that we could
1850
* be connected to a legacy switch that doesn't advertise
1851
* desired flow control, but can be forced on the link
1852
* partner. So if we advertised no flow control, that is
1853
* what we will resolve to. If we advertised some kind of
1854
* receive capability (Rx Pause Only or Full Flow Control)
1855
* and the link partner advertised none, we will configure
1856
* ourselves to enable Rx Flow Control only. We can do
1857
* this safely for two reasons: If the link partner really
1858
* didn't want flow control enabled, and we enable Rx, no
1859
* harm done since we won't be receiving any PAUSE frames
1860
* anyway. If the intent on the link partner was to have
1861
* flow control enabled, then by us enabling RX only, we
1862
* can at least receive pause frames and process them.
1863
* This is a good idea because in most cases, since we are
1864
* predominantly a server NIC, more times than not we will
1865
* be asked to delay transmission of packets than asking
1866
* our link partner to pause transmission of frames.
1868
else if(hw->original_fc == e1000_fc_none ||
1869
hw->original_fc == e1000_fc_tx_pause) {
1870
hw->fc = e1000_fc_none;
1871
DEBUGOUT("Flow Control = NONE.\r\n");
1872
} else if(!hw->fc_strict_ieee) {
1873
hw->fc = e1000_fc_rx_pause;
1874
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1877
/* Now we need to do one last check... If we auto-
1878
* negotiated to HALF DUPLEX, flow control should not be
1879
* enabled per IEEE 802.3 spec.
1881
if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
1882
DEBUGOUT("Error getting link speed and duplex\n");
1886
if(duplex == HALF_DUPLEX)
1887
hw->fc = e1000_fc_none;
1889
/* Now we call a subroutine to actually force the MAC
1890
* controller to use the correct flow control settings.
1892
if((ret_val = e1000_force_mac_fc(hw))) {
1893
DEBUGOUT("Error forcing flow control settings\n");
1897
DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1900
return E1000_SUCCESS;
1903
/******************************************************************************
1904
* Checks to see if the link status of the hardware has changed.
1906
* hw - Struct containing variables accessed by shared code
1908
* Called by any function that needs to check the link status of the adapter.
1909
*****************************************************************************/
1911
e1000_check_for_link(struct e1000_hw *hw)
1917
uint32_t signal = 0;
1920
uint16_t lp_capability;
1922
DEBUGFUNC("e1000_check_for_link");
1924
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1925
* set when the optics detect a signal. On older adapters, it will be
1926
* cleared when there is a signal. This applies to fiber media only.
1928
if(hw->media_type == e1000_media_type_fiber)
1929
signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1931
ctrl = E1000_READ_REG(hw, CTRL);
1932
status = E1000_READ_REG(hw, STATUS);
1933
rxcw = E1000_READ_REG(hw, RXCW);
1935
/* If we have a copper PHY then we only want to go out to the PHY
1936
* registers to see if Auto-Neg has completed and/or if our link
1937
* status has changed. The get_link_status flag will be set if we
1938
* receive a Link Status Change interrupt or we have Rx Sequence
1941
if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1942
/* First we want to see if the MII Status Register reports
1943
* link. If so, then we want to get the current speed/duplex
1945
* Read the register twice since the link bit is sticky.
1947
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1949
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1952
if(phy_data & MII_SR_LINK_STATUS) {
1953
hw->get_link_status = FALSE;
1954
/* Check if there was DownShift, must be checked immediately after
1956
e1000_check_downshift(hw);
1959
/* No link detected */
1960
e1000_config_dsp_after_link_change(hw, FALSE);
1964
/* If we are forcing speed/duplex, then we simply return since
1965
* we have already determined whether we have link or not.
1967
if(!hw->autoneg) return -E1000_ERR_CONFIG;
1969
/* optimize the dsp settings for the igp phy */
1970
e1000_config_dsp_after_link_change(hw, TRUE);
1972
/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1973
* have Si on board that is 82544 or newer, Auto
1974
* Speed Detection takes care of MAC speed/duplex
1975
* configuration. So we only need to configure Collision
1976
* Distance in the MAC. Otherwise, we need to force
1977
* speed/duplex on the MAC to the current PHY speed/duplex
1980
if(hw->mac_type >= e1000_82544)
1981
e1000_config_collision_dist(hw);
1983
if((ret_val = e1000_config_mac_to_phy(hw))) {
1984
DEBUGOUT("Error configuring MAC to PHY settings\n");
1989
/* Configure Flow Control now that Auto-Neg has completed. First, we
1990
* need to restore the desired flow control settings because we may
1991
* have had to re-autoneg with a different link partner.
1993
if((ret_val = e1000_config_fc_after_link_up(hw))) {
1994
DEBUGOUT("Error configuring flow control\n");
1998
/* At this point we know that we are on copper and we have
1999
* auto-negotiated link. These are conditions for checking the link
2000
* parter capability register. We use the link partner capability to
2001
* determine if TBI Compatibility needs to be turned on or off. If
2002
* the link partner advertises any speed in addition to Gigabit, then
2003
* we assume that they are GMII-based, and TBI compatibility is not
2004
* needed. If no other speeds are advertised, we assume the link
2005
* partner is TBI-based, and we turn on TBI Compatibility.
2007
if(hw->tbi_compatibility_en) {
2008
if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2011
if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
2012
NWAY_LPAR_10T_FD_CAPS |
2013
NWAY_LPAR_100TX_HD_CAPS |
2014
NWAY_LPAR_100TX_FD_CAPS |
2015
NWAY_LPAR_100T4_CAPS)) {
2016
/* If our link partner advertises anything in addition to
2017
* gigabit, we do not need to enable TBI compatibility.
2019
if(hw->tbi_compatibility_on) {
2020
/* If we previously were in the mode, turn it off. */
2021
rctl = E1000_READ_REG(hw, RCTL);
2022
rctl &= ~E1000_RCTL_SBP;
2023
E1000_WRITE_REG(hw, RCTL, rctl);
2024
hw->tbi_compatibility_on = FALSE;
2027
/* If TBI compatibility is was previously off, turn it on. For
2028
* compatibility with a TBI link partner, we will store bad
2029
* packets. Some frames have an additional byte on the end and
2030
* will look like CRC errors to to the hardware.
2032
if(!hw->tbi_compatibility_on) {
2033
hw->tbi_compatibility_on = TRUE;
2034
rctl = E1000_READ_REG(hw, RCTL);
2035
rctl |= E1000_RCTL_SBP;
2036
E1000_WRITE_REG(hw, RCTL, rctl);
2041
/* If we don't have link (auto-negotiation failed or link partner cannot
2042
* auto-negotiate), the cable is plugged in (we have signal), and our
2043
* link partner is not trying to auto-negotiate with us (we are receiving
2044
* idles or data), we need to force link up. We also need to give
2045
* auto-negotiation time to complete, in case the cable was just plugged
2046
* in. The autoneg_failed flag does this.
2048
else if((hw->media_type == e1000_media_type_fiber) &&
2049
(!(status & E1000_STATUS_LU)) &&
2050
((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
2051
(!(rxcw & E1000_RXCW_C))) {
2052
if(hw->autoneg_failed == 0) {
2053
hw->autoneg_failed = 1;
2056
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2058
/* Disable auto-negotiation in the TXCW register */
2059
E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2061
/* Force link-up and also force full-duplex. */
2062
ctrl = E1000_READ_REG(hw, CTRL);
2063
ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2064
E1000_WRITE_REG(hw, CTRL, ctrl);
2066
/* Configure Flow Control after forcing link up. */
2067
if((ret_val = e1000_config_fc_after_link_up(hw))) {
2068
DEBUGOUT("Error configuring flow control\n");
2072
/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2073
* auto-negotiation in the TXCW register and disable forced link in the
2074
* Device Control register in an attempt to auto-negotiate with our link
2077
else if((hw->media_type == e1000_media_type_fiber) &&
2078
(ctrl & E1000_CTRL_SLU) &&
2079
(rxcw & E1000_RXCW_C)) {
2080
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2081
E1000_WRITE_REG(hw, TXCW, hw->txcw);
2082
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2084
return E1000_SUCCESS;
2087
/******************************************************************************
2088
* Detects the current speed and duplex settings of the hardware.
2090
* hw - Struct containing variables accessed by shared code
2091
* speed - Speed of the connection
2092
* duplex - Duplex setting of the connection
2093
*****************************************************************************/
2095
e1000_get_speed_and_duplex(struct e1000_hw *hw,
2103
DEBUGFUNC("e1000_get_speed_and_duplex");
2105
if(hw->mac_type >= e1000_82543) {
2106
status = E1000_READ_REG(hw, STATUS);
2107
if(status & E1000_STATUS_SPEED_1000) {
2108
*speed = SPEED_1000;
2109
DEBUGOUT("1000 Mbs, ");
2110
} else if(status & E1000_STATUS_SPEED_100) {
2112
DEBUGOUT("100 Mbs, ");
2115
DEBUGOUT("10 Mbs, ");
2118
if(status & E1000_STATUS_FD) {
2119
*duplex = FULL_DUPLEX;
2120
DEBUGOUT("Full Duplex\r\n");
2122
*duplex = HALF_DUPLEX;
2123
DEBUGOUT(" Half Duplex\r\n");
2126
DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2127
*speed = SPEED_1000;
2128
*duplex = FULL_DUPLEX;
2131
/* IGP01 PHY may advertise full duplex operation after speed downgrade even
2132
* if it is operating at half duplex. Here we set the duplex settings to
2133
* match the duplex in the link partner's capabilities.
2135
if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2136
if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
2139
if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2140
*duplex = HALF_DUPLEX;
2142
if((ret_val == e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
2144
if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2145
(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2146
*duplex = HALF_DUPLEX;
2150
return E1000_SUCCESS;
2153
/******************************************************************************
2154
* Blocks until autoneg completes or times out (~4.5 seconds)
2156
* hw - Struct containing variables accessed by shared code
2157
******************************************************************************/
2159
e1000_wait_autoneg(struct e1000_hw *hw)
2165
DEBUGFUNC("e1000_wait_autoneg");
2166
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2168
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
2169
for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2170
/* Read the MII Status Register and wait for Auto-Neg
2171
* Complete bit to be set.
2173
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2175
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2177
if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2178
return E1000_SUCCESS;
2182
return E1000_SUCCESS;
2185
/******************************************************************************
2186
* Raises the Management Data Clock
2188
* hw - Struct containing variables accessed by shared code
2189
* ctrl - Device control register's current value
2190
******************************************************************************/
2192
e1000_raise_mdi_clk(struct e1000_hw *hw,
2195
/* Raise the clock input to the Management Data Clock (by setting the MDC
2196
* bit), and then delay 10 microseconds.
2198
E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2199
E1000_WRITE_FLUSH(hw);
2203
/******************************************************************************
2204
* Lowers the Management Data Clock
2206
* hw - Struct containing variables accessed by shared code
2207
* ctrl - Device control register's current value
2208
******************************************************************************/
2210
e1000_lower_mdi_clk(struct e1000_hw *hw,
2213
/* Lower the clock input to the Management Data Clock (by clearing the MDC
2214
* bit), and then delay 10 microseconds.
2216
E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2217
E1000_WRITE_FLUSH(hw);
2221
/******************************************************************************
2222
* Shifts data bits out to the PHY
2224
* hw - Struct containing variables accessed by shared code
2225
* data - Data to send out to the PHY
2226
* count - Number of bits to shift out
2228
* Bits are shifted out in MSB to LSB order.
2229
******************************************************************************/
2231
e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2238
/* We need to shift "count" number of bits out to the PHY. So, the value
2239
* in the "data" parameter will be shifted out to the PHY one bit at a
2240
* time. In order to do this, "data" must be broken down into bits.
2243
mask <<= (count - 1);
2245
ctrl = E1000_READ_REG(hw, CTRL);
2247
/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2248
ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2251
/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2252
* then raising and lowering the Management Data Clock. A "0" is
2253
* shifted out to the PHY by setting the MDIO bit to "0" and then
2254
* raising and lowering the clock.
2256
if(data & mask) ctrl |= E1000_CTRL_MDIO;
2257
else ctrl &= ~E1000_CTRL_MDIO;
2259
E1000_WRITE_REG(hw, CTRL, ctrl);
2260
E1000_WRITE_FLUSH(hw);
2264
e1000_raise_mdi_clk(hw, &ctrl);
2265
e1000_lower_mdi_clk(hw, &ctrl);
2271
/******************************************************************************
2272
* Shifts data bits in from the PHY
2274
* hw - Struct containing variables accessed by shared code
2276
* Bits are shifted in in MSB to LSB order.
2277
******************************************************************************/
2279
e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2285
/* In order to read a register from the PHY, we need to shift in a total
2286
* of 18 bits from the PHY. The first two bit (turnaround) times are used
2287
* to avoid contention on the MDIO pin when a read operation is performed.
2288
* These two bits are ignored by us and thrown away. Bits are "shifted in"
2289
* by raising the input to the Management Data Clock (setting the MDC bit),
2290
* and then reading the value of the MDIO bit.
2292
ctrl = E1000_READ_REG(hw, CTRL);
2294
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2295
ctrl &= ~E1000_CTRL_MDIO_DIR;
2296
ctrl &= ~E1000_CTRL_MDIO;
2298
E1000_WRITE_REG(hw, CTRL, ctrl);
2299
E1000_WRITE_FLUSH(hw);
2301
/* Raise and Lower the clock before reading in the data. This accounts for
2302
* the turnaround bits. The first clock occurred when we clocked out the
2303
* last bit of the Register Address.
2305
e1000_raise_mdi_clk(hw, &ctrl);
2306
e1000_lower_mdi_clk(hw, &ctrl);
2308
for(data = 0, i = 0; i < 16; i++) {
2310
e1000_raise_mdi_clk(hw, &ctrl);
2311
ctrl = E1000_READ_REG(hw, CTRL);
2312
/* Check to see if we shifted in a "1". */
2313
if(ctrl & E1000_CTRL_MDIO) data |= 1;
2314
e1000_lower_mdi_clk(hw, &ctrl);
2317
e1000_raise_mdi_clk(hw, &ctrl);
2318
e1000_lower_mdi_clk(hw, &ctrl);
2323
/*****************************************************************************
2324
* Reads the value from a PHY register, if the value is on a specific non zero
2325
* page, sets the page first.
2326
* hw - Struct containing variables accessed by shared code
2327
* reg_addr - address of the PHY register to read
2328
******************************************************************************/
2330
e1000_read_phy_reg(struct e1000_hw *hw,
2336
DEBUGFUNC("e1000_read_phy_reg");
2338
if(hw->phy_type == e1000_phy_igp &&
2339
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2340
if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2341
(uint16_t)reg_addr)))
2345
ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2352
e1000_read_phy_reg_ex(struct e1000_hw *hw,
2358
const uint32_t phy_addr = 1;
2360
DEBUGFUNC("e1000_read_phy_reg_ex");
2362
if(reg_addr > MAX_PHY_REG_ADDRESS) {
2363
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2364
return -E1000_ERR_PARAM;
2367
if(hw->mac_type > e1000_82543) {
2368
/* Set up Op-code, Phy Address, and register address in the MDI
2369
* Control register. The MAC will take care of interfacing with the
2370
* PHY to retrieve the desired data.
2372
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2373
(phy_addr << E1000_MDIC_PHY_SHIFT) |
2374
(E1000_MDIC_OP_READ));
2376
E1000_WRITE_REG(hw, MDIC, mdic);
2378
/* Poll the ready bit to see if the MDI read completed */
2379
for(i = 0; i < 64; i++) {
2381
mdic = E1000_READ_REG(hw, MDIC);
2382
if(mdic & E1000_MDIC_READY) break;
2384
if(!(mdic & E1000_MDIC_READY)) {
2385
DEBUGOUT("MDI Read did not complete\n");
2386
return -E1000_ERR_PHY;
2388
if(mdic & E1000_MDIC_ERROR) {
2389
DEBUGOUT("MDI Error\n");
2390
return -E1000_ERR_PHY;
2392
*phy_data = (uint16_t) mdic;
2394
/* We must first send a preamble through the MDIO pin to signal the
2395
* beginning of an MII instruction. This is done by sending 32
2396
* consecutive "1" bits.
2398
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2400
/* Now combine the next few fields that are required for a read
2401
* operation. We use this method instead of calling the
2402
* e1000_shift_out_mdi_bits routine five different times. The format of
2403
* a MII read instruction consists of a shift out of 14 bits and is
2404
* defined as follows:
2405
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2406
* followed by a shift in of 18 bits. This first two bits shifted in
2407
* are TurnAround bits used to avoid contention on the MDIO pin when a
2408
* READ operation is performed. These two bits are thrown away
2409
* followed by a shift in of 16 bits which contains the desired data.
2411
mdic = ((reg_addr) | (phy_addr << 5) |
2412
(PHY_OP_READ << 10) | (PHY_SOF << 12));
2414
e1000_shift_out_mdi_bits(hw, mdic, 14);
2416
/* Now that we've shifted out the read command to the MII, we need to
2417
* "shift in" the 16-bit value (18 total bits) of the requested PHY
2420
*phy_data = e1000_shift_in_mdi_bits(hw);
2422
return E1000_SUCCESS;
2425
/******************************************************************************
2426
* Writes a value to a PHY register
2428
* hw - Struct containing variables accessed by shared code
2429
* reg_addr - address of the PHY register to write
2430
* data - data to write to the PHY
2431
******************************************************************************/
2433
e1000_write_phy_reg(struct e1000_hw *hw,
2439
DEBUGFUNC("e1000_write_phy_reg");
2441
if(hw->phy_type == e1000_phy_igp &&
2442
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2443
if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2444
(uint16_t)reg_addr)))
2448
ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2455
e1000_write_phy_reg_ex(struct e1000_hw *hw,
2461
const uint32_t phy_addr = 1;
2463
DEBUGFUNC("e1000_write_phy_reg_ex");
2465
if(reg_addr > MAX_PHY_REG_ADDRESS) {
2466
DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2467
return -E1000_ERR_PARAM;
2470
if(hw->mac_type > e1000_82543) {
2471
/* Set up Op-code, Phy Address, register address, and data intended
2472
* for the PHY register in the MDI Control register. The MAC will take
2473
* care of interfacing with the PHY to send the desired data.
2475
mdic = (((uint32_t) phy_data) |
2476
(reg_addr << E1000_MDIC_REG_SHIFT) |
2477
(phy_addr << E1000_MDIC_PHY_SHIFT) |
2478
(E1000_MDIC_OP_WRITE));
2480
E1000_WRITE_REG(hw, MDIC, mdic);
2482
/* Poll the ready bit to see if the MDI read completed */
2483
for(i = 0; i < 64; i++) {
2485
mdic = E1000_READ_REG(hw, MDIC);
2486
if(mdic & E1000_MDIC_READY) break;
2488
if(!(mdic & E1000_MDIC_READY)) {
2489
DEBUGOUT("MDI Write did not complete\n");
2490
return -E1000_ERR_PHY;
2493
/* We'll need to use the SW defined pins to shift the write command
2494
* out to the PHY. We first send a preamble to the PHY to signal the
2495
* beginning of the MII instruction. This is done by sending 32
2496
* consecutive "1" bits.
2498
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2500
/* Now combine the remaining required fields that will indicate a
2501
* write operation. We use this method instead of calling the
2502
* e1000_shift_out_mdi_bits routine for each field in the command. The
2503
* format of a MII write instruction is as follows:
2504
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2506
mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2507
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2509
mdic |= (uint32_t) phy_data;
2511
e1000_shift_out_mdi_bits(hw, mdic, 32);
2514
return E1000_SUCCESS;
2517
/******************************************************************************
2518
* Returns the PHY to the power-on reset state
2520
* hw - Struct containing variables accessed by shared code
2521
******************************************************************************/
2523
e1000_phy_hw_reset(struct e1000_hw *hw)
2525
uint32_t ctrl, ctrl_ext;
2528
DEBUGFUNC("e1000_phy_hw_reset");
2530
DEBUGOUT("Resetting Phy...\n");
2532
if(hw->mac_type > e1000_82543) {
2533
/* Read the device control register and assert the E1000_CTRL_PHY_RST
2534
* bit. Then, take it out of reset.
2536
ctrl = E1000_READ_REG(hw, CTRL);
2537
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2538
E1000_WRITE_FLUSH(hw);
2540
E1000_WRITE_REG(hw, CTRL, ctrl);
2541
E1000_WRITE_FLUSH(hw);
2543
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2544
* bit to put the PHY into reset. Then, take it out of reset.
2546
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2547
ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2548
ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2549
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2550
E1000_WRITE_FLUSH(hw);
2552
ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2553
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2554
E1000_WRITE_FLUSH(hw);
2558
if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2559
/* Configure activity LED after PHY reset */
2560
led_ctrl = E1000_READ_REG(hw, LEDCTL);
2561
led_ctrl &= IGP_ACTIVITY_LED_MASK;
2562
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2563
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2567
/******************************************************************************
2570
* hw - Struct containing variables accessed by shared code
2572
* Sets bit 15 of the MII Control regiser
2573
******************************************************************************/
2575
e1000_phy_reset(struct e1000_hw *hw)
2580
DEBUGFUNC("e1000_phy_reset");
2582
if(hw->mac_type != e1000_82541_rev_2) {
2583
if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2586
phy_data |= MII_CR_RESET;
2587
if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
2591
} else e1000_phy_hw_reset(hw);
2593
if(hw->phy_type == e1000_phy_igp)
2594
e1000_phy_init_script(hw);
2596
return E1000_SUCCESS;
2599
/******************************************************************************
2600
* Probes the expected PHY address for known PHY IDs
2602
* hw - Struct containing variables accessed by shared code
2603
******************************************************************************/
2605
e1000_detect_gig_phy(struct e1000_hw *hw)
2607
int32_t phy_init_status, ret_val;
2608
uint16_t phy_id_high, phy_id_low;
2609
boolean_t match = FALSE;
2611
DEBUGFUNC("e1000_detect_gig_phy");
2613
/* Read the PHY ID Registers to identify which PHY is onboard. */
2614
if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2617
hw->phy_id = (uint32_t) (phy_id_high << 16);
2619
if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2622
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2623
hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2625
switch(hw->mac_type) {
2627
if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2630
if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2634
case e1000_82545_rev_3:
2636
case e1000_82546_rev_3:
2637
if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2640
case e1000_82541_rev_2:
2642
case e1000_82547_rev_2:
2643
if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2646
DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2647
return -E1000_ERR_CONFIG;
2649
phy_init_status = e1000_set_phy_type(hw);
2651
if ((match) && (phy_init_status == E1000_SUCCESS)) {
2652
DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2653
return E1000_SUCCESS;
2655
DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2656
return -E1000_ERR_PHY;
2659
/******************************************************************************
2660
* Resets the PHY's DSP
2662
* hw - Struct containing variables accessed by shared code
2663
******************************************************************************/
2665
e1000_phy_reset_dsp(struct e1000_hw *hw)
2668
DEBUGFUNC("e1000_phy_reset_dsp");
2671
if((ret_val = e1000_write_phy_reg(hw, 29, 0x001d))) break;
2672
if((ret_val = e1000_write_phy_reg(hw, 30, 0x00c1))) break;
2673
if((ret_val = e1000_write_phy_reg(hw, 30, 0x0000))) break;
2674
ret_val = E1000_SUCCESS;
2680
/******************************************************************************
2681
* Get PHY information from various PHY registers for igp PHY only.
2683
* hw - Struct containing variables accessed by shared code
2684
* phy_info - PHY information structure
2685
******************************************************************************/
2687
e1000_phy_igp_get_info(struct e1000_hw *hw,
2688
struct e1000_phy_info *phy_info)
2691
uint16_t phy_data, polarity, min_length, max_length, average;
2693
DEBUGFUNC("e1000_phy_igp_get_info");
2695
/* The downshift status is checked only once, after link is established,
2696
* and it stored in the hw->speed_downgraded parameter. */
2697
phy_info->downshift = hw->speed_downgraded;
2699
/* IGP01E1000 does not need to support it. */
2700
phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
2702
/* IGP01E1000 always correct polarity reversal */
2703
phy_info->polarity_correction = e1000_polarity_reversal_enabled;
2705
/* Check polarity status */
2706
if((ret_val = e1000_check_polarity(hw, &polarity)))
2709
phy_info->cable_polarity = polarity;
2711
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2715
phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2716
IGP01E1000_PSSR_MDIX_SHIFT;
2718
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2719
IGP01E1000_PSSR_SPEED_1000MBPS) {
2720
/* Local/Remote Receiver Information are only valid at 1000 Mbps */
2721
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2724
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2725
SR_1000T_LOCAL_RX_STATUS_SHIFT;
2726
phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2727
SR_1000T_REMOTE_RX_STATUS_SHIFT;
2729
/* Get cable length */
2730
if((ret_val = e1000_get_cable_length(hw, &min_length, &max_length)))
2733
/* transalte to old method */
2734
average = (max_length + min_length) / 2;
2736
if(average <= e1000_igp_cable_length_50)
2737
phy_info->cable_length = e1000_cable_length_50;
2738
else if(average <= e1000_igp_cable_length_80)
2739
phy_info->cable_length = e1000_cable_length_50_80;
2740
else if(average <= e1000_igp_cable_length_110)
2741
phy_info->cable_length = e1000_cable_length_80_110;
2742
else if(average <= e1000_igp_cable_length_140)
2743
phy_info->cable_length = e1000_cable_length_110_140;
2745
phy_info->cable_length = e1000_cable_length_140;
2748
return E1000_SUCCESS;
2751
/******************************************************************************
2752
* Get PHY information from various PHY registers fot m88 PHY only.
2754
* hw - Struct containing variables accessed by shared code
2755
* phy_info - PHY information structure
2756
******************************************************************************/
2758
e1000_phy_m88_get_info(struct e1000_hw *hw,
2759
struct e1000_phy_info *phy_info)
2762
uint16_t phy_data, polarity;
2764
DEBUGFUNC("e1000_phy_m88_get_info");
2766
/* The downshift status is checked only once, after link is established,
2767
* and it stored in the hw->speed_downgraded parameter. */
2768
phy_info->downshift = hw->speed_downgraded;
2770
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
2773
phy_info->extended_10bt_distance =
2774
(phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2775
M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2776
phy_info->polarity_correction =
2777
(phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2778
M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2780
/* Check polarity status */
2781
if((ret_val = e1000_check_polarity(hw, &polarity)))
2784
phy_info->cable_polarity = polarity;
2786
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
2789
phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2790
M88E1000_PSSR_MDIX_SHIFT;
2792
if(phy_data & M88E1000_PSSR_1000MBS) {
2793
/* Cable Length Estimation and Local/Remote Receiver Informatoion
2794
* are only valid at 1000 Mbps
2796
phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2797
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2799
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2802
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2803
SR_1000T_LOCAL_RX_STATUS_SHIFT;
2805
phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2806
SR_1000T_REMOTE_RX_STATUS_SHIFT;
2809
return E1000_SUCCESS;
2812
/******************************************************************************
2813
* Get PHY information from various PHY registers
2815
* hw - Struct containing variables accessed by shared code
2816
* phy_info - PHY information structure
2817
******************************************************************************/
2819
e1000_phy_get_info(struct e1000_hw *hw,
2820
struct e1000_phy_info *phy_info)
2825
DEBUGFUNC("e1000_phy_get_info");
2827
phy_info->cable_length = e1000_cable_length_undefined;
2828
phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
2829
phy_info->cable_polarity = e1000_rev_polarity_undefined;
2830
phy_info->downshift = e1000_downshift_undefined;
2831
phy_info->polarity_correction = e1000_polarity_reversal_undefined;
2832
phy_info->mdix_mode = e1000_auto_x_mode_undefined;
2833
phy_info->local_rx = e1000_1000t_rx_status_undefined;
2834
phy_info->remote_rx = e1000_1000t_rx_status_undefined;
2836
if(hw->media_type != e1000_media_type_copper) {
2837
DEBUGOUT("PHY info is only valid for copper media\n");
2838
return -E1000_ERR_CONFIG;
2841
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2844
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2847
if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2848
DEBUGOUT("PHY info is only valid if link is up\n");
2849
return -E1000_ERR_CONFIG;
2852
if(hw->phy_type == e1000_phy_igp)
2853
return e1000_phy_igp_get_info(hw, phy_info);
2855
return e1000_phy_m88_get_info(hw, phy_info);
2859
e1000_validate_mdi_setting(struct e1000_hw *hw)
2861
DEBUGFUNC("e1000_validate_mdi_settings");
2863
if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2864
DEBUGOUT("Invalid MDI setting detected\n");
2866
return -E1000_ERR_CONFIG;
2868
return E1000_SUCCESS;
2872
/******************************************************************************
2873
* Sets up eeprom variables in the hw struct. Must be called after mac_type
2876
* hw - Struct containing variables accessed by shared code
2877
*****************************************************************************/
2879
e1000_init_eeprom_params(struct e1000_hw *hw)
2881
struct e1000_eeprom_info *eeprom = &hw->eeprom;
2882
uint32_t eecd = E1000_READ_REG(hw, EECD);
2883
uint16_t eeprom_size;
2885
DEBUGFUNC("e1000_init_eeprom_params");
2887
switch (hw->mac_type) {
2888
case e1000_82542_rev2_0:
2889
case e1000_82542_rev2_1:
2892
eeprom->type = e1000_eeprom_microwire;
2893
eeprom->word_size = 64;
2894
eeprom->opcode_bits = 3;
2895
eeprom->address_bits = 6;
2896
eeprom->delay_usec = 50;
2900
case e1000_82545_rev_3:
2902
case e1000_82546_rev_3:
2903
eeprom->type = e1000_eeprom_microwire;
2904
eeprom->opcode_bits = 3;
2905
eeprom->delay_usec = 50;
2906
if(eecd & E1000_EECD_SIZE) {
2907
eeprom->word_size = 256;
2908
eeprom->address_bits = 8;
2910
eeprom->word_size = 64;
2911
eeprom->address_bits = 6;
2915
case e1000_82541_rev_2:
2917
case e1000_82547_rev_2:
2918
if (eecd & E1000_EECD_TYPE) {
2919
eeprom->type = e1000_eeprom_spi;
2920
eeprom->opcode_bits = 8;
2921
eeprom->delay_usec = 1;
2922
if (eecd & E1000_EECD_ADDR_BITS) {
2923
eeprom->page_size = 32;
2924
eeprom->address_bits = 16;
2926
eeprom->page_size = 8;
2927
eeprom->address_bits = 8;
2930
eeprom->type = e1000_eeprom_microwire;
2931
eeprom->opcode_bits = 3;
2932
eeprom->delay_usec = 50;
2933
if (eecd & E1000_EECD_ADDR_BITS) {
2934
eeprom->word_size = 256;
2935
eeprom->address_bits = 8;
2937
eeprom->word_size = 64;
2938
eeprom->address_bits = 6;
2943
eeprom->type = e1000_eeprom_spi;
2944
eeprom->opcode_bits = 8;
2945
eeprom->delay_usec = 1;
2946
if (eecd & E1000_EECD_ADDR_BITS) {
2947
eeprom->page_size = 32;
2948
eeprom->address_bits = 16;
2950
eeprom->page_size = 8;
2951
eeprom->address_bits = 8;
2956
if (eeprom->type == e1000_eeprom_spi) {
2957
eeprom->word_size = 64;
2958
if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2959
eeprom_size &= EEPROM_SIZE_MASK;
2961
switch (eeprom_size) {
2962
case EEPROM_SIZE_16KB:
2963
eeprom->word_size = 8192;
2965
case EEPROM_SIZE_8KB:
2966
eeprom->word_size = 4096;
2968
case EEPROM_SIZE_4KB:
2969
eeprom->word_size = 2048;
2971
case EEPROM_SIZE_2KB:
2972
eeprom->word_size = 1024;
2974
case EEPROM_SIZE_1KB:
2975
eeprom->word_size = 512;
2977
case EEPROM_SIZE_512B:
2978
eeprom->word_size = 256;
2980
case EEPROM_SIZE_128B:
2982
eeprom->word_size = 64;
2989
/******************************************************************************
2990
* Raises the EEPROM's clock input.
2992
* hw - Struct containing variables accessed by shared code
2993
* eecd - EECD's current value
2994
*****************************************************************************/
2996
e1000_raise_ee_clk(struct e1000_hw *hw,
2999
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
3000
* wait <delay> microseconds.
3002
*eecd = *eecd | E1000_EECD_SK;
3003
E1000_WRITE_REG(hw, EECD, *eecd);
3004
E1000_WRITE_FLUSH(hw);
3005
usec_delay(hw->eeprom.delay_usec);
3008
/******************************************************************************
3009
* Lowers the EEPROM's clock input.
3011
* hw - Struct containing variables accessed by shared code
3012
* eecd - EECD's current value
3013
*****************************************************************************/
3015
e1000_lower_ee_clk(struct e1000_hw *hw,
3018
/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3019
* wait 50 microseconds.
3021
*eecd = *eecd & ~E1000_EECD_SK;
3022
E1000_WRITE_REG(hw, EECD, *eecd);
3023
E1000_WRITE_FLUSH(hw);
3024
usec_delay(hw->eeprom.delay_usec);
3027
/******************************************************************************
3028
* Shift data bits out to the EEPROM.
3030
* hw - Struct containing variables accessed by shared code
3031
* data - data to send to the EEPROM
3032
* count - number of bits to shift out
3033
*****************************************************************************/
3035
e1000_shift_out_ee_bits(struct e1000_hw *hw,
3039
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3043
/* We need to shift "count" bits out to the EEPROM. So, value in the
3044
* "data" parameter will be shifted out to the EEPROM one bit at a time.
3045
* In order to do this, "data" must be broken down into bits.
3047
mask = 0x01 << (count - 1);
3048
eecd = E1000_READ_REG(hw, EECD);
3049
if (eeprom->type == e1000_eeprom_microwire) {
3050
eecd &= ~E1000_EECD_DO;
3051
} else if (eeprom->type == e1000_eeprom_spi) {
3052
eecd |= E1000_EECD_DO;
3055
/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3056
* and then raising and then lowering the clock (the SK bit controls
3057
* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3058
* by setting "DI" to "0" and then raising and then lowering the clock.
3060
eecd &= ~E1000_EECD_DI;
3063
eecd |= E1000_EECD_DI;
3065
E1000_WRITE_REG(hw, EECD, eecd);
3066
E1000_WRITE_FLUSH(hw);
3068
usec_delay(eeprom->delay_usec);
3070
e1000_raise_ee_clk(hw, &eecd);
3071
e1000_lower_ee_clk(hw, &eecd);
3077
/* We leave the "DI" bit set to "0" when we leave this routine. */
3078
eecd &= ~E1000_EECD_DI;
3079
E1000_WRITE_REG(hw, EECD, eecd);
3082
/******************************************************************************
3083
* Shift data bits in from the EEPROM
3085
* hw - Struct containing variables accessed by shared code
3086
*****************************************************************************/
3088
e1000_shift_in_ee_bits(struct e1000_hw *hw,
3095
/* In order to read a register from the EEPROM, we need to shift 'count'
3096
* bits in from the EEPROM. Bits are "shifted in" by raising the clock
3097
* input to the EEPROM (setting the SK bit), and then reading the value of
3098
* the "DO" bit. During this "shifting in" process the "DI" bit should
3102
eecd = E1000_READ_REG(hw, EECD);
3104
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3107
for(i = 0; i < count; i++) {
3109
e1000_raise_ee_clk(hw, &eecd);
3111
eecd = E1000_READ_REG(hw, EECD);
3113
eecd &= ~(E1000_EECD_DI);
3114
if(eecd & E1000_EECD_DO)
3117
e1000_lower_ee_clk(hw, &eecd);
3123
/******************************************************************************
3124
* Prepares EEPROM for access
3126
* hw - Struct containing variables accessed by shared code
3128
* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3129
* function should be called before issuing a command to the EEPROM.
3130
*****************************************************************************/
3132
e1000_acquire_eeprom(struct e1000_hw *hw)
3134
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3137
DEBUGFUNC("e1000_acquire_eeprom");
3139
eecd = E1000_READ_REG(hw, EECD);
3141
/* Request EEPROM Access */
3142
if(hw->mac_type > e1000_82544) {
3143
eecd |= E1000_EECD_REQ;
3144
E1000_WRITE_REG(hw, EECD, eecd);
3145
eecd = E1000_READ_REG(hw, EECD);
3146
while((!(eecd & E1000_EECD_GNT)) &&
3147
(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3150
eecd = E1000_READ_REG(hw, EECD);
3152
if(!(eecd & E1000_EECD_GNT)) {
3153
eecd &= ~E1000_EECD_REQ;
3154
E1000_WRITE_REG(hw, EECD, eecd);
3155
DEBUGOUT("Could not acquire EEPROM grant\n");
3156
return -E1000_ERR_EEPROM;
3160
/* Setup EEPROM for Read/Write */
3162
if (eeprom->type == e1000_eeprom_microwire) {
3163
/* Clear SK and DI */
3164
eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3165
E1000_WRITE_REG(hw, EECD, eecd);
3168
eecd |= E1000_EECD_CS;
3169
E1000_WRITE_REG(hw, EECD, eecd);
3170
} else if (eeprom->type == e1000_eeprom_spi) {
3171
/* Clear SK and CS */
3172
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3173
E1000_WRITE_REG(hw, EECD, eecd);
3177
return E1000_SUCCESS;
3180
/******************************************************************************
3181
* Returns EEPROM to a "standby" state
3183
* hw - Struct containing variables accessed by shared code
3184
*****************************************************************************/
3186
e1000_standby_eeprom(struct e1000_hw *hw)
3188
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3191
eecd = E1000_READ_REG(hw, EECD);
3193
if(eeprom->type == e1000_eeprom_microwire) {
3194
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3195
E1000_WRITE_REG(hw, EECD, eecd);
3196
E1000_WRITE_FLUSH(hw);
3197
usec_delay(eeprom->delay_usec);
3200
eecd |= E1000_EECD_SK;
3201
E1000_WRITE_REG(hw, EECD, eecd);
3202
E1000_WRITE_FLUSH(hw);
3203
usec_delay(eeprom->delay_usec);
3206
eecd |= E1000_EECD_CS;
3207
E1000_WRITE_REG(hw, EECD, eecd);
3208
E1000_WRITE_FLUSH(hw);
3209
usec_delay(eeprom->delay_usec);
3212
eecd &= ~E1000_EECD_SK;
3213
E1000_WRITE_REG(hw, EECD, eecd);
3214
E1000_WRITE_FLUSH(hw);
3215
usec_delay(eeprom->delay_usec);
3216
} else if(eeprom->type == e1000_eeprom_spi) {
3217
/* Toggle CS to flush commands */
3218
eecd |= E1000_EECD_CS;
3219
E1000_WRITE_REG(hw, EECD, eecd);
3220
E1000_WRITE_FLUSH(hw);
3221
usec_delay(eeprom->delay_usec);
3222
eecd &= ~E1000_EECD_CS;
3223
E1000_WRITE_REG(hw, EECD, eecd);
3224
E1000_WRITE_FLUSH(hw);
3225
usec_delay(eeprom->delay_usec);
3229
/******************************************************************************
3230
* Terminates a command by inverting the EEPROM's chip select pin
3232
* hw - Struct containing variables accessed by shared code
3233
*****************************************************************************/
3235
e1000_release_eeprom(struct e1000_hw *hw)
3239
DEBUGFUNC("e1000_release_eeprom");
3241
eecd = E1000_READ_REG(hw, EECD);
3243
if (hw->eeprom.type == e1000_eeprom_spi) {
3244
eecd |= E1000_EECD_CS; /* Pull CS high */
3245
eecd &= ~E1000_EECD_SK; /* Lower SCK */
3247
E1000_WRITE_REG(hw, EECD, eecd);
3249
usec_delay(hw->eeprom.delay_usec);
3250
} else if(hw->eeprom.type == e1000_eeprom_microwire) {
3251
/* cleanup eeprom */
3253
/* CS on Microwire is active-high */
3254
eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3256
E1000_WRITE_REG(hw, EECD, eecd);
3258
/* Rising edge of clock */
3259
eecd |= E1000_EECD_SK;
3260
E1000_WRITE_REG(hw, EECD, eecd);
3261
E1000_WRITE_FLUSH(hw);
3262
usec_delay(hw->eeprom.delay_usec);
3264
/* Falling edge of clock */
3265
eecd &= ~E1000_EECD_SK;
3266
E1000_WRITE_REG(hw, EECD, eecd);
3267
E1000_WRITE_FLUSH(hw);
3268
usec_delay(hw->eeprom.delay_usec);
3271
/* Stop requesting EEPROM access */
3272
if(hw->mac_type > e1000_82544) {
3273
eecd &= ~E1000_EECD_REQ;
3274
E1000_WRITE_REG(hw, EECD, eecd);
3278
/******************************************************************************
3279
* Reads a 16 bit word from the EEPROM.
3281
* hw - Struct containing variables accessed by shared code
3282
*****************************************************************************/
3284
e1000_spi_eeprom_ready(struct e1000_hw *hw)
3286
uint16_t retry_count = 0;
3287
uint8_t spi_stat_reg;
3289
DEBUGFUNC("e1000_spi_eeprom_ready");
3291
/* Read "Status Register" repeatedly until the LSB is cleared. The
3292
* EEPROM will signal that the command has been completed by clearing
3293
* bit 0 of the internal status register. If it's not cleared within
3294
* 5 milliseconds, then error out.
3298
e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3299
hw->eeprom.opcode_bits);
3300
spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3301
if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3307
} while(retry_count < EEPROM_MAX_RETRY_SPI);
3309
/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3310
* only 0-5mSec on 5V devices)
3312
if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3313
DEBUGOUT("SPI EEPROM Status error\n");
3314
return -E1000_ERR_EEPROM;
3317
return E1000_SUCCESS;
3320
/******************************************************************************
3321
* Reads a 16 bit word from the EEPROM.
3323
* hw - Struct containing variables accessed by shared code
3324
* offset - offset of word in the EEPROM to read
3325
* data - word read from the EEPROM
3326
* words - number of words to read
3327
*****************************************************************************/
3329
e1000_read_eeprom(struct e1000_hw *hw,
3334
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3337
DEBUGFUNC("e1000_read_eeprom");
3339
/* A check for invalid values: offset too large, too many words, and not
3342
if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3344
DEBUGOUT("\"words\" parameter out of bounds\n");
3345
return -E1000_ERR_EEPROM;
3348
/* Prepare the EEPROM for reading */
3349
if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3350
return -E1000_ERR_EEPROM;
3352
if(eeprom->type == e1000_eeprom_spi) {
3354
uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3356
if(e1000_spi_eeprom_ready(hw)) {
3357
e1000_release_eeprom(hw);
3358
return -E1000_ERR_EEPROM;
3361
e1000_standby_eeprom(hw);
3363
/* Some SPI eeproms use the 8th address bit embedded in the opcode */
3364
if((eeprom->address_bits == 8) && (offset >= 128))
3365
read_opcode |= EEPROM_A8_OPCODE_SPI;
3367
/* Send the READ command (opcode + addr) */
3368
e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3369
e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3371
/* Read the data. The address of the eeprom internally increments with
3372
* each byte (spi) being read, saving on the overhead of eeprom setup
3373
* and tear-down. The address counter will roll over if reading beyond
3374
* the size of the eeprom, thus allowing the entire memory to be read
3375
* starting from any offset. */
3376
for (i = 0; i < words; i++) {
3377
word_in = e1000_shift_in_ee_bits(hw, 16);
3378
data[i] = (word_in >> 8) | (word_in << 8);
3380
} else if(eeprom->type == e1000_eeprom_microwire) {
3381
for (i = 0; i < words; i++) {
3382
/* Send the READ command (opcode + addr) */
3383
e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3384
eeprom->opcode_bits);
3385
e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3386
eeprom->address_bits);
3388
/* Read the data. For microwire, each word requires the overhead
3389
* of eeprom setup and tear-down. */
3390
data[i] = e1000_shift_in_ee_bits(hw, 16);
3391
e1000_standby_eeprom(hw);
3395
/* End this read operation */
3396
e1000_release_eeprom(hw);
3398
return E1000_SUCCESS;
3401
/******************************************************************************
3402
* Verifies that the EEPROM has a valid checksum
3404
* hw - Struct containing variables accessed by shared code
3406
* Reads the first 64 16 bit words of the EEPROM and sums the values read.
3407
* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3409
*****************************************************************************/
3411
e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3413
uint16_t checksum = 0;
3414
uint16_t i, eeprom_data;
3416
DEBUGFUNC("e1000_validate_eeprom_checksum");
3418
for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3419
if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3420
DEBUGOUT("EEPROM Read Error\n");
3421
return -E1000_ERR_EEPROM;
3423
checksum += eeprom_data;
3426
if(checksum == (uint16_t) EEPROM_SUM)
3427
return E1000_SUCCESS;
3429
DEBUGOUT("EEPROM Checksum Invalid\n");
3430
return -E1000_ERR_EEPROM;
3434
/******************************************************************************
3435
* Calculates the EEPROM checksum and writes it to the EEPROM
3437
* hw - Struct containing variables accessed by shared code
3439
* Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3440
* Writes the difference to word offset 63 of the EEPROM.
3441
*****************************************************************************/
3443
e1000_update_eeprom_checksum(struct e1000_hw *hw)
3445
uint16_t checksum = 0;
3446
uint16_t i, eeprom_data;
3448
DEBUGFUNC("e1000_update_eeprom_checksum");
3450
for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3451
if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3452
DEBUGOUT("EEPROM Read Error\n");
3453
return -E1000_ERR_EEPROM;
3455
checksum += eeprom_data;
3457
checksum = (uint16_t) EEPROM_SUM - checksum;
3458
if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3459
DEBUGOUT("EEPROM Write Error\n");
3460
return -E1000_ERR_EEPROM;
3462
return E1000_SUCCESS;
3465
/******************************************************************************
3466
* Parent function for writing words to the different EEPROM types.
3468
* hw - Struct containing variables accessed by shared code
3469
* offset - offset within the EEPROM to be written to
3470
* words - number of words to write
3471
* data - 16 bit word to be written to the EEPROM
3473
* If e1000_update_eeprom_checksum is not called after this function, the
3474
* EEPROM will most likely contain an invalid checksum.
3475
*****************************************************************************/
3477
e1000_write_eeprom(struct e1000_hw *hw,
3482
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3485
DEBUGFUNC("e1000_write_eeprom");
3487
/* A check for invalid values: offset too large, too many words, and not
3490
if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3492
DEBUGOUT("\"words\" parameter out of bounds\n");
3493
return -E1000_ERR_EEPROM;
3496
/* Prepare the EEPROM for writing */
3497
if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3498
return -E1000_ERR_EEPROM;
3500
if(eeprom->type == e1000_eeprom_microwire)
3501
status = e1000_write_eeprom_microwire(hw, offset, words, data);
3503
status = e1000_write_eeprom_spi(hw, offset, words, data);
3505
/* Done with writing */
3506
e1000_release_eeprom(hw);
3511
/******************************************************************************
3512
* Writes a 16 bit word to a given offset in an SPI EEPROM.
3514
* hw - Struct containing variables accessed by shared code
3515
* offset - offset within the EEPROM to be written to
3516
* words - number of words to write
3517
* data - pointer to array of 8 bit words to be written to the EEPROM
3519
*****************************************************************************/
3521
e1000_write_eeprom_spi(struct e1000_hw *hw,
3526
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3529
DEBUGFUNC("e1000_write_eeprom_spi");
3531
while (widx < words) {
3532
uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3534
if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3536
e1000_standby_eeprom(hw);
3538
/* Send the WRITE ENABLE command (8 bit opcode ) */
3539
e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3540
eeprom->opcode_bits);
3542
e1000_standby_eeprom(hw);
3544
/* Some SPI eeproms use the 8th address bit embedded in the opcode */
3545
if((eeprom->address_bits == 8) && (offset >= 128))
3546
write_opcode |= EEPROM_A8_OPCODE_SPI;
3548
/* Send the Write command (8-bit opcode + addr) */
3549
e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3551
e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3552
eeprom->address_bits);
3556
/* Loop to allow for up to whole page write (32 bytes) of eeprom */
3557
while (widx < words) {
3558
uint16_t word_out = data[widx];
3559
word_out = (word_out >> 8) | (word_out << 8);
3560
e1000_shift_out_ee_bits(hw, word_out, 16);
3563
/* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3564
* operation, while the smaller eeproms are capable of an 8-byte
3565
* PAGE WRITE operation. Break the inner loop to pass new address
3567
if((((offset + widx)*2) % eeprom->page_size) == 0) {
3568
e1000_standby_eeprom(hw);
3574
return E1000_SUCCESS;
3577
/******************************************************************************
3578
* Writes a 16 bit word to a given offset in a Microwire EEPROM.
3580
* hw - Struct containing variables accessed by shared code
3581
* offset - offset within the EEPROM to be written to
3582
* words - number of words to write
3583
* data - pointer to array of 16 bit words to be written to the EEPROM
3585
*****************************************************************************/
3587
e1000_write_eeprom_microwire(struct e1000_hw *hw,
3592
struct e1000_eeprom_info *eeprom = &hw->eeprom;
3594
uint16_t words_written = 0;
3597
DEBUGFUNC("e1000_write_eeprom_microwire");
3599
/* Send the write enable command to the EEPROM (3-bit opcode plus
3600
* 6/8-bit dummy address beginning with 11). It's less work to include
3601
* the 11 of the dummy address as part of the opcode than it is to shift
3602
* it over the correct number of bits for the address. This puts the
3603
* EEPROM into write/erase mode.
3605
e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3606
(uint16_t)(eeprom->opcode_bits + 2));
3608
e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3610
/* Prepare the EEPROM */
3611
e1000_standby_eeprom(hw);
3613
while (words_written < words) {
3614
/* Send the Write command (3-bit opcode + addr) */
3615
e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3616
eeprom->opcode_bits);
3618
e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3619
eeprom->address_bits);
3622
e1000_shift_out_ee_bits(hw, data[words_written], 16);
3624
/* Toggle the CS line. This in effect tells the EEPROM to execute
3625
* the previous command.
3627
e1000_standby_eeprom(hw);
3629
/* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3630
* signal that the command has been completed by raising the DO signal.
3631
* If DO does not go high in 10 milliseconds, then error out.
3633
for(i = 0; i < 200; i++) {
3634
eecd = E1000_READ_REG(hw, EECD);
3635
if(eecd & E1000_EECD_DO) break;
3639
DEBUGOUT("EEPROM Write did not complete\n");
3640
return -E1000_ERR_EEPROM;
3643
/* Recover from write */
3644
e1000_standby_eeprom(hw);
3649
/* Send the write disable command to the EEPROM (3-bit opcode plus
3650
* 6/8-bit dummy address beginning with 10). It's less work to include
3651
* the 10 of the dummy address as part of the opcode than it is to shift
3652
* it over the correct number of bits for the address. This takes the
3653
* EEPROM out of write/erase mode.
3655
e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3656
(uint16_t)(eeprom->opcode_bits + 2));
3658
e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3660
return E1000_SUCCESS;
3663
/******************************************************************************
3664
* Reads the adapter's part number from the EEPROM
3666
* hw - Struct containing variables accessed by shared code
3667
* part_num - Adapter's part number
3668
*****************************************************************************/
3670
e1000_read_part_num(struct e1000_hw *hw,
3673
uint16_t offset = EEPROM_PBA_BYTE_1;
3674
uint16_t eeprom_data;
3676
DEBUGFUNC("e1000_read_part_num");
3678
/* Get word 0 from EEPROM */
3679
if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3680
DEBUGOUT("EEPROM Read Error\n");
3681
return -E1000_ERR_EEPROM;
3683
/* Save word 0 in upper half of part_num */
3684
*part_num = (uint32_t) (eeprom_data << 16);
3686
/* Get word 1 from EEPROM */
3687
if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3688
DEBUGOUT("EEPROM Read Error\n");
3689
return -E1000_ERR_EEPROM;
3691
/* Save word 1 in lower half of part_num */
3692
*part_num |= eeprom_data;
3694
return E1000_SUCCESS;
3697
/******************************************************************************
3698
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3699
* second function of dual function devices
3701
* hw - Struct containing variables accessed by shared code
3702
*****************************************************************************/
3704
e1000_read_mac_addr(struct e1000_hw * hw)
3707
uint16_t eeprom_data, i;
3709
DEBUGFUNC("e1000_read_mac_addr");
3711
for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3713
if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3714
DEBUGOUT("EEPROM Read Error\n");
3715
return -E1000_ERR_EEPROM;
3717
hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3718
hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3720
if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3721
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3722
if(hw->perm_mac_addr[5] & 0x01)
3723
hw->perm_mac_addr[5] &= ~(0x01);
3725
hw->perm_mac_addr[5] |= 0x01;
3727
for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3728
hw->mac_addr[i] = hw->perm_mac_addr[i];
3729
return E1000_SUCCESS;
3732
/******************************************************************************
3733
* Initializes receive address filters.
3735
* hw - Struct containing variables accessed by shared code
3737
* Places the MAC address in receive address register 0 and clears the rest
3738
* of the receive addresss registers. Clears the multicast table. Assumes
3739
* the receiver is in reset when the routine is called.
3740
*****************************************************************************/
3742
e1000_init_rx_addrs(struct e1000_hw *hw)
3748
DEBUGFUNC("e1000_init_rx_addrs");
3750
/* Setup the receive address. */
3751
DEBUGOUT("Programming MAC Address into RAR[0]\n");
3752
addr_low = (hw->mac_addr[0] |
3753
(hw->mac_addr[1] << 8) |
3754
(hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3756
addr_high = (hw->mac_addr[4] |
3757
(hw->mac_addr[5] << 8) | E1000_RAH_AV);
3759
E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3760
E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3762
/* Zero out the other 15 receive addresses. */
3763
DEBUGOUT("Clearing RAR[1-15]\n");
3764
for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3765
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3766
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3770
/******************************************************************************
3771
* Updates the MAC's list of multicast addresses.
3773
* hw - Struct containing variables accessed by shared code
3774
* mc_addr_list - the list of new multicast addresses
3775
* mc_addr_count - number of addresses
3776
* pad - number of bytes between addresses in the list
3778
* The given list replaces any existing list. Clears the last 15 receive
3779
* address registers and the multicast table. Uses receive address registers
3780
* for the first 15 multicast addresses, and hashes the rest into the
3782
*****************************************************************************/
3784
e1000_mc_addr_list_update(struct e1000_hw *hw,
3785
uint8_t *mc_addr_list,
3786
uint32_t mc_addr_count,
3789
uint32_t hash_value;
3791
uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
3793
DEBUGFUNC("e1000_mc_addr_list_update");
3795
/* Set the new number of MC addresses that we are being requested to use. */
3796
hw->num_mc_addrs = mc_addr_count;
3798
/* Clear RAR[1-15] */
3799
DEBUGOUT(" Clearing RAR[1-15]\n");
3800
for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3801
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3802
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3806
DEBUGOUT(" Clearing MTA\n");
3807
for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3808
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3811
/* Add the new addresses */
3812
for(i = 0; i < mc_addr_count; i++) {
3813
DEBUGOUT(" Adding the multicast addresses:\n");
3814
DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3815
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3816
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3817
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3818
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3819
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3820
mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3822
hash_value = e1000_hash_mc_addr(hw,
3824
(i * (ETH_LENGTH_OF_ADDRESS + pad)));
3826
DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3828
/* Place this multicast address in the RAR if there is room, *
3829
* else put it in the MTA
3831
if(rar_used_count < E1000_RAR_ENTRIES) {
3833
mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3837
e1000_mta_set(hw, hash_value);
3840
DEBUGOUT("MC Update Complete\n");
3843
/******************************************************************************
3844
* Hashes an address to determine its location in the multicast table
3846
* hw - Struct containing variables accessed by shared code
3847
* mc_addr - the multicast address to hash
3848
*****************************************************************************/
3850
e1000_hash_mc_addr(struct e1000_hw *hw,
3853
uint32_t hash_value = 0;
3855
/* The portion of the address that is used for the hash table is
3856
* determined by the mc_filter_type setting.
3858
switch (hw->mc_filter_type) {
3859
/* [0] [1] [2] [3] [4] [5]
3864
/* [47:36] i.e. 0x563 for above example address */
3865
hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3868
/* [46:35] i.e. 0xAC6 for above example address */
3869
hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3872
/* [45:34] i.e. 0x5D8 for above example address */
3873
hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3876
/* [43:32] i.e. 0x634 for above example address */
3877
hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3881
hash_value &= 0xFFF;
3885
/******************************************************************************
3886
* Sets the bit in the multicast table corresponding to the hash value.
3888
* hw - Struct containing variables accessed by shared code
3889
* hash_value - Multicast address hash value
3890
*****************************************************************************/
3892
e1000_mta_set(struct e1000_hw *hw,
3893
uint32_t hash_value)
3895
uint32_t hash_bit, hash_reg;
3899
/* The MTA is a register array of 128 32-bit registers.
3900
* It is treated like an array of 4096 bits. We want to set
3901
* bit BitArray[hash_value]. So we figure out what register
3902
* the bit is in, read it, OR in the new bit, then write
3903
* back the new value. The register is determined by the
3904
* upper 7 bits of the hash value and the bit within that
3905
* register are determined by the lower 5 bits of the value.
3907
hash_reg = (hash_value >> 5) & 0x7F;
3908
hash_bit = hash_value & 0x1F;
3910
mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3912
mta |= (1 << hash_bit);
3914
/* If we are on an 82544 and we are trying to write an odd offset
3915
* in the MTA, save off the previous entry before writing and
3916
* restore the old value after writing.
3918
if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
3919
temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
3920
E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3921
E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
3923
E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3927
/******************************************************************************
3928
* Puts an ethernet address into a receive address register.
3930
* hw - Struct containing variables accessed by shared code
3931
* addr - Address to put into receive address register
3932
* index - Receive address register to write
3933
*****************************************************************************/
3935
e1000_rar_set(struct e1000_hw *hw,
3939
uint32_t rar_low, rar_high;
3941
/* HW expects these in little endian so we reverse the byte order
3942
* from network order (big endian) to little endian
3944
rar_low = ((uint32_t) addr[0] |
3945
((uint32_t) addr[1] << 8) |
3946
((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
3948
rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
3950
E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
3951
E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
3954
/******************************************************************************
3955
* Writes a value to the specified offset in the VLAN filter table.
3957
* hw - Struct containing variables accessed by shared code
3958
* offset - Offset in VLAN filer table to write
3959
* value - Value to write into VLAN filter table
3960
*****************************************************************************/
3962
e1000_write_vfta(struct e1000_hw *hw,
3968
if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
3969
temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
3970
E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3971
E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
3973
E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3977
/******************************************************************************
3978
* Clears the VLAN filer table
3980
* hw - Struct containing variables accessed by shared code
3981
*****************************************************************************/
3983
e1000_clear_vfta(struct e1000_hw *hw)
3987
for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3988
E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3992
e1000_id_led_init(struct e1000_hw * hw)
3995
const uint32_t ledctl_mask = 0x000000FF;
3996
const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
3997
const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
3998
uint16_t eeprom_data, i, temp;
3999
const uint16_t led_mask = 0x0F;
4001
DEBUGFUNC("e1000_id_led_init");
4003
if(hw->mac_type < e1000_82540) {
4005
return E1000_SUCCESS;
4008
ledctl = E1000_READ_REG(hw, LEDCTL);
4009
hw->ledctl_default = ledctl;
4010
hw->ledctl_mode1 = hw->ledctl_default;
4011
hw->ledctl_mode2 = hw->ledctl_default;
4013
if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4014
DEBUGOUT("EEPROM Read Error\n");
4015
return -E1000_ERR_EEPROM;
4017
if((eeprom_data== ID_LED_RESERVED_0000) ||
4018
(eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4019
for(i = 0; i < 4; i++) {
4020
temp = (eeprom_data >> (i << 2)) & led_mask;
4022
case ID_LED_ON1_DEF2:
4023
case ID_LED_ON1_ON2:
4024
case ID_LED_ON1_OFF2:
4025
hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4026
hw->ledctl_mode1 |= ledctl_on << (i << 3);
4028
case ID_LED_OFF1_DEF2:
4029
case ID_LED_OFF1_ON2:
4030
case ID_LED_OFF1_OFF2:
4031
hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4032
hw->ledctl_mode1 |= ledctl_off << (i << 3);
4039
case ID_LED_DEF1_ON2:
4040
case ID_LED_ON1_ON2:
4041
case ID_LED_OFF1_ON2:
4042
hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4043
hw->ledctl_mode2 |= ledctl_on << (i << 3);
4045
case ID_LED_DEF1_OFF2:
4046
case ID_LED_ON1_OFF2:
4047
case ID_LED_OFF1_OFF2:
4048
hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4049
hw->ledctl_mode2 |= ledctl_off << (i << 3);
4056
return E1000_SUCCESS;
4059
/******************************************************************************
4060
* Prepares SW controlable LED for use and saves the current state of the LED.
4062
* hw - Struct containing variables accessed by shared code
4063
*****************************************************************************/
4065
e1000_setup_led(struct e1000_hw *hw)
4068
int32_t ret_val = E1000_SUCCESS;
4070
DEBUGFUNC("e1000_setup_led");
4072
switch(hw->mac_type) {
4073
case e1000_82542_rev2_0:
4074
case e1000_82542_rev2_1:
4077
/* No setup necessary */
4081
case e1000_82541_rev_2:
4082
case e1000_82547_rev_2:
4083
/* Turn off PHY Smart Power Down (if enabled) */
4084
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4085
&hw->phy_spd_default)))
4087
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4088
(uint16_t)(hw->phy_spd_default &
4089
~IGP01E1000_GMII_SPD))))
4093
if(hw->media_type == e1000_media_type_fiber) {
4094
ledctl = E1000_READ_REG(hw, LEDCTL);
4095
/* Save current LEDCTL settings */
4096
hw->ledctl_default = ledctl;
4098
ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4099
E1000_LEDCTL_LED0_BLINK |
4100
E1000_LEDCTL_LED0_MODE_MASK);
4101
ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4102
E1000_LEDCTL_LED0_MODE_SHIFT);
4103
E1000_WRITE_REG(hw, LEDCTL, ledctl);
4104
} else if(hw->media_type == e1000_media_type_copper)
4105
E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4109
return E1000_SUCCESS;
4112
/******************************************************************************
4113
* Restores the saved state of the SW controlable LED.
4115
* hw - Struct containing variables accessed by shared code
4116
*****************************************************************************/
4118
e1000_cleanup_led(struct e1000_hw *hw)
4120
int32_t ret_val = E1000_SUCCESS;
4122
DEBUGFUNC("e1000_cleanup_led");
4124
switch(hw->mac_type) {
4125
case e1000_82542_rev2_0:
4126
case e1000_82542_rev2_1:
4129
/* No cleanup necessary */
4133
case e1000_82541_rev_2:
4134
case e1000_82547_rev_2:
4135
/* Turn on PHY Smart Power Down (if previously enabled) */
4136
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4137
hw->phy_spd_default)))
4141
/* Restore LEDCTL settings */
4142
E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4146
return E1000_SUCCESS;
4149
/******************************************************************************
4150
* Turns on the software controllable LED
4152
* hw - Struct containing variables accessed by shared code
4153
*****************************************************************************/
4155
e1000_led_on(struct e1000_hw *hw)
4157
uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4159
DEBUGFUNC("e1000_led_on");
4161
switch(hw->mac_type) {
4162
case e1000_82542_rev2_0:
4163
case e1000_82542_rev2_1:
4165
/* Set SW Defineable Pin 0 to turn on the LED */
4166
ctrl |= E1000_CTRL_SWDPIN0;
4167
ctrl |= E1000_CTRL_SWDPIO0;
4170
if(hw->media_type == e1000_media_type_fiber) {
4171
/* Set SW Defineable Pin 0 to turn on the LED */
4172
ctrl |= E1000_CTRL_SWDPIN0;
4173
ctrl |= E1000_CTRL_SWDPIO0;
4175
/* Clear SW Defineable Pin 0 to turn on the LED */
4176
ctrl &= ~E1000_CTRL_SWDPIN0;
4177
ctrl |= E1000_CTRL_SWDPIO0;
4181
if(hw->media_type == e1000_media_type_fiber) {
4182
/* Clear SW Defineable Pin 0 to turn on the LED */
4183
ctrl &= ~E1000_CTRL_SWDPIN0;
4184
ctrl |= E1000_CTRL_SWDPIO0;
4185
} else if(hw->media_type == e1000_media_type_copper) {
4186
E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4187
return E1000_SUCCESS;
4192
E1000_WRITE_REG(hw, CTRL, ctrl);
4194
return E1000_SUCCESS;
4197
/******************************************************************************
4198
* Turns off the software controllable LED
4200
* hw - Struct containing variables accessed by shared code
4201
*****************************************************************************/
4203
e1000_led_off(struct e1000_hw *hw)
4205
uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4207
DEBUGFUNC("e1000_led_off");
4209
switch(hw->mac_type) {
4210
case e1000_82542_rev2_0:
4211
case e1000_82542_rev2_1:
4213
/* Clear SW Defineable Pin 0 to turn off the LED */
4214
ctrl &= ~E1000_CTRL_SWDPIN0;
4215
ctrl |= E1000_CTRL_SWDPIO0;
4218
if(hw->media_type == e1000_media_type_fiber) {
4219
/* Clear SW Defineable Pin 0 to turn off the LED */
4220
ctrl &= ~E1000_CTRL_SWDPIN0;
4221
ctrl |= E1000_CTRL_SWDPIO0;
4223
/* Set SW Defineable Pin 0 to turn off the LED */
4224
ctrl |= E1000_CTRL_SWDPIN0;
4225
ctrl |= E1000_CTRL_SWDPIO0;
4229
if(hw->media_type == e1000_media_type_fiber) {
4230
/* Set SW Defineable Pin 0 to turn off the LED */
4231
ctrl |= E1000_CTRL_SWDPIN0;
4232
ctrl |= E1000_CTRL_SWDPIO0;
4233
} else if(hw->media_type == e1000_media_type_copper) {
4234
E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4235
return E1000_SUCCESS;
4240
E1000_WRITE_REG(hw, CTRL, ctrl);
4242
return E1000_SUCCESS;
4245
/******************************************************************************
4246
* Clears all hardware statistics counters.
4248
* hw - Struct containing variables accessed by shared code
4249
*****************************************************************************/
4251
e1000_clear_hw_cntrs(struct e1000_hw *hw)
4253
volatile uint32_t temp;
4255
temp = E1000_READ_REG(hw, CRCERRS);
4256
temp = E1000_READ_REG(hw, SYMERRS);
4257
temp = E1000_READ_REG(hw, MPC);
4258
temp = E1000_READ_REG(hw, SCC);
4259
temp = E1000_READ_REG(hw, ECOL);
4260
temp = E1000_READ_REG(hw, MCC);
4261
temp = E1000_READ_REG(hw, LATECOL);
4262
temp = E1000_READ_REG(hw, COLC);
4263
temp = E1000_READ_REG(hw, DC);
4264
temp = E1000_READ_REG(hw, SEC);
4265
temp = E1000_READ_REG(hw, RLEC);
4266
temp = E1000_READ_REG(hw, XONRXC);
4267
temp = E1000_READ_REG(hw, XONTXC);
4268
temp = E1000_READ_REG(hw, XOFFRXC);
4269
temp = E1000_READ_REG(hw, XOFFTXC);
4270
temp = E1000_READ_REG(hw, FCRUC);
4271
temp = E1000_READ_REG(hw, PRC64);
4272
temp = E1000_READ_REG(hw, PRC127);
4273
temp = E1000_READ_REG(hw, PRC255);
4274
temp = E1000_READ_REG(hw, PRC511);
4275
temp = E1000_READ_REG(hw, PRC1023);
4276
temp = E1000_READ_REG(hw, PRC1522);
4277
temp = E1000_READ_REG(hw, GPRC);
4278
temp = E1000_READ_REG(hw, BPRC);
4279
temp = E1000_READ_REG(hw, MPRC);
4280
temp = E1000_READ_REG(hw, GPTC);
4281
temp = E1000_READ_REG(hw, GORCL);
4282
temp = E1000_READ_REG(hw, GORCH);
4283
temp = E1000_READ_REG(hw, GOTCL);
4284
temp = E1000_READ_REG(hw, GOTCH);
4285
temp = E1000_READ_REG(hw, RNBC);
4286
temp = E1000_READ_REG(hw, RUC);
4287
temp = E1000_READ_REG(hw, RFC);
4288
temp = E1000_READ_REG(hw, ROC);
4289
temp = E1000_READ_REG(hw, RJC);
4290
temp = E1000_READ_REG(hw, TORL);
4291
temp = E1000_READ_REG(hw, TORH);
4292
temp = E1000_READ_REG(hw, TOTL);
4293
temp = E1000_READ_REG(hw, TOTH);
4294
temp = E1000_READ_REG(hw, TPR);
4295
temp = E1000_READ_REG(hw, TPT);
4296
temp = E1000_READ_REG(hw, PTC64);
4297
temp = E1000_READ_REG(hw, PTC127);
4298
temp = E1000_READ_REG(hw, PTC255);
4299
temp = E1000_READ_REG(hw, PTC511);
4300
temp = E1000_READ_REG(hw, PTC1023);
4301
temp = E1000_READ_REG(hw, PTC1522);
4302
temp = E1000_READ_REG(hw, MPTC);
4303
temp = E1000_READ_REG(hw, BPTC);
4305
if(hw->mac_type < e1000_82543) return;
4307
temp = E1000_READ_REG(hw, ALGNERRC);
4308
temp = E1000_READ_REG(hw, RXERRC);
4309
temp = E1000_READ_REG(hw, TNCRS);
4310
temp = E1000_READ_REG(hw, CEXTERR);
4311
temp = E1000_READ_REG(hw, TSCTC);
4312
temp = E1000_READ_REG(hw, TSCTFC);
4314
if(hw->mac_type <= e1000_82544) return;
4316
temp = E1000_READ_REG(hw, MGTPRC);
4317
temp = E1000_READ_REG(hw, MGTPDC);
4318
temp = E1000_READ_REG(hw, MGTPTC);
4321
/******************************************************************************
4322
* Resets Adaptive IFS to its default state.
4324
* hw - Struct containing variables accessed by shared code
4326
* Call this after e1000_init_hw. You may override the IFS defaults by setting
4327
* hw->ifs_params_forced to TRUE. However, you must initialize hw->
4328
* current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4329
* before calling this function.
4330
*****************************************************************************/
4332
e1000_reset_adaptive(struct e1000_hw *hw)
4334
DEBUGFUNC("e1000_reset_adaptive");
4336
if(hw->adaptive_ifs) {
4337
if(!hw->ifs_params_forced) {
4338
hw->current_ifs_val = 0;
4339
hw->ifs_min_val = IFS_MIN;
4340
hw->ifs_max_val = IFS_MAX;
4341
hw->ifs_step_size = IFS_STEP;
4342
hw->ifs_ratio = IFS_RATIO;
4344
hw->in_ifs_mode = FALSE;
4345
E1000_WRITE_REG(hw, AIT, 0);
4347
DEBUGOUT("Not in Adaptive IFS mode!\n");
4351
/******************************************************************************
4352
* Called during the callback/watchdog routine to update IFS value based on
4353
* the ratio of transmits to collisions.
4355
* hw - Struct containing variables accessed by shared code
4356
* tx_packets - Number of transmits since last callback
4357
* total_collisions - Number of collisions since last callback
4358
*****************************************************************************/
4360
e1000_update_adaptive(struct e1000_hw *hw)
4362
DEBUGFUNC("e1000_update_adaptive");
4364
if(hw->adaptive_ifs) {
4365
if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4366
if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4367
hw->in_ifs_mode = TRUE;
4368
if(hw->current_ifs_val < hw->ifs_max_val) {
4369
if(hw->current_ifs_val == 0)
4370
hw->current_ifs_val = hw->ifs_min_val;
4372
hw->current_ifs_val += hw->ifs_step_size;
4373
E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4377
if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4378
hw->current_ifs_val = 0;
4379
hw->in_ifs_mode = FALSE;
4380
E1000_WRITE_REG(hw, AIT, 0);
4384
DEBUGOUT("Not in Adaptive IFS mode!\n");
4388
/******************************************************************************
4389
* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4391
* hw - Struct containing variables accessed by shared code
4392
* frame_len - The length of the frame in question
4393
* mac_addr - The Ethernet destination address of the frame in question
4394
*****************************************************************************/
4396
e1000_tbi_adjust_stats(struct e1000_hw *hw,
4397
struct e1000_hw_stats *stats,
4403
/* First adjust the frame length. */
4405
/* We need to adjust the statistics counters, since the hardware
4406
* counters overcount this packet as a CRC error and undercount
4407
* the packet as a good packet
4409
/* This packet should not be counted as a CRC error. */
4411
/* This packet does count as a Good Packet Received. */
4414
/* Adjust the Good Octets received counters */
4415
carry_bit = 0x80000000 & stats->gorcl;
4416
stats->gorcl += frame_len;
4417
/* If the high bit of Gorcl (the low 32 bits of the Good Octets
4418
* Received Count) was one before the addition,
4419
* AND it is zero after, then we lost the carry out,
4420
* need to add one to Gorch (Good Octets Received Count High).
4421
* This could be simplified if all environments supported
4424
if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4426
/* Is this a broadcast or multicast? Check broadcast first,
4427
* since the test for a multicast frame will test positive on
4428
* a broadcast frame.
4430
if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4431
/* Broadcast packet */
4433
else if(*mac_addr & 0x01)
4434
/* Multicast packet */
4437
if(frame_len == hw->max_frame_size) {
4438
/* In this case, the hardware has overcounted the number of
4445
/* Adjust the bin counters when the extra byte put the frame in the
4446
* wrong bin. Remember that the frame_len was adjusted above.
4448
if(frame_len == 64) {
4451
} else if(frame_len == 127) {
4454
} else if(frame_len == 255) {
4457
} else if(frame_len == 511) {
4460
} else if(frame_len == 1023) {
4463
} else if(frame_len == 1522) {
4468
/******************************************************************************
4469
* Gets the current PCI bus type, speed, and width of the hardware
4471
* hw - Struct containing variables accessed by shared code
4472
*****************************************************************************/
4474
e1000_get_bus_info(struct e1000_hw *hw)
4478
if(hw->mac_type < e1000_82543) {
4479
hw->bus_type = e1000_bus_type_unknown;
4480
hw->bus_speed = e1000_bus_speed_unknown;
4481
hw->bus_width = e1000_bus_width_unknown;
4485
status = E1000_READ_REG(hw, STATUS);
4486
hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4487
e1000_bus_type_pcix : e1000_bus_type_pci;
4489
if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4490
hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4491
e1000_bus_speed_66 : e1000_bus_speed_120;
4492
} else if(hw->bus_type == e1000_bus_type_pci) {
4493
hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4494
e1000_bus_speed_66 : e1000_bus_speed_33;
4496
switch (status & E1000_STATUS_PCIX_SPEED) {
4497
case E1000_STATUS_PCIX_SPEED_66:
4498
hw->bus_speed = e1000_bus_speed_66;
4500
case E1000_STATUS_PCIX_SPEED_100:
4501
hw->bus_speed = e1000_bus_speed_100;
4503
case E1000_STATUS_PCIX_SPEED_133:
4504
hw->bus_speed = e1000_bus_speed_133;
4507
hw->bus_speed = e1000_bus_speed_reserved;
4511
hw->bus_width = (status & E1000_STATUS_BUS64) ?
4512
e1000_bus_width_64 : e1000_bus_width_32;
4514
/******************************************************************************
4515
* Reads a value from one of the devices registers using port I/O (as opposed
4516
* memory mapped I/O). Only 82544 and newer devices support port I/O.
4518
* hw - Struct containing variables accessed by shared code
4519
* offset - offset to read from
4520
*****************************************************************************/
4522
e1000_read_reg_io(struct e1000_hw *hw,
4525
uint32_t io_addr = hw->io_base;
4526
uint32_t io_data = hw->io_base + 4;
4528
e1000_io_write(hw, io_addr, offset);
4529
return e1000_io_read(hw, io_data);
4532
/******************************************************************************
4533
* Writes a value to one of the devices registers using port I/O (as opposed to
4534
* memory mapped I/O). Only 82544 and newer devices support port I/O.
4536
* hw - Struct containing variables accessed by shared code
4537
* offset - offset to write to
4538
* value - value to write
4539
*****************************************************************************/
4541
e1000_write_reg_io(struct e1000_hw *hw,
4545
uint32_t io_addr = hw->io_base;
4546
uint32_t io_data = hw->io_base + 4;
4548
e1000_io_write(hw, io_addr, offset);
4549
e1000_io_write(hw, io_data, value);
4553
/******************************************************************************
4554
* Estimates the cable length.
4556
* hw - Struct containing variables accessed by shared code
4557
* min_length - The estimated minimum length
4558
* max_length - The estimated maximum length
4560
* returns: - E1000_ERR_XXX
4563
* This function always returns a ranged length (minimum & maximum).
4564
* So for M88 phy's, this function interprets the one value returned from the
4565
* register to the minimum and maximum range.
4566
* For IGP phy's, the function calculates the range by the AGC registers.
4567
*****************************************************************************/
4569
e1000_get_cable_length(struct e1000_hw *hw,
4570
uint16_t *min_length,
4571
uint16_t *max_length)
4574
uint16_t agc_value = 0;
4575
uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4576
uint16_t i, phy_data;
4578
DEBUGFUNC("e1000_get_cable_length");
4580
*min_length = *max_length = 0;
4582
/* Use old method for Phy older than IGP */
4583
if(hw->phy_type == e1000_phy_m88) {
4584
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4588
/* Convert the enum value to ranged values */
4589
switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4590
M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4591
case e1000_cable_length_50:
4593
*max_length = e1000_igp_cable_length_50;
4595
case e1000_cable_length_50_80:
4596
*min_length = e1000_igp_cable_length_50;
4597
*max_length = e1000_igp_cable_length_80;
4599
case e1000_cable_length_80_110:
4600
*min_length = e1000_igp_cable_length_80;
4601
*max_length = e1000_igp_cable_length_110;
4603
case e1000_cable_length_110_140:
4604
*min_length = e1000_igp_cable_length_110;
4605
*max_length = e1000_igp_cable_length_140;
4607
case e1000_cable_length_140:
4608
*min_length = e1000_igp_cable_length_140;
4609
*max_length = e1000_igp_cable_length_170;
4612
return -E1000_ERR_PHY;
4615
} else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4616
uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4617
{IGP01E1000_PHY_AGC_A,
4618
IGP01E1000_PHY_AGC_B,
4619
IGP01E1000_PHY_AGC_C,
4620
IGP01E1000_PHY_AGC_D};
4621
/* Read the AGC registers for all channels */
4622
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4624
if((ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
4627
cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4629
/* Array bound check. */
4630
if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4632
return -E1000_ERR_PHY;
4634
agc_value += cur_agc;
4636
/* Update minimal AGC value. */
4637
if(min_agc > cur_agc)
4641
/* Remove the minimal AGC result for length < 50m */
4642
if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4643
agc_value -= min_agc;
4645
/* Get the average length of the remaining 3 channels */
4646
agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4648
/* Get the average length of all the 4 channels. */
4649
agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4652
/* Set the range of the calculated length. */
4653
*min_length = ((e1000_igp_cable_length_table[agc_value] -
4654
IGP01E1000_AGC_RANGE) > 0) ?
4655
(e1000_igp_cable_length_table[agc_value] -
4656
IGP01E1000_AGC_RANGE) : 0;
4657
*max_length = e1000_igp_cable_length_table[agc_value] +
4658
IGP01E1000_AGC_RANGE;
4661
return E1000_SUCCESS;
4664
/******************************************************************************
4665
* Check the cable polarity
4667
* hw - Struct containing variables accessed by shared code
4668
* polarity - output parameter : 0 - Polarity is not reversed
4669
* 1 - Polarity is reversed.
4671
* returns: - E1000_ERR_XXX
4674
* For phy's older then IGP, this function simply reads the polarity bit in the
4675
* Phy Status register. For IGP phy's, this bit is valid only if link speed is
4676
* 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4677
* return 0. If the link speed is 1000 Mbps the polarity status is in the
4678
* IGP01E1000_PHY_PCS_INIT_REG.
4679
*****************************************************************************/
4681
e1000_check_polarity(struct e1000_hw *hw,
4687
DEBUGFUNC("e1000_check_polarity");
4689
if(hw->phy_type == e1000_phy_m88) {
4690
/* return the Polarity bit in the Status register. */
4691
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4694
*polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4695
M88E1000_PSSR_REV_POLARITY_SHIFT;
4696
} else if(hw->phy_type == e1000_phy_igp) {
4697
/* Read the Status register to check the speed */
4698
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4702
/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4703
* find the polarity status */
4704
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4705
IGP01E1000_PSSR_SPEED_1000MBPS) {
4707
/* Read the GIG initialization PCS register (0x00B4) */
4708
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4712
/* Check the polarity bits */
4713
*polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4715
/* For 10 Mbps, read the polarity bit in the status register. (for
4716
* 100 Mbps this bit is always 0) */
4717
*polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4720
return E1000_SUCCESS;
4723
/******************************************************************************
4724
* Check if Downshift occured
4726
* hw - Struct containing variables accessed by shared code
4727
* downshift - output parameter : 0 - No Downshift ocured.
4728
* 1 - Downshift ocured.
4730
* returns: - E1000_ERR_XXX
4733
* For phy's older then IGP, this function reads the Downshift bit in the Phy
4734
* Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4735
* Link Health register. In IGP this bit is latched high, so the driver must
4736
* read it immediately after link is established.
4737
*****************************************************************************/
4739
e1000_check_downshift(struct e1000_hw *hw)
4744
DEBUGFUNC("e1000_check_downshift");
4746
if(hw->phy_type == e1000_phy_igp) {
4747
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4751
hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4753
else if(hw->phy_type == e1000_phy_m88) {
4754
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4758
hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4759
M88E1000_PSSR_DOWNSHIFT_SHIFT;
4761
return E1000_SUCCESS;
4764
/*****************************************************************************
4766
* 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4767
* gigabit link is achieved to improve link quality.
4769
* hw: Struct containing variables accessed by shared code
4771
* returns: - E1000_ERR_PHY if fail to read/write the PHY
4772
* E1000_SUCCESS at any other case.
4774
****************************************************************************/
4777
e1000_config_dsp_after_link_change(struct e1000_hw *hw,
4781
uint16_t phy_data, speed, duplex, i;
4782
uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4783
{IGP01E1000_PHY_AGC_PARAM_A,
4784
IGP01E1000_PHY_AGC_PARAM_B,
4785
IGP01E1000_PHY_AGC_PARAM_C,
4786
IGP01E1000_PHY_AGC_PARAM_D};
4787
uint16_t min_length, max_length;
4789
DEBUGFUNC("e1000_config_dsp_after_link_change");
4791
if(hw->phy_type != e1000_phy_igp)
4792
return E1000_SUCCESS;
4795
if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
4796
DEBUGOUT("Error getting link speed and duplex\n");
4800
if(speed == SPEED_1000) {
4802
e1000_get_cable_length(hw, &min_length, &max_length);
4804
if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
4805
min_length >= e1000_igp_cable_length_50) {
4807
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4808
if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4812
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4814
if((ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
4818
hw->dsp_config_state = e1000_dsp_config_activated;
4821
if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
4822
(min_length < e1000_igp_cable_length_50)) {
4824
uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
4825
uint32_t idle_errs = 0;
4827
/* clear previous idle error counts */
4828
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4832
for(i = 0; i < ffe_idle_err_timeout; i++) {
4834
if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4838
idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
4839
if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
4840
hw->ffe_config_state = e1000_ffe_config_active;
4842
if((ret_val = e1000_write_phy_reg(hw,
4843
IGP01E1000_PHY_DSP_FFE,
4844
IGP01E1000_PHY_DSP_FFE_CM_CP)))
4850
ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
4855
if(hw->dsp_config_state == e1000_dsp_config_activated) {
4856
if((ret_val = e1000_write_phy_reg(hw, 0x0000,
4857
IGP01E1000_IEEE_FORCE_GIGA)))
4859
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4860
if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4864
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4865
phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
4867
if((ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i],
4872
if((ret_val = e1000_write_phy_reg(hw, 0x0000,
4873
IGP01E1000_IEEE_RESTART_AUTONEG)))
4876
hw->dsp_config_state = e1000_dsp_config_enabled;
4879
if(hw->ffe_config_state == e1000_ffe_config_active) {
4880
if((ret_val = e1000_write_phy_reg(hw, 0x0000,
4881
IGP01E1000_IEEE_FORCE_GIGA)))
4883
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
4884
IGP01E1000_PHY_DSP_FFE_DEFAULT)))
4887
if((ret_val = e1000_write_phy_reg(hw, 0x0000,
4888
IGP01E1000_IEEE_RESTART_AUTONEG)))
4890
hw->ffe_config_state = e1000_ffe_config_enabled;
4893
return E1000_SUCCESS;
4896
/***************************************************************************
4898
* Workaround for the 82547 long TTL on noisy 100HD hubs.
4900
* This function, specific to 82547 hardware only, needs to be called every
4901
* second. It checks if a parallel detect fault has occurred. If a fault
4902
* occurred, disable/enable the DSP reset mechanism up to 5 times (once per
4903
* second). If link is established, stop the workaround and ensure the DSP
4906
* hw: Struct containing variables accessed by shared code
4908
* returns: - E1000_ERR_PHY if fail to read/write the PHY
4909
* E1000_SUCCESS in any other case
4911
****************************************************************************/
4913
e1000_igp_ttl_workaround(struct e1000_hw *hw)
4916
uint16_t phy_data = 0;
4917
uint16_t dsp_value = DSP_RESET_ENABLE;
4919
if(((hw->mac_type != e1000_82541) && (hw->mac_type != e1000_82547)) ||
4920
(!hw->ttl_wa_activation)) {
4921
return E1000_SUCCESS;
4924
/* Check for link first */
4925
if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
4928
if(phy_data & MII_SR_LINK_STATUS) {
4929
/* If link is established during the workaround, the DSP mechanism must
4931
if(hw->dsp_reset_counter) {
4932
hw->dsp_reset_counter = 0;
4933
dsp_value = DSP_RESET_ENABLE;
4935
return E1000_SUCCESS;
4937
if(hw->dsp_reset_counter == 0) {
4938
/* Workaround not activated, check if it needs activation */
4939
if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
4941
/* Activate the workaround if there was a parallel detect fault */
4942
if(phy_data & NWAY_ER_PAR_DETECT_FAULT)
4943
hw->dsp_reset_counter++;
4945
return E1000_SUCCESS;
4948
if(hw->dsp_reset_counter) {
4949
/* After 5 times, stop the workaround */
4950
if(hw->dsp_reset_counter > E1000_MAX_DSP_RESETS) {
4951
hw->dsp_reset_counter = 0;
4952
dsp_value = DSP_RESET_ENABLE;
4954
dsp_value = (hw->dsp_reset_counter & 1) ? DSP_RESET_DISABLE :
4956
hw->dsp_reset_counter++;
4961
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value)))
4964
return E1000_SUCCESS;
4967
/*****************************************************************************
4969
* This function sets the lplu state according to the active flag. When
4970
* activating lplu this function also disables smart speed and vise versa.
4971
* lplu will not be activated unless the device autonegotiation advertisment
4972
* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
4973
* hw: Struct containing variables accessed by shared code
4974
* active - true to enable lplu false to disable lplu.
4976
* returns: - E1000_ERR_PHY if fail to read/write the PHY
4977
* E1000_SUCCESS at any other case.
4979
****************************************************************************/
4982
e1000_set_d3_lplu_state(struct e1000_hw *hw,
4987
DEBUGFUNC("e1000_set_d3_lplu_state");
4989
if(!((hw->mac_type == e1000_82541_rev_2) ||
4990
(hw->mac_type == e1000_82547_rev_2)))
4991
return E1000_SUCCESS;
4993
/* During driver activity LPLU should not be used or it will attain link
4994
* from the lowest speeds starting from 10Mbps. The capability is used for
4995
* Dx transitions and states */
4996
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
5000
phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5001
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
5004
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5005
* Dx states where the power conservation is most important. During
5006
* driver activity we should enable SmartSpeed, so performance is
5008
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5012
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5013
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5017
} else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5018
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5019
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5021
phy_data |= IGP01E1000_GMII_FLEX_SPD;
5022
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
5025
/* When LPLU is enabled we should disable SmartSpeed */
5026
if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5030
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5031
if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5036
return E1000_SUCCESS;
5039
/******************************************************************************
5040
* Change VCO speed register to improve Bit Error Rate performance of SERDES.
5042
* hw - Struct containing variables accessed by shared code
5043
*****************************************************************************/
5045
e1000_set_vco_speed(struct e1000_hw *hw)
5048
uint16_t default_page = 0;
5051
DEBUGFUNC("e1000_set_vco_speed");
5053
switch(hw->mac_type) {
5054
case e1000_82545_rev_3:
5055
case e1000_82546_rev_3:
5058
return E1000_SUCCESS;
5061
/* Set PHY register 30, page 5, bit 8 to 0 */
5063
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5067
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
5070
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5073
phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5074
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5077
/* Set PHY register 30, page 4, bit 11 to 1 */
5079
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
5082
if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5085
phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5086
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5089
if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5093
return E1000_SUCCESS;
added
removed
xen/drivers/net/e1000/e1000_hw.c
