1
/******************************************************************************
4
* Interrupt distribution and delivery logic.
6
* Copyright (c) 2006, K A Fraser, XenSource Inc.
8
* This program is free software; you can redistribute it and/or modify it
9
* under the terms and conditions of the GNU General Public License,
10
* version 2, as published by the Free Software Foundation.
12
* This program is distributed in the hope it will be useful, but WITHOUT
13
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17
* You should have received a copy of the GNU General Public License along with
18
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19
* Place - Suite 330, Boston, MA 02111-1307 USA.
22
#ifndef __ASM_X86_HVM_IRQ_H__
23
#define __ASM_X86_HVM_IRQ_H__
25
#include <xen/hvm/irq.h>
26
#include <asm/hvm/hvm.h>
27
#include <asm/hvm/vpic.h>
28
#include <asm/hvm/vioapic.h>
32
* Virtual interrupt wires for a single PCI bus.
33
* Indexed by: device*4 + INTx#.
35
struct hvm_hw_pci_irqs pci_intx;
38
* Virtual interrupt wires for ISA devices.
39
* Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
41
struct hvm_hw_isa_irqs isa_irq;
44
* PCI-ISA interrupt router.
45
* Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
46
* the traditional 'barber's pole' mapping ((device + INTx#) & 3).
47
* The router provides a programmable mapping from each link to a GSI.
49
struct hvm_hw_pci_link pci_link;
51
/* Virtual interrupt and via-link for paravirtual platform driver. */
52
uint32_t callback_via_asserted;
57
HVMIRQ_callback_pci_intx
62
struct { uint8_t dev, intx; } pci;
65
/* Number of INTx wires asserting each PCI-ISA link. */
66
u8 pci_link_assert_count[4];
69
* Number of wires asserting each GSI.
71
* GSIs 0-15 are the ISA IRQs. ISA devices map directly into this space
72
* except ISA IRQ 0, which is connected to GSI 2.
73
* PCI links map into this space via the PCI-ISA bridge.
75
* GSIs 16+ are used only be PCI devices. The mapping from PCI device to
76
* GSI is as follows: ((device*4 + device/8 + INTx#) & 31) + 16
78
u8 gsi_assert_count[VIOAPIC_NUM_PINS];
81
* GSIs map onto PIC/IO-APIC in the usual way:
82
* 0-7: Master 8259 PIC, IO-APIC pins 0-7
83
* 8-15: Slave 8259 PIC, IO-APIC pins 8-15
84
* 16+ : IO-APIC pins 16+
87
/* Last VCPU that was delivered a LowestPrio interrupt. */
88
u8 round_robin_prev_vcpu;
90
struct hvm_irq_dpci *dpci;
93
#define hvm_pci_intx_gsi(dev, intx) \
94
(((((dev)<<2) + ((dev)>>3) + (intx)) & 31) + 16)
95
#define hvm_pci_intx_link(dev, intx) \
96
(((dev) + (intx)) & 3)
98
#define hvm_isa_irq_to_gsi(isa_irq) ((isa_irq) ? : 2)
100
/* Check/Acknowledge next pending interrupt. */
101
struct hvm_intack hvm_vcpu_has_pending_irq(struct vcpu *v);
102
struct hvm_intack hvm_vcpu_ack_pending_irq(struct vcpu *v,
103
struct hvm_intack intack);
106
* Currently IA64 Xen doesn't support MSI. So for x86, we define this macro
107
* to control the conditional compilation of some MSI-related functions.
108
* This macro will be removed once IA64 has MSI support.
110
#define SUPPORT_MSI_REMAPPING 1
112
#endif /* __ASM_X86_HVM_IRQ_H__ */