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* Athlon/Hammer specific Machine Check Exception Reporting
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* (C) Copyright 2002 Dave Jones <davej@codemonkey.org.uk>
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#include <xen/kernel.h>
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#include <xen/config.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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/* Machine Check Handler For AMD Athlon/Duron */
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static fastcall void k7_machine_check(struct cpu_user_regs * regs, long error_code)
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u32 alow, ahigh, high, low;
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rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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for (i=1; i<nr_mce_banks; i++) {
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rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
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printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
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rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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printk ("[%08x%08x]", ahigh, alow);
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rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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printk (" at %08x%08x", ahigh, alow);
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wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
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add_taint(TAINT_MACHINE_CHECK);
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mc_panic ("CPU context corrupt");
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mc_panic ("Unable to continue");
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printk (KERN_EMERG "Attempting to continue.\n");
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wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
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/* AMD K7 machine check */
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enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c)
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/* Check for PPro style MCA; our caller has confirmed MCE support. */
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if (!cpu_has(c, X86_FEATURE_MCA))
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x86_mce_vector_register(k7_machine_check);
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rdmsr (MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<8)) /* Control register present ? */
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wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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nr_mce_banks = l & 0xff;
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/* Clear status for MC index 0 separately, we don't touch CTL,
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* as some Athlons cause spurious MCEs when its enabled. */
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wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
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for (i=1; i<nr_mce_banks; i++) {
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wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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set_in_cr4 (X86_CR4_MCE);