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//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file implements the CriticalAntiDepBreaker class, which
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// implements register anti-dependence breaking along a blocks
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// critical path during post-RA scheduler.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "CriticalAntiDepBreaker.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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CriticalAntiDepBreaker::
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CriticalAntiDepBreaker(MachineFunction& MFi) :
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AntiDepBreaker(), MF(MFi),
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TII(MF.getTarget().getInstrInfo()),
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TRI(MF.getTarget().getRegisterInfo()),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
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KillIndices(TRI->getNumRegs(), 0),
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DefIndices(TRI->getNumRegs(), 0) {}
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CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
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void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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const unsigned BBSize = BB->size();
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for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
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// Clear out the register class data.
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Classes[i] = static_cast<const TargetRegisterClass *>(0);
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// Initialize the indices to indicate that no registers are live.
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DefIndices[i] = BBSize;
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// Clear "do not change" set.
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bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
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// Determine the live-out physregs for this block.
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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// In a non-return block, examine the live-in regs of all successors.
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// Note a return block can have successors if the return instruction is
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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// Mark live-out callee-saved registers. In a return block this is
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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void CriticalAntiDepBreaker::FinishBlock() {
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void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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unsigned InsertPosIndex) {
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if (MI->isDebugValue())
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assert(Count < InsertPosIndex && "Instruction index out of expected range!");
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// Any register which was defined within the previous scheduling region
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// may have been rescheduled and its lifetime may overlap with registers
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// in ways not reflected in our current liveness state. For each such
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// register, adjust the liveness state to be conservatively correct.
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for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
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if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
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assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
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// Mark this register to be non-renamable.
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// Move the def index to the end of the previous region, to reflect
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// that the def could theoretically have been scheduled at the end.
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DefIndices[Reg] = InsertPosIndex;
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PrescanInstruction(MI);
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ScanInstruction(MI, Count);
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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static const SDep *CriticalPathStep(const SUnit *SU) {
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const SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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const SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
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// It's not safe to change register allocation for source operands of
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// that have special allocation requirements. Also assume all registers
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// used in a call must not be changed (ABI).
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// FIXME: The issue with predicated instruction is more complex. We are being
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// conservatively here because the kill markers cannot be trusted after
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// %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
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// STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
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// %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
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// STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
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// The first R6 kill is not really a kill since it's killed by a predicated
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// instruction which may not be executed. The second R6 def may or may not
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// re-define R6 so it's not safe to change it since the last R6 use cannot be
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bool Special = MI->getDesc().isCall() ||
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MI->getDesc().hasExtraSrcRegAllocReq() ||
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TII->isPredicated(MI);
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// Scan the register operands for this instruction and update
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// Classes and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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if (!Classes[Reg] && NewRC)
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Classes[Reg] = NewRC;
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else if (!NewRC || Classes[Reg] != NewRC)
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// Now check for aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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// If an alias of the reg is used during the live range, give up.
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// Note that this allows us to skip checking if AntiDepReg
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// overlaps with any of the aliases, among other things.
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unsigned AliasReg = *Alias;
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if (Classes[AliasReg]) {
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// If we're still willing to consider this register, note the reference.
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if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
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RegRefs.insert(std::make_pair(Reg, &MO));
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if (MO.isUse() && Special) {
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if (KeepRegs.insert(Reg)) {
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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KeepRegs.insert(*Subreg);
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void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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// Proceding upwards, registers that are defed but not used in this
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// instruction are now dead.
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if (!TII->isPredicated(MI)) {
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// Predicated defs are modeled as read + write, i.e. similar to two
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!MO.isDef()) continue;
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// Ignore two-addr defs.
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if (MI->isRegTiedToUseOperand(i)) continue;
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DefIndices[Reg] = Count;
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KillIndices[Reg] = ~0u;
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assert(((KillIndices[Reg] == ~0u) !=
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(DefIndices[Reg] == ~0u)) &&
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"Kill and Def maps aren't consistent for Reg!");
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// Repeat, for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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unsigned SubregReg = *Subreg;
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DefIndices[SubregReg] = Count;
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KillIndices[SubregReg] = ~0u;
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KeepRegs.erase(SubregReg);
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Classes[SubregReg] = 0;
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RegRefs.erase(SubregReg);
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// Conservatively mark super-registers as unusable.
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for (const unsigned *Super = TRI->getSuperRegisters(Reg);
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unsigned SuperReg = *Super;
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Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!MO.isUse()) continue;
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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if (!Classes[Reg] && NewRC)
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Classes[Reg] = NewRC;
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else if (!NewRC || Classes[Reg] != NewRC)
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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RegRefs.insert(std::make_pair(Reg, &MO));
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// It wasn't previously live but now it is, this is a kill.
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if (KillIndices[Reg] == ~0u) {
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KillIndices[Reg] = Count;
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DefIndices[Reg] = ~0u;
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assert(((KillIndices[Reg] == ~0u) !=
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(DefIndices[Reg] == ~0u)) &&
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"Kill and Def maps aren't consistent for Reg!");
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (KillIndices[AliasReg] == ~0u) {
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KillIndices[AliasReg] = Count;
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DefIndices[AliasReg] = ~0u;
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CriticalAntiDepBreaker::findSuitableFreeRegister(MachineInstr *MI,
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const TargetRegisterClass *RC)
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for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
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RE = RC->allocation_order_end(MF); R != RE; ++R) {
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unsigned NewReg = *R;
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// Don't consider non-allocatable registers
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if (!AllocatableSet.test(NewReg)) continue;
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// Don't replace a register with itself.
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if (NewReg == AntiDepReg) continue;
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// Don't replace a register with one that was recently used to repair
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// an anti-dependence with this AntiDepReg, because that would
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// re-introduce that anti-dependence.
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if (NewReg == LastNewReg) continue;
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// If the instruction already has a def of the NewReg, it's not suitable.
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// For example, Instruction with multiple definitions can result in this
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if (MI->modifiesRegister(NewReg, TRI)) continue;
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// If NewReg is dead and NewReg's most recent def is not before
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// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
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assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
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&& "Kill and Def maps aren't consistent for AntiDepReg!");
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assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
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&& "Kill and Def maps aren't consistent for NewReg!");
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if (KillIndices[NewReg] != ~0u ||
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Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
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KillIndices[AntiDepReg] > DefIndices[NewReg])
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// No registers are free and available!
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unsigned CriticalAntiDepBreaker::
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BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned InsertPosIndex) {
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// The code below assumes that there is at least one instruction,
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// so just duck out immediately if the block is empty.
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if (SUnits.empty()) return 0;
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// Keep a map of the MachineInstr*'s back to the SUnit representing them.
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// This is used for updating debug information.
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DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
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// Find the node at the bottom of the critical path.
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const SUnit *Max = 0;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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const SUnit *SU = &SUnits[i];
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MISUnitMap[SU->getInstr()] = SU;
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if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
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DEBUG(dbgs() << "Critical path has total latency "
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<< (Max->getDepth() + Max->Latency) << "\n");
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DEBUG(dbgs() << "Available regs:");
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for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
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if (KillIndices[Reg] == ~0u)
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DEBUG(dbgs() << " " << TRI->getName(Reg));
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DEBUG(dbgs() << '\n');
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// Track progress along the critical path through the SUnit graph as we walk
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const SUnit *CriticalPathSU = Max;
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MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
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// Consider this pattern:
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// There are three anti-dependencies here, and without special care,
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// we'd break all of them using the same register:
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// because at each anti-dependence, B is the first register that
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// isn't A which is free. This re-introduces anti-dependencies
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// at all but one of the original anti-dependencies that we were
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// trying to break. To avoid this, keep track of the most recent
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// register that each register was replaced with, avoid
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// using it to repair an anti-dependence on the same register.
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// This lets us produce this:
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// This still has an anti-dependence on B, but at least it isn't on the
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// original critical path.
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// TODO: If we tracked more than one register here, we could potentially
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// fix that remaining critical edge too. This is a little more involved,
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// because unlike the most recent register, less recent registers should
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// still be considered, though only if no other registers are available.
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std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
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// Attempt to break anti-dependence edges on the critical path. Walk the
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// instructions from the bottom up, tracking information about liveness
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// as we go to help determine which registers are available.
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unsigned Count = InsertPosIndex - 1;
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for (MachineBasicBlock::iterator I = End, E = Begin;
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MachineInstr *MI = --I;
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if (MI->isDebugValue())
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// Check if this instruction has a dependence on the critical path that
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// is an anti-dependence that we may be able to break. If it is, set
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// AntiDepReg to the non-zero register associated with the anti-dependence.
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// We limit our attention to the critical path as a heuristic to avoid
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// breaking anti-dependence edges that aren't going to significantly
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// impact the overall schedule. There are a limited number of registers
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// and we want to save them for the important edges.
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// TODO: Instructions with multiple defs could have multiple
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// anti-dependencies. The current code here only knows how to break one
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// edge per instruction. Note that we'd have to be able to break all of
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// the anti-dependencies in an instruction in order to be effective.
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unsigned AntiDepReg = 0;
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if (MI == CriticalPathMI) {
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if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
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const SUnit *NextSU = Edge->getSUnit();
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// Only consider anti-dependence edges.
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if (Edge->getKind() == SDep::Anti) {
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AntiDepReg = Edge->getReg();
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assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
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if (!AllocatableSet.test(AntiDepReg))
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// Don't break anti-dependencies on non-allocatable registers.
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else if (KeepRegs.count(AntiDepReg))
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// Don't break anti-dependencies if an use down below requires
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// this exact register.
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// If the SUnit has other dependencies on the SUnit that it
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// anti-depends on, don't bother breaking the anti-dependency
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// since those edges would prevent such units from being
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// scheduled past each other regardless.
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// Also, if there are dependencies on other SUnits with the
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// same register as the anti-dependency, don't attempt to
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for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
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PE = CriticalPathSU->Preds.end(); P != PE; ++P)
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if (P->getSUnit() == NextSU ?
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(P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
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(P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
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CriticalPathSU = NextSU;
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CriticalPathMI = CriticalPathSU->getInstr();
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// We've reached the end of the critical path.
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PrescanInstruction(MI);
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// If MI's defs have a special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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// defined in a call must not be changed (ABI).
518
if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
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TII->isPredicated(MI))
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// If this instruction's defs have special allocation requirement, don't
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// break this anti-dependency.
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else if (AntiDepReg) {
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// If this instruction has a use of AntiDepReg, breaking it
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
527
MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
530
if (Reg == 0) continue;
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if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
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// Determine AntiDepReg's register class, if it is live and is
539
// consistently used within a single class.
540
const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
541
assert((AntiDepReg == 0 || RC != NULL) &&
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"Register should be live if it's causing an anti-dependence!");
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if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
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// Look for a suitable register to use to break the anti-depenence.
548
// TODO: Instead of picking the first free register, consider which might
550
if (AntiDepReg != 0) {
551
if (unsigned NewReg = findSuitableFreeRegister(MI, AntiDepReg,
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LastNewReg[AntiDepReg],
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DEBUG(dbgs() << "Breaking anti-dependence edge on "
555
<< TRI->getName(AntiDepReg)
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<< " with " << RegRefs.count(AntiDepReg) << " references"
557
<< " using " << TRI->getName(NewReg) << "!\n");
559
// Update the references to the old register to refer to the new
561
std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
562
std::multimap<unsigned, MachineOperand *>::iterator>
563
Range = RegRefs.equal_range(AntiDepReg);
564
for (std::multimap<unsigned, MachineOperand *>::iterator
565
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
566
Q->second->setReg(NewReg);
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// If the SU for the instruction being updated has debug information
568
// related to the anti-dependency register, make sure to update that
570
const SUnit *SU = MISUnitMap[Q->second->getParent()];
572
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
573
MachineInstr *DI = SU->DbgInstrList[i];
574
assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&
575
DI->getOperand(0).getReg()
576
&& "Non register dbg_value attached to SUnit!");
577
if (DI->getOperand(0).getReg() == AntiDepReg)
578
DI->getOperand(0).setReg(NewReg);
582
// We just went back in time and modified history; the
583
// liveness information for the anti-depenence reg is now
584
// inconsistent. Set the state as if it were dead.
585
Classes[NewReg] = Classes[AntiDepReg];
586
DefIndices[NewReg] = DefIndices[AntiDepReg];
587
KillIndices[NewReg] = KillIndices[AntiDepReg];
588
assert(((KillIndices[NewReg] == ~0u) !=
589
(DefIndices[NewReg] == ~0u)) &&
590
"Kill and Def maps aren't consistent for NewReg!");
592
Classes[AntiDepReg] = 0;
593
DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
594
KillIndices[AntiDepReg] = ~0u;
595
assert(((KillIndices[AntiDepReg] == ~0u) !=
596
(DefIndices[AntiDepReg] == ~0u)) &&
597
"Kill and Def maps aren't consistent for AntiDepReg!");
599
RegRefs.erase(AntiDepReg);
600
LastNewReg[AntiDepReg] = NewReg;
605
ScanInstruction(MI, Count);
added
removed
libclamav/c++/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
