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//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation, see the following papers:
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
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// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "PBQP/HeuristicSolver.h"
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#include "PBQP/Graph.h"
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#include "PBQP/Heuristics/Briggs.h"
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#include "RenderMachineFunction.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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static RegisterRegAlloc
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registerPBQPRepAlloc("pbqp", "PBQP register allocator",
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llvm::createPBQPRegisterAllocator);
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pbqpCoalescing("pbqp-coalescing",
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cl::desc("Attempt coalescing during PBQP register allocation."),
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cl::init(false), cl::Hidden);
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pbqpPreSplitting("pbqp-pre-splitting",
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cl::desc("Pre-splite before PBQP register allocation."),
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cl::init(false), cl::Hidden);
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/// PBQP based allocators solve the register allocation problem by mapping
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/// register allocation problems to Partitioned Boolean Quadratic
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/// Programming problems.
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class PBQPRegAlloc : public MachineFunctionPass {
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/// Construct a PBQP register allocator.
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PBQPRegAlloc() : MachineFunctionPass(ID) {}
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "PBQP Register Allocator";
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/// PBQP analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &au) const {
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au.addRequired<SlotIndexes>();
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au.addPreserved<SlotIndexes>();
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au.addRequired<LiveIntervals>();
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//au.addRequiredID(SplitCriticalEdgesID);
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au.addRequired<RegisterCoalescer>();
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au.addRequired<CalculateSpillWeights>();
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au.addRequired<LiveStacks>();
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au.addPreserved<LiveStacks>();
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au.addRequired<MachineLoopInfo>();
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au.addPreserved<MachineLoopInfo>();
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if (pbqpPreSplitting)
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au.addRequired<LoopSplitter>();
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au.addRequired<VirtRegMap>();
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au.addRequired<RenderMachineFunction>();
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MachineFunctionPass::getAnalysisUsage(au);
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/// Perform register allocation
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool operator()(const LiveInterval *li1, const LiveInterval *li2) const {
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return li1->reg < li2->reg;
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typedef std::map<const LiveInterval*, unsigned, LIOrdering> LI2NodeMap;
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typedef std::vector<const LiveInterval*> Node2LIMap;
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typedef std::vector<unsigned> AllowedSet;
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typedef std::vector<AllowedSet> AllowedSetMap;
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typedef std::set<unsigned> RegSet;
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typedef std::pair<unsigned, unsigned> RegPair;
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typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
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typedef std::set<LiveInterval*, LIOrdering> LiveIntervalSet;
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typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
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const TargetMachine *tm;
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const TargetRegisterInfo *tri;
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const TargetInstrInfo *tii;
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const MachineLoopInfo *loopInfo;
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MachineRegisterInfo *mri;
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RenderMachineFunction *rmf;
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AllowedSetMap allowedSets;
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LiveIntervalSet vregIntervalsToAlloc,
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NodeVector problemNodes;
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/// Builds a PBQP cost vector.
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template <typename RegContainer>
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PBQP::Vector buildCostVector(unsigned vReg,
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const RegContainer &allowed,
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const CoalesceMap &cealesces,
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PBQP::PBQPNum spillCost) const;
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/// \brief Builds a PBQP interference matrix.
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/// @return Either a pointer to a non-zero PBQP matrix representing the
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/// allocation option costs, or a null pointer for a zero matrix.
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/// Expects allowed sets for two interfering LiveIntervals. These allowed
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/// sets should contain only allocable registers from the LiveInterval's
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/// register class, with any interfering pre-colored registers removed.
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template <typename RegContainer>
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PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
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const RegContainer &allowed2) const;
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/// Expects allowed sets for two potentially coalescable LiveIntervals,
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/// and an estimated benefit due to coalescing. The allowed sets should
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/// contain only allocable registers from the LiveInterval's register
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/// classes, with any interfering pre-colored registers removed.
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template <typename RegContainer>
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PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
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const RegContainer &allowed2,
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PBQP::PBQPNum cBenefit) const;
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/// \brief Finds coalescing opportunities and returns them as a map.
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/// Any entries in the map are guaranteed coalescable, even if their
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/// corresponding live intervals overlap.
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CoalesceMap findCoalesces();
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/// \brief Finds the initial set of vreg intervals to allocate.
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void findVRegIntervalsToAlloc();
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/// \brief Constructs a PBQP problem representation of the register
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/// allocation problem for this function.
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/// @return a PBQP solver object for the register allocation problem.
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PBQP::Graph constructPBQPProblem();
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/// \brief Adds a stack interval if the given live interval has been
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/// spilled. Used to support stack slot coloring.
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void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
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/// \brief Given a solved PBQP problem maps this solution back to a register
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bool mapPBQPToRegAlloc(const PBQP::Solution &solution);
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/// \brief Postprocessing before final spilling. Sets basic block "live in"
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void finalizeAlloc() const;
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char PBQPRegAlloc::ID = 0;
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template <typename RegContainer>
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PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg,
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const RegContainer &allowed,
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const CoalesceMap &coalesces,
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PBQP::PBQPNum spillCost) const {
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typedef typename RegContainer::const_iterator AllowedItr;
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// Allocate vector. Additional element (0th) used for spill option
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PBQP::Vector v(allowed.size() + 1, 0);
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// Iterate over the allowed registers inserting coalesce benefits if there
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for (AllowedItr itr = allowed.begin(), end = allowed.end();
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itr != end; ++itr, ++ai) {
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unsigned pReg = *itr;
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CoalesceMap::const_iterator cmItr =
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coalesces.find(RegPair(vReg, pReg));
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// No coalesce - on to the next preg.
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if (cmItr == coalesces.end())
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// We have a coalesce - insert the benefit.
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v[ai + 1] = -cmItr->second;
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template <typename RegContainer>
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PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix(
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const RegContainer &allowed1, const RegContainer &allowed2) const {
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typedef typename RegContainer::const_iterator RegContainerIterator;
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// Construct a PBQP matrix representing the cost of allocation options. The
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// rows and columns correspond to the allocation options for the two live
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// intervals. Elements will be infinite where corresponding registers alias,
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// since we cannot allocate aliasing registers to interfering live intervals.
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// All other elements (non-aliasing combinations) will have zero cost. Note
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// that the spill option (element 0,0) has zero cost, since we can allocate
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// both intervals to memory safely (the cost for each individual allocation
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// to memory is accounted for by the cost vectors for each live interval).
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new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
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// Assume this is a zero matrix until proven otherwise. Zero matrices occur
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// between interfering live ranges with non-overlapping register sets (e.g.
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// non-overlapping reg classes, or disjoint sets of allowed regs within the
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// same class). The term "overlapping" is used advisedly: sets which do not
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// intersect, but contain registers which alias, will have non-zero matrices.
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// We optimize zero matrices away to improve solver speed.
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bool isZeroMatrix = true;
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// Row index. Starts at 1, since the 0th row is for the spill option, which
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// Iterate over allowed sets, insert infinities where required.
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for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
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a1Itr != a1End; ++a1Itr) {
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// Column index, starts at 1 as for row index.
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unsigned reg1 = *a1Itr;
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for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
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a2Itr != a2End; ++a2Itr) {
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unsigned reg2 = *a2Itr;
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// If the row/column regs are identical or alias insert an infinity.
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if (tri->regsOverlap(reg1, reg2)) {
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(*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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isZeroMatrix = false;
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// If this turns out to be a zero matrix...
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// free it and return null.
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// ...otherwise return the cost matrix.
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template <typename RegContainer>
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PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix(
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const RegContainer &allowed1, const RegContainer &allowed2,
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PBQP::PBQPNum cBenefit) const {
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typedef typename RegContainer::const_iterator RegContainerIterator;
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// Construct a PBQP Matrix representing the benefits of coalescing. As with
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// interference matrices the rows and columns represent allowed registers
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// for the LiveIntervals which are (potentially) to be coalesced. The amount
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// -cBenefit will be placed in any element representing the same register
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// for both intervals.
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new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
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// Reset costs to zero.
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// Assume the matrix is zero till proven otherwise. Zero matrices will be
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// optimized away as in the interference case.
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bool isZeroMatrix = true;
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// Row index. Starts at 1, since the 0th row is for the spill option, which
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// Iterate over the allowed sets, insert coalescing benefits where
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for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
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a1Itr != a1End; ++a1Itr) {
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// Column index, starts at 1 as for row index.
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unsigned reg1 = *a1Itr;
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for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
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a2Itr != a2End; ++a2Itr) {
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// If the row and column represent the same register insert a beneficial
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// cost to preference this allocation - it would allow us to eliminate a
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if (reg1 == *a2Itr) {
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(*m)[ri][ci] = -cBenefit;
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isZeroMatrix = false;
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// If this turns out to be a zero matrix...
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// ...free it and return null.
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PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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typedef MachineFunction::const_iterator MFIterator;
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typedef MachineBasicBlock::const_iterator MBBIterator;
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typedef LiveInterval::const_vni_iterator VNIIterator;
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CoalesceMap coalescesFound;
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// To find coalesces we need to iterate over the function looking for
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// copy instructions.
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for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
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bbItr != bbEnd; ++bbItr) {
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const MachineBasicBlock *mbb = &*bbItr;
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for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
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iItr != iEnd; ++iItr) {
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const MachineInstr *instr = &*iItr;
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// If this isn't a copy then continue to the next instruction.
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if (!instr->isCopy())
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unsigned srcReg = instr->getOperand(1).getReg();
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unsigned dstReg = instr->getOperand(0).getReg();
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// If the registers are already the same our job is nice and easy.
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if (dstReg == srcReg)
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bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
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dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
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// If both registers are physical then we can't coalesce.
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if (srcRegIsPhysical && dstRegIsPhysical)
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// If it's a copy that includes two virtual register but the source and
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// destination classes differ then we can't coalesce.
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if (!srcRegIsPhysical && !dstRegIsPhysical &&
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mri->getRegClass(srcReg) != mri->getRegClass(dstReg))
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// If one is physical and one is virtual, check that the physical is
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// allocatable in the class of the virtual.
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if (srcRegIsPhysical && !dstRegIsPhysical) {
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const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg);
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if (std::find(dstRegClass->allocation_order_begin(*mf),
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dstRegClass->allocation_order_end(*mf), srcReg) ==
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dstRegClass->allocation_order_end(*mf))
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if (!srcRegIsPhysical && dstRegIsPhysical) {
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const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg);
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if (std::find(srcRegClass->allocation_order_begin(*mf),
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srcRegClass->allocation_order_end(*mf), dstReg) ==
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srcRegClass->allocation_order_end(*mf))
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// If we've made it here we have a copy with compatible register classes.
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// We can probably coalesce, but we need to consider overlap.
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const LiveInterval *srcLI = &lis->getInterval(srcReg),
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*dstLI = &lis->getInterval(dstReg);
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if (srcLI->overlaps(*dstLI)) {
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// Even in the case of an overlap we might still be able to coalesce,
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// but we need to make sure that no definition of either range occurs
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// while the other range is live.
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// Otherwise start by assuming we're ok.
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// Test all defs of the source range.
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vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
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vniItr != vniEnd; ++vniItr) {
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// If we find a poorly defined def we err on the side of caution.
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if (!(*vniItr)->def.isValid()) {
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// If we find a def that kills the coalescing opportunity then
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// record it and break from the loop.
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if (dstLI->liveAt((*vniItr)->def)) {
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// If we have a bad def give up, continue to the next instruction.
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// Otherwise test definitions of the destination range.
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vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
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vniItr != vniEnd; ++vniItr) {
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// We want to make sure we skip the copy instruction itself.
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if ((*vniItr)->getCopy() == instr)
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if (!(*vniItr)->def.isValid()) {
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if (srcLI->liveAt((*vniItr)->def)) {
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// As before a bad def we give up and continue to the next instr.
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// If we make it to here then either the ranges didn't overlap, or they
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// did, but none of their definitions would prevent us from coalescing.
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// We're good to go with the coalesce.
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float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0;
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coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
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coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
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return coalescesFound;
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void PBQPRegAlloc::findVRegIntervalsToAlloc() {
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// Iterate over all live ranges.
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for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
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// Ignore physical ones.
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if (TargetRegisterInfo::isPhysicalRegister(itr->first))
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LiveInterval *li = itr->second;
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// If this live interval is non-empty we will use pbqp to allocate it.
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// Empty intervals we allocate in a simple post-processing stage in
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vregIntervalsToAlloc.insert(li);
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emptyVRegIntervals.insert(li);
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PBQP::Graph PBQPRegAlloc::constructPBQPProblem() {
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typedef std::vector<const LiveInterval*> LIVector;
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typedef std::vector<unsigned> RegVector;
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// This will store the physical intervals for easy reference.
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LIVector physIntervals;
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// Start by clearing the old node <-> live interval mappings & allowed sets
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// Populate physIntervals, update preg use:
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for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
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if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
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physIntervals.push_back(itr->second);
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mri->setPhysRegUsed(itr->second->reg);
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// Iterate over vreg intervals, construct live interval <-> node number
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for (LiveIntervalSet::const_iterator
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itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
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const LiveInterval *li = *itr;
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li2Node[li] = node2LI.size();
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node2LI.push_back(li);
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// Get the set of potential coalesces.
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CoalesceMap coalesces;
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if (pbqpCoalescing) {
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coalesces = findCoalesces();
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// Construct a PBQP solver for this problem
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problemNodes.resize(vregIntervalsToAlloc.size());
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// Resize allowedSets container appropriately.
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allowedSets.resize(vregIntervalsToAlloc.size());
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BitVector ReservedRegs = tri->getReservedRegs(*mf);
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// Iterate over virtual register intervals to compute allowed sets...
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for (unsigned node = 0; node < node2LI.size(); ++node) {
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// Grab pointers to the interval and its register class.
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const LiveInterval *li = node2LI[node];
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const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
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// Start by assuming all allocable registers in the class are allowed...
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TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf);
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TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf);
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for (TargetRegisterClass::iterator it = aob; it != aoe; ++it)
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if (!ReservedRegs.test(*it))
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liAllowed.push_back(*it);
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// Eliminate the physical registers which overlap with this range, along
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// with all their aliases.
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for (LIVector::iterator pItr = physIntervals.begin(),
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pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
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if (!li->overlaps(**pItr))
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unsigned pReg = (*pItr)->reg;
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// If we get here then the live intervals overlap, but we're still ok
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// if they're coalescable.
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if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end())
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// If we get here then we have a genuine exclusion.
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// Remove the overlapping reg...
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RegVector::iterator eraseItr =
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std::find(liAllowed.begin(), liAllowed.end(), pReg);
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if (eraseItr != liAllowed.end())
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liAllowed.erase(eraseItr);
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const unsigned *aliasItr = tri->getAliasSet(pReg);
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// ...and its aliases.
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for (; *aliasItr != 0; ++aliasItr) {
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RegVector::iterator eraseItr =
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std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
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if (eraseItr != liAllowed.end()) {
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liAllowed.erase(eraseItr);
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// Copy the allowed set into a member vector for use when constructing cost
648
// vectors & matrices, and mapping PBQP solutions back to assignments.
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allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
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// Set the spill cost to the interval weight, or epsilon if the
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// interval weight is zero
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PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
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li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
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// Build a cost vector for this interval.
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buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
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// Now add the cost matrices...
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for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
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const LiveInterval *li = node2LI[node1];
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// Test for live range overlaps and insert interference matrices.
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for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
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const LiveInterval *li2 = node2LI[node2];
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CoalesceMap::const_iterator cmItr =
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coalesces.find(RegPair(li->reg, li2->reg));
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if (cmItr != coalesces.end()) {
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m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
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else if (li->overlaps(*li2)) {
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m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
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problem.addEdge(problemNodes[node1],
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assert(problem.getNumNodes() == allowedSets.size());
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std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
698
<< problem.getNumEdges() << " edges.\n";
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problem.printDot(std::cerr);
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// We're done, PBQP problem constructed - return it.
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void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled,
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MachineRegisterInfo* mri) {
708
int stackSlot = vrm->getStackSlot(spilled->reg);
710
if (stackSlot == VirtRegMap::NO_STACK_SLOT)
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const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
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LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
717
if (stackInterval.getNumValNums() != 0)
718
vni = stackInterval.getValNumInfo(0);
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vni = stackInterval.getNextValue(
721
SlotIndex(), 0, false, lss->getVNInfoAllocator());
723
LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
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stackInterval.MergeRangesInAsValue(rhsInterval, vni);
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bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
729
// Set to true if we have any spills
730
bool anotherRoundNeeded = false;
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// Clear the existing allocation.
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// Iterate over the nodes mapping the PBQP solution to a register assignment.
736
for (unsigned node = 0; node < node2LI.size(); ++node) {
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unsigned virtReg = node2LI[node]->reg,
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allocSelection = solution.getSelection(problemNodes[node]);
741
// If the PBQP solution is non-zero it's a physical register...
742
if (allocSelection != 0) {
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// Get the physical reg, subtracting 1 to account for the spill option.
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unsigned physReg = allowedSets[node][allocSelection - 1];
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DEBUG(dbgs() << "VREG " << virtReg << " -> "
747
<< tri->getName(physReg) << "\n");
749
assert(physReg != 0);
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// Add to the virt reg map and update the used phys regs.
752
vrm->assignVirt2Phys(virtReg, physReg);
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// ...Otherwise it's a spill.
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// Make sure we ignore this virtual reg on the next round
759
vregIntervalsToAlloc.erase(&lis->getInterval(virtReg));
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// Insert spill ranges for this live range
762
const LiveInterval *spillInterval = node2LI[node];
763
double oldSpillWeight = spillInterval->weight;
764
SmallVector<LiveInterval*, 8> spillIs;
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rmf->rememberUseDefs(spillInterval);
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std::vector<LiveInterval*> newSpills =
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lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
768
addStackInterval(spillInterval, mri);
769
rmf->rememberSpills(spillInterval, newSpills);
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(void) oldSpillWeight;
772
DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: "
773
<< oldSpillWeight << ", New vregs: ");
775
// Copy any newly inserted live intervals into the list of regs to
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for (std::vector<LiveInterval*>::const_iterator
778
itr = newSpills.begin(), end = newSpills.end();
781
assert(!(*itr)->empty() && "Empty spill range.");
783
DEBUG(dbgs() << (*itr)->reg << " ");
785
vregIntervalsToAlloc.insert(*itr);
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DEBUG(dbgs() << ")\n");
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// We need another round if spill intervals were added.
791
anotherRoundNeeded |= !newSpills.empty();
795
return !anotherRoundNeeded;
798
void PBQPRegAlloc::finalizeAlloc() const {
799
typedef LiveIntervals::iterator LIIterator;
800
typedef LiveInterval::Ranges::const_iterator LRIterator;
802
// First allocate registers for the empty intervals.
803
for (LiveIntervalSet::const_iterator
804
itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
806
LiveInterval *li = *itr;
808
unsigned physReg = vrm->getRegAllocPref(li->reg);
811
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
812
physReg = *liRC->allocation_order_begin(*mf);
815
vrm->assignVirt2Phys(li->reg, physReg);
818
// Finally iterate over the basic blocks to compute and set the live-in sets.
819
SmallVector<MachineBasicBlock*, 8> liveInMBBs;
820
MachineBasicBlock *entryMBB = &*mf->begin();
822
for (LIIterator liItr = lis->begin(), liEnd = lis->end();
823
liItr != liEnd; ++liItr) {
825
const LiveInterval *li = liItr->second;
828
// Get the physical register for this interval
829
if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
832
else if (vrm->isAssignedReg(li->reg)) {
833
reg = vrm->getPhys(li->reg);
836
// Ranges which are assigned a stack slot only are ignored.
841
// Filter out zero regs - they're for intervals that were spilled.
845
// Iterate over the ranges of the current interval...
846
for (LRIterator lrItr = li->begin(), lrEnd = li->end();
847
lrItr != lrEnd; ++lrItr) {
849
// Find the set of basic blocks which this range is live into...
850
if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
851
// And add the physreg for this interval to their live-in sets.
852
for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
853
if (liveInMBBs[i] != entryMBB) {
854
if (!liveInMBBs[i]->isLiveIn(reg)) {
855
liveInMBBs[i]->addLiveIn(reg);
866
bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
869
tm = &mf->getTarget();
870
tri = tm->getRegisterInfo();
871
tii = tm->getInstrInfo();
872
mri = &mf->getRegInfo();
874
lis = &getAnalysis<LiveIntervals>();
875
lss = &getAnalysis<LiveStacks>();
876
loopInfo = &getAnalysis<MachineLoopInfo>();
877
rmf = &getAnalysis<RenderMachineFunction>();
879
vrm = &getAnalysis<VirtRegMap>();
882
DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
884
// Allocator main loop:
886
// * Map current regalloc problem to a PBQP problem
887
// * Solve the PBQP problem
888
// * Map the solution back to a register allocation
889
// * Spill if necessary
891
// This process is continued till no more spills are generated.
893
// Find the vreg intervals in need of allocation.
894
findVRegIntervalsToAlloc();
896
// If there are non-empty intervals allocate them using pbqp.
897
if (!vregIntervalsToAlloc.empty()) {
899
bool pbqpAllocComplete = false;
902
while (!pbqpAllocComplete) {
903
DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
905
PBQP::Graph problem = constructPBQPProblem();
906
PBQP::Solution solution =
907
PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
909
pbqpAllocComplete = mapPBQPToRegAlloc(solution);
915
// Finalise allocation, allocate empty ranges.
918
rmf->renderMachineFunction("After PBQP register allocation.", vrm);
920
vregIntervalsToAlloc.clear();
921
emptyVRegIntervals.clear();
925
problemNodes.clear();
927
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
930
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
932
rewriter->runOnMachineFunction(*mf, *vrm, lis);
937
FunctionPass* llvm::createPBQPRegisterAllocator() {
938
return new PBQPRegAlloc();
added
removed
libclamav/c++/llvm/lib/CodeGen/RegAllocPBQP.cpp
