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//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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class X86RegisterInfo;
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class X86TargetMachine;
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// Enums for memory operand decoding. Each memory operand is represented with
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// a 5 operand sequence in the form:
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// [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
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// These enums help decode this.
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/// AddrSegmentReg - The operand # of the segment in the memory operand.
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/// AddrNumOperands - Total number of operands in a memory reference.
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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// Artificial condition codes. These are used by AnalyzeBranch
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// to indicate a block terminated with two conditional branches to
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// the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
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// which can't be represented on x86 with a single condition. These
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// are never used in MachineInstrs.
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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/// Target Operand Flag enum.
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//===------------------------------------------------------------------===//
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// X86 Specific MachineOperand flags.
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/// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
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/// SYMBOL_LABEL + [. - PICBASELABEL]
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MO_GOT_ABSOLUTE_ADDRESS,
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/// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
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/// immediate should get the value of the symbol minus the PIC base label:
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/// SYMBOL_LABEL - PICBASELABEL
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/// MO_GOT - On a symbol operand this indicates that the immediate is the
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/// offset to the GOT entry for the symbol name from the base of the GOT.
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOT
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/// MO_GOTOFF - On a symbol operand this indicates that the immediate is
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/// the offset to the location of the symbol name from the base of the GOT.
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTOFF
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/// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
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/// offset to the GOT entry for the symbol name from the current code
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTPCREL
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/// MO_PLT - On a symbol operand this indicates that the immediate is
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/// offset to the PLT entry of symbol name from the current code location.
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @PLT
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/// MO_TLSGD - On a symbol operand this indicates that the immediate is
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TLSGD
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/// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @GOTTPOFF
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/// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @INDNTPOFF
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/// MO_TPOFF - On a symbol operand this indicates that the immediate is
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TPOFF
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/// MO_NTPOFF - On a symbol operand this indicates that the immediate is
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @NTPOFF
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/// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "__imp_FOO" symbol. This is used for
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/// dllimport linkage on windows.
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/// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$stub" symbol. This is used for calls
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/// and jumps to external functions on Tiger and before.
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/// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
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/// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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/// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
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/// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
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/// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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MO_DARWIN_NONLAZY_PIC_BASE,
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/// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
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/// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
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/// which is a PIC-base-relative reference to a hidden dyld lazy pointer
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MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
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/// MO_TLVP - On a symbol operand this indicates that the immediate is
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/// This is the TLS offset for the Darwin TLS mechanism.
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/// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
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/// is some TLS offset from the picbase.
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/// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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/// a reference to a stub for a global, not the global itself.
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
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case X86II::MO_TLVP: // ??? Pretty sure..
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for X86
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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/// MRM[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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// First, instructions that operate on a register r/m operand...
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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
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// MRMInitReg - This form is used for instructions whose source and
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// destinations are the same register.
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//// MRM_C1 - A mod/rm byte of exactly 0xC1.
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/// RawFrmImm16 - This is used for CALL FAR instructions, which have two
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/// immediates, the first of which is a 16 or 32-bit immediate (specified by
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/// the imm encoding) and the second is a 16-bit fixed value. In the AMD
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/// manual, this operand is described as pntr16:32 and pntr16:16
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//===------------------------------------------------------------------===//
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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// instead of 32 bit address (or 32 bit address in 64 bit mode).
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//===------------------------------------------------------------------===//
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
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// used to obtain the setting of this field. If no bits in this field is
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// set, there is no prefix byte for obtaining a multibyte opcode.
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Op0Mask = 0xF << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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// REP - The 0xF3 prefix byte indicating repetition of the following
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
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DA = 5 << Op0Shift, DB = 6 << Op0Shift,
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DC = 7 << Op0Shift, DD = 8 << Op0Shift,
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DE = 9 << Op0Shift, DF = 10 << Op0Shift,
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// XS, XD - These prefix codes are for single and double precision scalar
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// floating point operations performed in the SSE registers.
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XD = 11 << Op0Shift, XS = 12 << Op0Shift,
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// T8, TA - Prefix after the 0x0F prefix.
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T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
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// TF - Prefix before and after 0x0F
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//===------------------------------------------------------------------===//
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// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
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// They are used to specify GPRs and SSE registers, 64-bit operand size,
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// etc. We only cares about REX.W and REX.R bits and only the former is
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// statically determined.
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REX_W = 1 << REXShift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm8PCRel = 2 << ImmShift,
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Imm16 = 3 << ImmShift,
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Imm16PCRel = 4 << ImmShift,
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Imm32 = 5 << ImmShift,
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Imm32PCRel = 6 << ImmShift,
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Imm64 = 7 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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NotFP = 0 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
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// explicit argument, but have no destination. Example: fucom, fucomi, ...
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CompareFP = 5 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 6 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 7 << FPTypeShift,
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LOCK = 1 << LOCKShift,
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// Segment override prefixes. Currently we just need ability to address
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// stuff in gs and fs segments.
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SegOvrMask = 3 << SegOvrShift,
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FS = 1 << SegOvrShift,
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GS = 2 << SegOvrShift,
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// Execution domain for SSE instructions in bits 22, 23.
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// 0 in bits 22-23 means normal, non-SSE instruction.
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OpcodeMask = 0xFF << OpcodeShift,
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//===------------------------------------------------------------------===//
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// VEX - The opcode prefix used by AVX instructions
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// VEX_W - Has a opcode specific functionality, but is used in the same
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// way as REX_W is for regular SSE instructions.
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// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
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// address instructions in SSE are represented as 3 address ones in AVX
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// and the additional register is encoded in VEX_VVVV prefix.
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// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
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// must be encoded in the i8 immediate field. This usually happens in
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// instructions with 4 operands.
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// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
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// instruction uses 256-bit wide registers. This is usually auto detected if
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// a VR256 register is used, but some AVX instructions also have this field
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// marked when using a f256 memory references.
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
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return TSFlags >> X86II::OpcodeShift;
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static inline bool hasImm(uint64_t TSFlags) {
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return (TSFlags & X86II::ImmMask) != 0;
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/// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
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/// of the specified instruction.
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static inline unsigned getSizeOfImm(uint64_t TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8PCRel: return 1;
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case X86II::Imm16PCRel: return 2;
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case X86II::Imm32PCRel: return 4;
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case X86II::Imm64: return 8;
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/// isImmPCRel - Return true if the immediate of the specified instruction's
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/// TSFlags indicates that it is pc relative.
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static inline unsigned isImmPCRel(uint64_t TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8PCRel:
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case X86II::Imm16PCRel:
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case X86II::Imm32PCRel:
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/// getMemoryOperandNo - The function returns the MCInst operand # for the
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/// first field of the memory operand. If the instruction doesn't have a
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/// memory operand, this returns -1.
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/// Note that this ignores tied operands. If there is a tied register which
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/// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
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/// counted as one operand.
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static inline int getMemoryOperandNo(uint64_t TSFlags) {
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
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default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
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case X86II::AddRegFrm:
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case X86II::MRMDestReg:
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case X86II::MRMSrcReg:
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case X86II::RawFrmImm16:
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case X86II::MRMDestMem:
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case X86II::MRMSrcMem: {
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bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
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unsigned FirstMemOp = 1;
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++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
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// FIXME: Maybe lea should have its own form? This is a horrible hack.
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//if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
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// Opcode == X86::LEA16r || Opcode == X86::LEA32r)
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case X86II::MRM0r: case X86II::MRM1r:
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r:
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m:
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inline static bool isScale(const MachineOperand &MO) {
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isReg() &&
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(MI->getOperand(Op+3).isImm() ||
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MI->getOperand(Op+3).isGlobal() ||
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MI->getOperand(Op+3).isCPI() ||
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MI->getOperand(Op+3).isJTI());
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+5 <= MI->getNumOperands() &&
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MI->getOperand(Op+4).isReg() &&
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class X86InstrInfo : public TargetInstrInfoImpl {
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X86TargetMachine &TM;
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const X86RegisterInfo RI;
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/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2 - Load / store folding opcode maps.
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
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explicit X86InstrInfo(X86TargetMachine &tm);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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/// hasLoadFromStackSlot - If the specified machine instruction has
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/// a load from a stack slot, return true along with the FrameIndex
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/// of the loaded stack slot and the machine mem operand containing
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/// the reference. If not, return false. Unlike
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/// isLoadFromStackSlot, this returns true for any instructions that
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/// loads from the stack. This is a hint only and may not catch all
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bool hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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/// hasStoreToStackSlot - If the specified machine instruction has a
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/// store to a stack slot, return true along with the FrameIndex of
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/// the loaded stack slot and the machine mem operand containing the
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/// reference. If not, return false. Unlike isStoreToStackSlot,
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/// this returns true for any instructions that loads from the
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/// stack. This is a hint only and may not catch all cases.
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bool hasStoreToStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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/// commuteInstruction - We have a few instructions that must be hacked on to
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
717
SmallVectorImpl<MachineInstr*> &NewMIs) const;
719
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
720
MachineBasicBlock::iterator MI,
721
unsigned DestReg, int FrameIndex,
722
const TargetRegisterClass *RC,
723
const TargetRegisterInfo *TRI) const;
725
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
726
SmallVectorImpl<MachineOperand> &Addr,
727
const TargetRegisterClass *RC,
728
MachineInstr::mmo_iterator MMOBegin,
729
MachineInstr::mmo_iterator MMOEnd,
730
SmallVectorImpl<MachineInstr*> &NewMIs) const;
732
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
733
MachineBasicBlock::iterator MI,
734
const std::vector<CalleeSavedInfo> &CSI,
735
const TargetRegisterInfo *TRI) const;
737
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
738
MachineBasicBlock::iterator MI,
739
const std::vector<CalleeSavedInfo> &CSI,
740
const TargetRegisterInfo *TRI) const;
743
MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
744
int FrameIx, uint64_t Offset,
748
/// foldMemoryOperand - If this target supports it, fold a load or store of
749
/// the specified stack slot into the specified machine instruction for the
750
/// specified operand(s). If this is possible, the target should perform the
751
/// folding and return true, otherwise it should return false. If it folds
752
/// the instruction, it is likely that the MachineInstruction the iterator
753
/// references has been changed.
754
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
756
const SmallVectorImpl<unsigned> &Ops,
757
int FrameIndex) const;
759
/// foldMemoryOperand - Same as the previous version except it allows folding
760
/// of any load and store from / to any address, not just from a specific
762
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
764
const SmallVectorImpl<unsigned> &Ops,
765
MachineInstr* LoadMI) const;
767
/// canFoldMemoryOperand - Returns true if the specified load / store is
768
/// folding is possible.
769
virtual bool canFoldMemoryOperand(const MachineInstr*,
770
const SmallVectorImpl<unsigned> &) const;
772
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
773
/// a store or a load and a store into two or more instruction. If this is
774
/// possible, returns true as well as the new instructions by reference.
775
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
776
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
777
SmallVectorImpl<MachineInstr*> &NewMIs) const;
779
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
780
SmallVectorImpl<SDNode*> &NewNodes) const;
782
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
783
/// instruction after load / store are unfolded from an instruction of the
784
/// specified opcode. It returns zero if the specified unfolding is not
785
/// possible. If LoadRegIndex is non-null, it is filled in with the operand
786
/// index of the operand which will hold the register holding the loaded
788
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
789
bool UnfoldLoad, bool UnfoldStore,
790
unsigned *LoadRegIndex = 0) const;
792
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
793
/// to determine if two loads are loading from the same base address. It
794
/// should only return true if the base pointers are the same and the
795
/// only differences between the two addresses are the offset. It also returns
796
/// the offsets by reference.
797
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
798
int64_t &Offset1, int64_t &Offset2) const;
800
/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
801
/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
802
/// be scheduled togther. On some targets if two loads are loading from
803
/// addresses in the same cache line, it's better if they are scheduled
804
/// together. This function takes two integers that represent the load offsets
805
/// from the common base address. It returns true if it decides it's desirable
806
/// to schedule the two loads together. "NumLoads" is the number of loads that
807
/// have already been scheduled after Load1.
808
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
809
int64_t Offset1, int64_t Offset2,
810
unsigned NumLoads) const;
812
virtual void getNoopForMachoTarget(MCInst &NopInst) const;
815
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
817
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
818
/// instruction that defines the specified register class.
819
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
821
static bool isX86_64NonExtLowByteReg(unsigned reg) {
822
return (reg == X86::SPL || reg == X86::BPL ||
823
reg == X86::SIL || reg == X86::DIL);
826
static bool isX86_64ExtendedReg(const MachineOperand &MO) {
827
if (!MO.isReg()) return false;
828
return isX86_64ExtendedReg(MO.getReg());
831
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
832
/// higher) register? e.g. r8, xmm8, xmm13, etc.
833
static bool isX86_64ExtendedReg(unsigned RegNo);
835
/// getGlobalBaseReg - Return a virtual register initialized with the
836
/// the global base register value. Output instructions required to
837
/// initialize the register in the function entry block, if necessary.
839
unsigned getGlobalBaseReg(MachineFunction *MF) const;
841
/// GetSSEDomain - Return the SSE execution domain of MI as the first element,
842
/// and a bitmask of possible arguments to SetSSEDomain ase the second.
843
std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
845
/// SetSSEDomain - Set the SSEDomain of MI.
846
void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
849
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
850
MachineFunction::iterator &MFI,
851
MachineBasicBlock::iterator &MBBI,
852
LiveVariables *LV) const;
854
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
857
const SmallVectorImpl<MachineOperand> &MOs,
858
unsigned Size, unsigned Alignment) const;
860
/// isFrameOperand - Return true and the FrameIndex if the specified
861
/// operand and follow operands form a reference to the stack frame.
862
bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
863
int &FrameIndex) const;
866
} // End llvm namespace
added
removed
libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.h
