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//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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let Namespace = "X86" in {
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// Subregister indices.
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def sub_8bit : SubRegIndex;
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def sub_8bit_hi : SubRegIndex;
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def sub_16bit : SubRegIndex;
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def sub_32bit : SubRegIndex;
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def sub_ss : SubRegIndex;
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def sub_sd : SubRegIndex;
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def sub_xmm : SubRegIndex;
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// Dwarf numbering is different for 32-bit and 64-bit, and there are
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// variations by target as well. Currently the first entry is for X86-64,
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// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
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// and debug information on X86-32/Darwin)
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def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
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def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
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def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
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def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
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def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
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def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
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def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
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def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
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def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
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def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
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def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
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def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
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def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
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def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
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def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
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def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
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// High registers. On x86-64, these cannot be used in any instruction
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def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
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def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
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def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
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def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
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let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
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def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
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def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
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def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
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def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
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let SubRegIndices = [sub_8bit] in {
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def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
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def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
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def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
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def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
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def IP : Register<"ip">, DwarfRegNum<[16]>;
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let SubRegIndices = [sub_8bit] in {
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def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
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def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
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def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
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def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
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def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
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def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
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def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
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def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
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let SubRegIndices = [sub_16bit] in {
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def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
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def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
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def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
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def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
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def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
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def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
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def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
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def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
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def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
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def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
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def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
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def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
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def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
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def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
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def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
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def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
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def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
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// 64-bit registers, X86-64 only
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let SubRegIndices = [sub_32bit] in {
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def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
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def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
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def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
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def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
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def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
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def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
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def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
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def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
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def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
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// Pseudo Floating Point registers
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def FP0 : Register<"fp0">;
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def FP1 : Register<"fp1">;
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def FP2 : Register<"fp2">;
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def FP3 : Register<"fp3">;
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def FP4 : Register<"fp4">;
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def FP5 : Register<"fp5">;
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def FP6 : Register<"fp6">;
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// XMM Registers, used by the various SSE instruction set extensions.
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// The sub_ss and sub_sd subregs are the same registers with another regclass.
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let CompositeIndices = [(sub_ss), (sub_sd)] in {
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def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
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def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
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def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
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def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
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def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
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def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
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def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
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def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
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def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
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def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
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def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
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def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
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def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
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def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
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def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
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def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
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// YMM Registers, used by AVX instructions
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let SubRegIndices = [sub_xmm] in {
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def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
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def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
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def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
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def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
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def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
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def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
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def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
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def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
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def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
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def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
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def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
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def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
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def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
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def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
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def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
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def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
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// Floating point stack registers
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def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
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def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
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def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
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def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
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def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
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def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
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def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
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def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
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// Status flags register
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def EFLAGS : Register<"flags">;
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def CS : Register<"cs">;
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def DS : Register<"ds">;
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def SS : Register<"ss">;
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def ES : Register<"es">;
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def FS : Register<"fs">;
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def GS : Register<"gs">;
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def DR0 : Register<"dr0">;
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def DR1 : Register<"dr1">;
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def DR2 : Register<"dr2">;
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def DR3 : Register<"dr3">;
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def DR4 : Register<"dr4">;
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def DR5 : Register<"dr5">;
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def DR6 : Register<"dr6">;
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def DR7 : Register<"dr7">;
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// Condition registers
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def CR0 : Register<"cr0">;
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def CR1 : Register<"cr1">;
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def CR2 : Register<"cr2">;
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def CR3 : Register<"cr3">;
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def CR4 : Register<"cr4">;
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def CR5 : Register<"cr5">;
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def CR6 : Register<"cr6">;
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def CR7 : Register<"cr7">;
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def CR8 : Register<"cr8">;
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// Pseudo index registers
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def EIZ : Register<"eiz">;
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def RIZ : Register<"riz">;
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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// List call-clobbered registers before callee-save registers. RBX, RBP, (and
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// R12, R13, R14, and R15 for X86-64) are callee-save registers.
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// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
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// Allocate R12 and R13 last, as these require an extra byte when
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// encoded in x86_64 instructions.
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// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
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// 64-bit mode. The main complication is that they cannot be encoded in an
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// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
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// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
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// cannot be encoded.
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def GR8 : RegisterClass<"X86", [i8], 8,
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[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
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R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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let MethodBodies = [{
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static const unsigned X86_GR8_AO_64[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
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X86::R8B, X86::R9B, X86::R10B, X86::R11B,
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X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
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GR8Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return X86_GR8_AO_64;
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GR8Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (!Subtarget.is64Bit())
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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else if (RI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate SPL or BPL.
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return array_endof(X86_GR8_AO_64) - 1;
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// If not, just don't allocate SPL.
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return array_endof(X86_GR8_AO_64);
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def GR16 : RegisterClass<"X86", [i16], 16,
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[AX, CX, DX, SI, DI, BX, BP, SP,
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R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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let MethodBodies = [{
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static const unsigned X86_GR16_AO_64[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
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X86::R8W, X86::R9W, X86::R10W, X86::R11W,
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X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
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GR16Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return X86_GR16_AO_64;
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GR16Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
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if (Subtarget.is64Bit()) {
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// Does the function dedicate RBP to being a frame ptr?
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if (RI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate SP or BP.
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return array_endof(X86_GR16_AO_64) - 1;
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// If not, just don't allocate SP.
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return array_endof(X86_GR16_AO_64);
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// Does the function dedicate EBP to being a frame ptr?
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if (RI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate SP or BP.
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// If not, just don't allocate SP.
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def GR32 : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
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R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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let MethodBodies = [{
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static const unsigned X86_GR32_AO_64[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
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X86::R8D, X86::R9D, X86::R10D, X86::R11D,
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X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
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GR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return X86_GR32_AO_64;
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GR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
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if (Subtarget.is64Bit()) {
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// Does the function dedicate RBP to being a frame ptr?
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if (RI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate ESP or EBP.
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return array_endof(X86_GR32_AO_64) - 1;
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// If not, just don't allocate ESP.
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return array_endof(X86_GR32_AO_64);
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// Does the function dedicate EBP to being a frame ptr?
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if (RI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate ESP or EBP.
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// If not, just don't allocate ESP.
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// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
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// RIP isn't really a register and it can't be used anywhere except in an
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// address, but it doesn't cause trouble.
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def GR64 : RegisterClass<"X86", [i64], 64,
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[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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let MethodBodies = [{
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GR64Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
434
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
435
if (!Subtarget.is64Bit())
436
return begin(); // None of these are allocatable in 32-bit.
437
// Does the function dedicate RBP to being a frame ptr?
438
if (RI->hasFP(MF) || MFI->getReserveFP())
439
return end()-3; // If so, don't allocate RIP, RSP or RBP
441
return end()-2; // If not, just don't allocate RIP or RSP
446
// Segment registers for use by MOV instructions (and others) that have a
447
// segment register as one operand. Always contain a 16-bit segment
449
def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
453
def DEBUG_REG : RegisterClass<"X86", [i32], 32,
454
[DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
457
// Control registers.
458
def CONTROL_REG : RegisterClass<"X86", [i64], 64,
459
[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
462
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
463
// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
464
// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
465
// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
466
// and GR64_ABCD are classes for registers that support 8-bit h-register
468
def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
470
def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
472
def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
473
let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
475
def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
476
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
477
(GR8_ABCD_H sub_8bit_hi),
478
(GR16_ABCD sub_16bit)];
480
def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
481
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
482
(GR8_ABCD_H sub_8bit_hi),
483
(GR16_ABCD sub_16bit),
484
(GR32_ABCD sub_32bit)];
486
def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
487
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
489
def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
491
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
493
(GR32_TC sub_32bit)];
496
// GR8_NOREX - GR8 registers which do not require a REX prefix.
497
def GR8_NOREX : RegisterClass<"X86", [i8], 8,
498
[AL, CL, DL, AH, CH, DH, BL, BH]> {
499
let MethodProtos = [{
500
iterator allocation_order_begin(const MachineFunction &MF) const;
501
iterator allocation_order_end(const MachineFunction &MF) const;
503
let MethodBodies = [{
504
// In 64-bit mode, it's not safe to blindly allocate H registers.
505
static const unsigned X86_GR8_NOREX_AO_64[] = {
506
X86::AL, X86::CL, X86::DL, X86::BL
509
GR8_NOREXClass::iterator
510
GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
511
const TargetMachine &TM = MF.getTarget();
512
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
513
if (Subtarget.is64Bit())
514
return X86_GR8_NOREX_AO_64;
519
GR8_NOREXClass::iterator
520
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
521
const TargetMachine &TM = MF.getTarget();
522
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
523
if (Subtarget.is64Bit())
524
return array_endof(X86_GR8_NOREX_AO_64);
530
// GR16_NOREX - GR16 registers which do not require a REX prefix.
531
def GR16_NOREX : RegisterClass<"X86", [i16], 16,
532
[AX, CX, DX, SI, DI, BX, BP, SP]> {
533
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
534
let MethodProtos = [{
535
iterator allocation_order_end(const MachineFunction &MF) const;
537
let MethodBodies = [{
538
GR16_NOREXClass::iterator
539
GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
540
const TargetMachine &TM = MF.getTarget();
541
const TargetRegisterInfo *RI = TM.getRegisterInfo();
542
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
543
// Does the function dedicate RBP / EBP to being a frame ptr?
544
if (RI->hasFP(MF) || MFI->getReserveFP())
545
// If so, don't allocate SP or BP.
548
// If not, just don't allocate SP.
553
// GR32_NOREX - GR32 registers which do not require a REX prefix.
554
def GR32_NOREX : RegisterClass<"X86", [i32], 32,
555
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
556
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
557
(GR16_NOREX sub_16bit)];
558
let MethodProtos = [{
559
iterator allocation_order_end(const MachineFunction &MF) const;
561
let MethodBodies = [{
562
GR32_NOREXClass::iterator
563
GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
564
const TargetMachine &TM = MF.getTarget();
565
const TargetRegisterInfo *RI = TM.getRegisterInfo();
566
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
567
// Does the function dedicate RBP / EBP to being a frame ptr?
568
if (RI->hasFP(MF) || MFI->getReserveFP())
569
// If so, don't allocate ESP or EBP.
572
// If not, just don't allocate ESP.
577
// GR64_NOREX - GR64 registers which do not require a REX prefix.
578
def GR64_NOREX : RegisterClass<"X86", [i64], 64,
579
[RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
580
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
581
(GR16_NOREX sub_16bit),
582
(GR32_NOREX sub_32bit)];
583
let MethodProtos = [{
584
iterator allocation_order_end(const MachineFunction &MF) const;
586
let MethodBodies = [{
587
GR64_NOREXClass::iterator
588
GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
589
const TargetMachine &TM = MF.getTarget();
590
const TargetRegisterInfo *RI = TM.getRegisterInfo();
591
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
592
// Does the function dedicate RBP to being a frame ptr?
593
if (RI->hasFP(MF) || MFI->getReserveFP())
594
// If so, don't allocate RIP, RSP or RBP.
597
// If not, just don't allocate RIP or RSP.
603
// GR32_NOSP - GR32 registers except ESP.
604
def GR32_NOSP : RegisterClass<"X86", [i32], 32,
605
[EAX, ECX, EDX, ESI, EDI, EBX, EBP,
606
R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
607
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
608
let MethodProtos = [{
609
iterator allocation_order_begin(const MachineFunction &MF) const;
610
iterator allocation_order_end(const MachineFunction &MF) const;
612
let MethodBodies = [{
613
static const unsigned X86_GR32_NOSP_AO_64[] = {
614
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
615
X86::R8D, X86::R9D, X86::R10D, X86::R11D,
616
X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
619
GR32_NOSPClass::iterator
620
GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
621
const TargetMachine &TM = MF.getTarget();
622
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
623
if (Subtarget.is64Bit())
624
return X86_GR32_NOSP_AO_64;
629
GR32_NOSPClass::iterator
630
GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
631
const TargetMachine &TM = MF.getTarget();
632
const TargetRegisterInfo *RI = TM.getRegisterInfo();
633
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
634
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
635
if (Subtarget.is64Bit()) {
636
// Does the function dedicate RBP to being a frame ptr?
637
if (RI->hasFP(MF) || MFI->getReserveFP())
638
// If so, don't allocate EBP.
639
return array_endof(X86_GR32_NOSP_AO_64) - 1;
641
// If not, any reg in this class is ok.
642
return array_endof(X86_GR32_NOSP_AO_64);
644
// Does the function dedicate EBP to being a frame ptr?
645
if (RI->hasFP(MF) || MFI->getReserveFP())
646
// If so, don't allocate EBP.
649
// If not, any reg in this class is ok.
656
// GR64_NOSP - GR64 registers except RSP (and RIP).
657
def GR64_NOSP : RegisterClass<"X86", [i64], 64,
658
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
659
RBX, R14, R15, R12, R13, RBP]> {
660
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
662
(GR32_NOSP sub_32bit)];
663
let MethodProtos = [{
664
iterator allocation_order_end(const MachineFunction &MF) const;
666
let MethodBodies = [{
667
GR64_NOSPClass::iterator
668
GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
669
const TargetMachine &TM = MF.getTarget();
670
const TargetRegisterInfo *RI = TM.getRegisterInfo();
671
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
672
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
673
if (!Subtarget.is64Bit())
674
return begin(); // None of these are allocatable in 32-bit.
675
// Does the function dedicate RBP to being a frame ptr?
676
if (RI->hasFP(MF) || MFI->getReserveFP())
677
return end()-1; // If so, don't allocate RBP
679
return end(); // If not, any reg in this class is ok.
684
// GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
685
def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
686
[RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
687
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
688
(GR16_NOREX sub_16bit),
689
(GR32_NOREX sub_32bit)];
690
let MethodProtos = [{
691
iterator allocation_order_end(const MachineFunction &MF) const;
693
let MethodBodies = [{
694
GR64_NOREX_NOSPClass::iterator
695
GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
697
const TargetMachine &TM = MF.getTarget();
698
const TargetRegisterInfo *RI = TM.getRegisterInfo();
699
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
700
// Does the function dedicate RBP to being a frame ptr?
701
if (RI->hasFP(MF) || MFI->getReserveFP())
702
// If so, don't allocate RBP.
705
// If not, any reg in this class is ok.
711
// A class to support the 'A' assembler constraint: EAX then EDX.
712
def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
713
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
714
(GR8_ABCD_H sub_8bit_hi),
715
(GR16_ABCD sub_16bit)];
718
// Scalar SSE2 floating point registers.
719
def FR32 : RegisterClass<"X86", [f32], 32,
720
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
721
XMM8, XMM9, XMM10, XMM11,
722
XMM12, XMM13, XMM14, XMM15]> {
723
let MethodProtos = [{
724
iterator allocation_order_end(const MachineFunction &MF) const;
726
let MethodBodies = [{
728
FR32Class::allocation_order_end(const MachineFunction &MF) const {
729
const TargetMachine &TM = MF.getTarget();
730
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
731
if (!Subtarget.is64Bit())
732
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
739
def FR64 : RegisterClass<"X86", [f64], 64,
740
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
741
XMM8, XMM9, XMM10, XMM11,
742
XMM12, XMM13, XMM14, XMM15]> {
743
let MethodProtos = [{
744
iterator allocation_order_end(const MachineFunction &MF) const;
746
let MethodBodies = [{
748
FR64Class::allocation_order_end(const MachineFunction &MF) const {
749
const TargetMachine &TM = MF.getTarget();
750
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
751
if (!Subtarget.is64Bit())
752
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
760
// FIXME: This sets up the floating point register files as though they are f64
761
// values, though they really are f80 values. This will cause us to spill
762
// values as 64-bit quantities instead of 80-bit quantities, which is much much
763
// faster on common hardware. In reality, this should be controlled by a
764
// command line option or something.
766
def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
767
def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
768
def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
770
// Floating point stack registers (these are not allocatable by the
771
// register allocator - the floating point stackifier is responsible
772
// for transforming FPn allocations to STn registers)
773
def RST : RegisterClass<"X86", [f80, f64, f32], 32,
774
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
775
let MethodProtos = [{
776
iterator allocation_order_end(const MachineFunction &MF) const;
778
let MethodBodies = [{
780
RSTClass::allocation_order_end(const MachineFunction &MF) const {
786
// Generic vector registers: VR64 and VR128.
787
def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
788
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
789
def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
790
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
791
XMM8, XMM9, XMM10, XMM11,
792
XMM12, XMM13, XMM14, XMM15]> {
793
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
795
let MethodProtos = [{
796
iterator allocation_order_end(const MachineFunction &MF) const;
798
let MethodBodies = [{
800
VR128Class::allocation_order_end(const MachineFunction &MF) const {
801
const TargetMachine &TM = MF.getTarget();
802
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
803
if (!Subtarget.is64Bit())
804
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
811
def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
812
[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
813
YMM8, YMM9, YMM10, YMM11,
814
YMM12, YMM13, YMM14, YMM15]> {
815
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
817
let MethodProtos = [{
818
iterator allocation_order_end(const MachineFunction &MF) const;
820
let MethodBodies = [{
822
VR256Class::allocation_order_end(const MachineFunction &MF) const {
823
const TargetMachine &TM = MF.getTarget();
824
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
825
if (!Subtarget.is64Bit())
826
return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
833
// Status flags registers.
834
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
835
let CopyCost = -1; // Don't allow copying of status registers.
837
// EFLAGS is not allocatable.
838
let MethodProtos = [{
839
iterator allocation_order_end(const MachineFunction &MF) const;
841
let MethodBodies = [{
843
CCRClass::allocation_order_end(const MachineFunction &MF) const {
844
return allocation_order_begin(MF);
added
removed
libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.td
