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//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This implements the TargetLowering class.
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
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bool isLocal = GV->hasLocalLinkage();
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bool isDeclaration = GV->isDeclaration();
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// FIXME: what should we do for protected and internal visibility?
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// For variables, is internal different from hidden?
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bool isHidden = GV->hasHiddenVisibility();
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if (reloc == Reloc::PIC_) {
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if (isLocal || isHidden)
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return TLSModel::LocalDynamic;
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return TLSModel::GeneralDynamic;
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if (!isDeclaration || isHidden)
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return TLSModel::LocalExec;
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return TLSModel::InitialExec;
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/// InitLibcallNames - Set default libcall names.
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static void InitLibcallNames(const char **Names) {
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Names[RTLIB::SHL_I16] = "__ashlhi3";
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Names[RTLIB::SHL_I32] = "__ashlsi3";
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Names[RTLIB::SHL_I64] = "__ashldi3";
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Names[RTLIB::SHL_I128] = "__ashlti3";
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Names[RTLIB::SRL_I16] = "__lshrhi3";
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Names[RTLIB::SRL_I32] = "__lshrsi3";
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Names[RTLIB::SRL_I64] = "__lshrdi3";
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Names[RTLIB::SRL_I128] = "__lshrti3";
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Names[RTLIB::SRA_I16] = "__ashrhi3";
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Names[RTLIB::SRA_I32] = "__ashrsi3";
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Names[RTLIB::SRA_I64] = "__ashrdi3";
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Names[RTLIB::SRA_I128] = "__ashrti3";
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Names[RTLIB::MUL_I8] = "__mulqi3";
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Names[RTLIB::MUL_I16] = "__mulhi3";
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Names[RTLIB::MUL_I32] = "__mulsi3";
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Names[RTLIB::MUL_I64] = "__muldi3";
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Names[RTLIB::MUL_I128] = "__multi3";
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Names[RTLIB::SDIV_I8] = "__divqi3";
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Names[RTLIB::SDIV_I16] = "__divhi3";
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Names[RTLIB::SDIV_I32] = "__divsi3";
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Names[RTLIB::SDIV_I64] = "__divdi3";
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Names[RTLIB::SDIV_I128] = "__divti3";
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Names[RTLIB::UDIV_I8] = "__udivqi3";
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Names[RTLIB::UDIV_I16] = "__udivhi3";
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Names[RTLIB::UDIV_I32] = "__udivsi3";
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Names[RTLIB::UDIV_I64] = "__udivdi3";
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Names[RTLIB::UDIV_I128] = "__udivti3";
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Names[RTLIB::SREM_I8] = "__modqi3";
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Names[RTLIB::SREM_I16] = "__modhi3";
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Names[RTLIB::SREM_I32] = "__modsi3";
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Names[RTLIB::SREM_I64] = "__moddi3";
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Names[RTLIB::SREM_I128] = "__modti3";
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Names[RTLIB::UREM_I8] = "__umodqi3";
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Names[RTLIB::UREM_I16] = "__umodhi3";
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Names[RTLIB::UREM_I32] = "__umodsi3";
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Names[RTLIB::UREM_I64] = "__umoddi3";
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Names[RTLIB::UREM_I128] = "__umodti3";
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Names[RTLIB::NEG_I32] = "__negsi2";
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Names[RTLIB::NEG_I64] = "__negdi2";
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Names[RTLIB::ADD_F32] = "__addsf3";
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Names[RTLIB::ADD_F64] = "__adddf3";
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Names[RTLIB::ADD_F80] = "__addxf3";
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Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
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Names[RTLIB::SUB_F32] = "__subsf3";
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Names[RTLIB::SUB_F64] = "__subdf3";
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Names[RTLIB::SUB_F80] = "__subxf3";
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Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
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Names[RTLIB::MUL_F32] = "__mulsf3";
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Names[RTLIB::MUL_F64] = "__muldf3";
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Names[RTLIB::MUL_F80] = "__mulxf3";
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Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
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Names[RTLIB::DIV_F32] = "__divsf3";
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Names[RTLIB::DIV_F64] = "__divdf3";
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Names[RTLIB::DIV_F80] = "__divxf3";
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Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
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Names[RTLIB::REM_F32] = "fmodf";
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Names[RTLIB::REM_F64] = "fmod";
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Names[RTLIB::REM_F80] = "fmodl";
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Names[RTLIB::REM_PPCF128] = "fmodl";
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Names[RTLIB::POWI_F32] = "__powisf2";
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Names[RTLIB::POWI_F64] = "__powidf2";
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Names[RTLIB::POWI_F80] = "__powixf2";
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Names[RTLIB::POWI_PPCF128] = "__powitf2";
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Names[RTLIB::SQRT_F32] = "sqrtf";
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Names[RTLIB::SQRT_F64] = "sqrt";
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Names[RTLIB::SQRT_F80] = "sqrtl";
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Names[RTLIB::SQRT_PPCF128] = "sqrtl";
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Names[RTLIB::LOG_F32] = "logf";
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Names[RTLIB::LOG_F64] = "log";
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Names[RTLIB::LOG_F80] = "logl";
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Names[RTLIB::LOG_PPCF128] = "logl";
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Names[RTLIB::LOG2_F32] = "log2f";
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Names[RTLIB::LOG2_F64] = "log2";
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Names[RTLIB::LOG2_F80] = "log2l";
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Names[RTLIB::LOG2_PPCF128] = "log2l";
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Names[RTLIB::LOG10_F32] = "log10f";
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Names[RTLIB::LOG10_F64] = "log10";
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Names[RTLIB::LOG10_F80] = "log10l";
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Names[RTLIB::LOG10_PPCF128] = "log10l";
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Names[RTLIB::EXP_F32] = "expf";
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Names[RTLIB::EXP_F64] = "exp";
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Names[RTLIB::EXP_F80] = "expl";
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Names[RTLIB::EXP_PPCF128] = "expl";
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Names[RTLIB::EXP2_F32] = "exp2f";
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Names[RTLIB::EXP2_F64] = "exp2";
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Names[RTLIB::EXP2_F80] = "exp2l";
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Names[RTLIB::EXP2_PPCF128] = "exp2l";
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Names[RTLIB::SIN_F32] = "sinf";
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Names[RTLIB::SIN_F64] = "sin";
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Names[RTLIB::SIN_F80] = "sinl";
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Names[RTLIB::SIN_PPCF128] = "sinl";
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Names[RTLIB::COS_F32] = "cosf";
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Names[RTLIB::COS_F64] = "cos";
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Names[RTLIB::COS_F80] = "cosl";
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Names[RTLIB::COS_PPCF128] = "cosl";
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Names[RTLIB::POW_F32] = "powf";
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Names[RTLIB::POW_F64] = "pow";
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Names[RTLIB::POW_F80] = "powl";
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Names[RTLIB::POW_PPCF128] = "powl";
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Names[RTLIB::CEIL_F32] = "ceilf";
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Names[RTLIB::CEIL_F64] = "ceil";
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Names[RTLIB::CEIL_F80] = "ceill";
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Names[RTLIB::CEIL_PPCF128] = "ceill";
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Names[RTLIB::TRUNC_F32] = "truncf";
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Names[RTLIB::TRUNC_F64] = "trunc";
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Names[RTLIB::TRUNC_F80] = "truncl";
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Names[RTLIB::TRUNC_PPCF128] = "truncl";
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Names[RTLIB::RINT_F32] = "rintf";
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Names[RTLIB::RINT_F64] = "rint";
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Names[RTLIB::RINT_F80] = "rintl";
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Names[RTLIB::RINT_PPCF128] = "rintl";
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Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
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Names[RTLIB::NEARBYINT_F64] = "nearbyint";
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Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
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Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
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Names[RTLIB::FLOOR_F32] = "floorf";
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Names[RTLIB::FLOOR_F64] = "floor";
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Names[RTLIB::FLOOR_F80] = "floorl";
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Names[RTLIB::FLOOR_PPCF128] = "floorl";
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Names[RTLIB::COPYSIGN_F32] = "copysignf";
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Names[RTLIB::COPYSIGN_F64] = "copysign";
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Names[RTLIB::COPYSIGN_F80] = "copysignl";
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Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
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Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
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Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
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Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
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Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
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Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
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Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
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Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
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Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
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Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
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Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
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Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
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Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
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Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
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Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
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Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
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Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
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Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
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Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
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Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
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Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
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Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
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Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
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Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
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Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
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Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
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Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
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Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
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Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
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Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
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Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
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Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
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Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
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Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
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Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
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Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
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Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
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Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
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Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
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Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
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Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
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Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
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Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
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Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
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Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
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Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
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Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
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Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
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Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
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Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
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Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
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Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
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Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
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Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
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Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
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Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
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Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
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Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
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Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
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Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
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Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
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Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
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Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
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Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
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Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
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Names[RTLIB::OEQ_F32] = "__eqsf2";
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Names[RTLIB::OEQ_F64] = "__eqdf2";
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Names[RTLIB::UNE_F32] = "__nesf2";
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Names[RTLIB::UNE_F64] = "__nedf2";
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Names[RTLIB::OGE_F32] = "__gesf2";
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Names[RTLIB::OGE_F64] = "__gedf2";
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Names[RTLIB::OLT_F32] = "__ltsf2";
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Names[RTLIB::OLT_F64] = "__ltdf2";
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Names[RTLIB::OLE_F32] = "__lesf2";
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Names[RTLIB::OLE_F64] = "__ledf2";
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Names[RTLIB::OGT_F32] = "__gtsf2";
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Names[RTLIB::OGT_F64] = "__gtdf2";
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Names[RTLIB::UO_F32] = "__unordsf2";
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Names[RTLIB::UO_F64] = "__unorddf2";
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Names[RTLIB::O_F32] = "__unordsf2";
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Names[RTLIB::O_F64] = "__unorddf2";
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Names[RTLIB::MEMCPY] = "memcpy";
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Names[RTLIB::MEMMOVE] = "memmove";
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Names[RTLIB::MEMSET] = "memset";
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Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
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Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
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Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
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Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
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Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
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Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
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Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
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Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
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Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
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Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
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Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
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Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
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Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
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Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
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Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
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Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
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Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
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Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
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Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
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Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
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Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
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Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
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Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
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Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
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Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
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Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
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Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
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Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
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Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
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Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
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Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
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Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
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Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
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/// InitLibcallCallingConvs - Set default libcall CallingConvs.
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static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
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for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
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CCs[i] = CallingConv::C;
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/// getFPEXT - Return the FPEXT_*_* value for the given types, or
308
/// UNKNOWN_LIBCALL if there is none.
309
RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
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if (OpVT == MVT::f32) {
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if (RetVT == MVT::f64)
312
return FPEXT_F32_F64;
315
return UNKNOWN_LIBCALL;
318
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
319
/// UNKNOWN_LIBCALL if there is none.
320
RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
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if (RetVT == MVT::f32) {
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if (OpVT == MVT::f64)
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return FPROUND_F64_F32;
324
if (OpVT == MVT::f80)
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return FPROUND_F80_F32;
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if (OpVT == MVT::ppcf128)
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return FPROUND_PPCF128_F32;
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} else if (RetVT == MVT::f64) {
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if (OpVT == MVT::f80)
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return FPROUND_F80_F64;
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if (OpVT == MVT::ppcf128)
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return FPROUND_PPCF128_F64;
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return UNKNOWN_LIBCALL;
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/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
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/// UNKNOWN_LIBCALL if there is none.
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RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
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if (OpVT == MVT::f32) {
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if (RetVT == MVT::i8)
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return FPTOSINT_F32_I8;
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if (RetVT == MVT::i16)
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return FPTOSINT_F32_I16;
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if (RetVT == MVT::i32)
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return FPTOSINT_F32_I32;
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if (RetVT == MVT::i64)
349
return FPTOSINT_F32_I64;
350
if (RetVT == MVT::i128)
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return FPTOSINT_F32_I128;
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} else if (OpVT == MVT::f64) {
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if (RetVT == MVT::i8)
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return FPTOSINT_F64_I8;
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if (RetVT == MVT::i16)
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return FPTOSINT_F64_I16;
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if (RetVT == MVT::i32)
358
return FPTOSINT_F64_I32;
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if (RetVT == MVT::i64)
360
return FPTOSINT_F64_I64;
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if (RetVT == MVT::i128)
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return FPTOSINT_F64_I128;
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} else if (OpVT == MVT::f80) {
364
if (RetVT == MVT::i32)
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return FPTOSINT_F80_I32;
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if (RetVT == MVT::i64)
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return FPTOSINT_F80_I64;
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if (RetVT == MVT::i128)
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return FPTOSINT_F80_I128;
370
} else if (OpVT == MVT::ppcf128) {
371
if (RetVT == MVT::i32)
372
return FPTOSINT_PPCF128_I32;
373
if (RetVT == MVT::i64)
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return FPTOSINT_PPCF128_I64;
375
if (RetVT == MVT::i128)
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return FPTOSINT_PPCF128_I128;
378
return UNKNOWN_LIBCALL;
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/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
382
/// UNKNOWN_LIBCALL if there is none.
383
RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
384
if (OpVT == MVT::f32) {
385
if (RetVT == MVT::i8)
386
return FPTOUINT_F32_I8;
387
if (RetVT == MVT::i16)
388
return FPTOUINT_F32_I16;
389
if (RetVT == MVT::i32)
390
return FPTOUINT_F32_I32;
391
if (RetVT == MVT::i64)
392
return FPTOUINT_F32_I64;
393
if (RetVT == MVT::i128)
394
return FPTOUINT_F32_I128;
395
} else if (OpVT == MVT::f64) {
396
if (RetVT == MVT::i8)
397
return FPTOUINT_F64_I8;
398
if (RetVT == MVT::i16)
399
return FPTOUINT_F64_I16;
400
if (RetVT == MVT::i32)
401
return FPTOUINT_F64_I32;
402
if (RetVT == MVT::i64)
403
return FPTOUINT_F64_I64;
404
if (RetVT == MVT::i128)
405
return FPTOUINT_F64_I128;
406
} else if (OpVT == MVT::f80) {
407
if (RetVT == MVT::i32)
408
return FPTOUINT_F80_I32;
409
if (RetVT == MVT::i64)
410
return FPTOUINT_F80_I64;
411
if (RetVT == MVT::i128)
412
return FPTOUINT_F80_I128;
413
} else if (OpVT == MVT::ppcf128) {
414
if (RetVT == MVT::i32)
415
return FPTOUINT_PPCF128_I32;
416
if (RetVT == MVT::i64)
417
return FPTOUINT_PPCF128_I64;
418
if (RetVT == MVT::i128)
419
return FPTOUINT_PPCF128_I128;
421
return UNKNOWN_LIBCALL;
424
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
425
/// UNKNOWN_LIBCALL if there is none.
426
RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
427
if (OpVT == MVT::i32) {
428
if (RetVT == MVT::f32)
429
return SINTTOFP_I32_F32;
430
else if (RetVT == MVT::f64)
431
return SINTTOFP_I32_F64;
432
else if (RetVT == MVT::f80)
433
return SINTTOFP_I32_F80;
434
else if (RetVT == MVT::ppcf128)
435
return SINTTOFP_I32_PPCF128;
436
} else if (OpVT == MVT::i64) {
437
if (RetVT == MVT::f32)
438
return SINTTOFP_I64_F32;
439
else if (RetVT == MVT::f64)
440
return SINTTOFP_I64_F64;
441
else if (RetVT == MVT::f80)
442
return SINTTOFP_I64_F80;
443
else if (RetVT == MVT::ppcf128)
444
return SINTTOFP_I64_PPCF128;
445
} else if (OpVT == MVT::i128) {
446
if (RetVT == MVT::f32)
447
return SINTTOFP_I128_F32;
448
else if (RetVT == MVT::f64)
449
return SINTTOFP_I128_F64;
450
else if (RetVT == MVT::f80)
451
return SINTTOFP_I128_F80;
452
else if (RetVT == MVT::ppcf128)
453
return SINTTOFP_I128_PPCF128;
455
return UNKNOWN_LIBCALL;
458
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
459
/// UNKNOWN_LIBCALL if there is none.
460
RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
461
if (OpVT == MVT::i32) {
462
if (RetVT == MVT::f32)
463
return UINTTOFP_I32_F32;
464
else if (RetVT == MVT::f64)
465
return UINTTOFP_I32_F64;
466
else if (RetVT == MVT::f80)
467
return UINTTOFP_I32_F80;
468
else if (RetVT == MVT::ppcf128)
469
return UINTTOFP_I32_PPCF128;
470
} else if (OpVT == MVT::i64) {
471
if (RetVT == MVT::f32)
472
return UINTTOFP_I64_F32;
473
else if (RetVT == MVT::f64)
474
return UINTTOFP_I64_F64;
475
else if (RetVT == MVT::f80)
476
return UINTTOFP_I64_F80;
477
else if (RetVT == MVT::ppcf128)
478
return UINTTOFP_I64_PPCF128;
479
} else if (OpVT == MVT::i128) {
480
if (RetVT == MVT::f32)
481
return UINTTOFP_I128_F32;
482
else if (RetVT == MVT::f64)
483
return UINTTOFP_I128_F64;
484
else if (RetVT == MVT::f80)
485
return UINTTOFP_I128_F80;
486
else if (RetVT == MVT::ppcf128)
487
return UINTTOFP_I128_PPCF128;
489
return UNKNOWN_LIBCALL;
492
/// InitCmpLibcallCCs - Set default comparison libcall CC.
494
static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
495
memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
496
CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
497
CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
498
CCs[RTLIB::UNE_F32] = ISD::SETNE;
499
CCs[RTLIB::UNE_F64] = ISD::SETNE;
500
CCs[RTLIB::OGE_F32] = ISD::SETGE;
501
CCs[RTLIB::OGE_F64] = ISD::SETGE;
502
CCs[RTLIB::OLT_F32] = ISD::SETLT;
503
CCs[RTLIB::OLT_F64] = ISD::SETLT;
504
CCs[RTLIB::OLE_F32] = ISD::SETLE;
505
CCs[RTLIB::OLE_F64] = ISD::SETLE;
506
CCs[RTLIB::OGT_F32] = ISD::SETGT;
507
CCs[RTLIB::OGT_F64] = ISD::SETGT;
508
CCs[RTLIB::UO_F32] = ISD::SETNE;
509
CCs[RTLIB::UO_F64] = ISD::SETNE;
510
CCs[RTLIB::O_F32] = ISD::SETEQ;
511
CCs[RTLIB::O_F64] = ISD::SETEQ;
514
/// NOTE: The constructor takes ownership of TLOF.
515
TargetLowering::TargetLowering(const TargetMachine &tm,
516
const TargetLoweringObjectFile *tlof)
517
: TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
518
// All operations default to being supported.
519
memset(OpActions, 0, sizeof(OpActions));
520
memset(LoadExtActions, 0, sizeof(LoadExtActions));
521
memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
522
memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
523
memset(CondCodeActions, 0, sizeof(CondCodeActions));
525
// Set default actions for various operations.
526
for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
527
// Default all indexed load / store to expand.
528
for (unsigned IM = (unsigned)ISD::PRE_INC;
529
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
530
setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
531
setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
534
// These operations default to expand.
535
setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
536
setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
539
// Most targets ignore the @llvm.prefetch intrinsic.
540
setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
542
// ConstantFP nodes default to expand. Targets can either change this to
543
// Legal, in which case all fp constants are legal, or use isFPImmLegal()
544
// to optimize expansions for certain constants.
545
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
546
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
547
setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
549
// These library functions default to expand.
550
setOperationAction(ISD::FLOG , MVT::f64, Expand);
551
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
552
setOperationAction(ISD::FLOG10,MVT::f64, Expand);
553
setOperationAction(ISD::FEXP , MVT::f64, Expand);
554
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
555
setOperationAction(ISD::FLOG , MVT::f32, Expand);
556
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
557
setOperationAction(ISD::FLOG10,MVT::f32, Expand);
558
setOperationAction(ISD::FEXP , MVT::f32, Expand);
559
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
561
// Default ISD::TRAP to expand (which turns it into abort).
562
setOperationAction(ISD::TRAP, MVT::Other, Expand);
564
IsLittleEndian = TD->isLittleEndian();
565
ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
566
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
567
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
568
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
569
benefitFromCodePlacementOpt = false;
570
UseUnderscoreSetJmp = false;
571
UseUnderscoreLongJmp = false;
572
SelectIsExpensive = false;
573
IntDivIsCheap = false;
574
Pow2DivIsCheap = false;
575
StackPointerRegisterToSaveRestore = 0;
576
ExceptionPointerRegister = 0;
577
ExceptionSelectorRegister = 0;
578
BooleanContents = UndefinedBooleanContent;
579
SchedPreferenceInfo = Sched::Latency;
581
JumpBufAlignment = 0;
582
PrefLoopAlignment = 0;
583
MinStackArgumentAlignment = 1;
584
ShouldFoldAtomicFences = false;
586
InitLibcallNames(LibcallRoutineNames);
587
InitCmpLibcallCCs(CmpLibcallCCs);
588
InitLibcallCallingConvs(LibcallCallingConvs);
591
TargetLowering::~TargetLowering() {
595
/// canOpTrap - Returns true if the operation can trap for the value type.
596
/// VT must be a legal type.
597
bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
598
assert(isTypeLegal(VT));
613
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
614
unsigned &NumIntermediates,
616
TargetLowering *TLI) {
617
// Figure out the right, legal destination reg to copy into.
618
unsigned NumElts = VT.getVectorNumElements();
619
MVT EltTy = VT.getVectorElementType();
621
unsigned NumVectorRegs = 1;
623
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
624
// could break down into LHS/RHS like LegalizeDAG does.
625
if (!isPowerOf2_32(NumElts)) {
626
NumVectorRegs = NumElts;
630
// Divide the input until we get to a supported size. This will always
631
// end with a scalar if the target doesn't support vectors.
632
while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
637
NumIntermediates = NumVectorRegs;
639
MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
640
if (!TLI->isTypeLegal(NewVT))
642
IntermediateVT = NewVT;
644
EVT DestVT = TLI->getRegisterType(NewVT);
646
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
647
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
649
// Otherwise, promotion or legal types use the same number of registers as
650
// the vector decimated to the appropriate level.
651
return NumVectorRegs;
654
/// isLegalRC - Return true if the value types that can be represented by the
655
/// specified register class are all legal.
656
bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
657
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
665
/// hasLegalSuperRegRegClasses - Return true if the specified register class
666
/// has one or more super-reg register classes that are legal.
668
TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
669
if (*RC->superregclasses_begin() == 0)
671
for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
672
E = RC->superregclasses_end(); I != E; ++I) {
673
const TargetRegisterClass *RRC = *I;
680
/// findRepresentativeClass - Return the largest legal super-reg register class
681
/// of the register class for the specified type and its associated "cost".
682
std::pair<const TargetRegisterClass*, uint8_t>
683
TargetLowering::findRepresentativeClass(EVT VT) const {
684
const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
686
return std::make_pair(RC, 0);
687
const TargetRegisterClass *BestRC = RC;
688
for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
689
E = RC->superregclasses_end(); I != E; ++I) {
690
const TargetRegisterClass *RRC = *I;
691
if (RRC->isASubClass() || !isLegalRC(RRC))
693
if (!hasLegalSuperRegRegClasses(RRC))
694
return std::make_pair(RRC, 1);
697
return std::make_pair(BestRC, 1);
701
/// computeRegisterProperties - Once all of the register classes are added,
702
/// this allows us to compute derived properties we expose.
703
void TargetLowering::computeRegisterProperties() {
704
assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
705
"Too many value types for ValueTypeActions to hold!");
707
// Everything defaults to needing one register.
708
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
709
NumRegistersForVT[i] = 1;
710
RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
712
// ...except isVoid, which doesn't need any registers.
713
NumRegistersForVT[MVT::isVoid] = 0;
715
// Find the largest integer register class.
716
unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
717
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
718
assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
720
// Every integer value type larger than this largest register takes twice as
721
// many registers to represent as the previous ValueType.
722
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
723
EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
724
if (!ExpandedVT.isInteger())
726
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
727
RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
728
TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
729
ValueTypeActions.setTypeAction(ExpandedVT, Expand);
732
// Inspect all of the ValueType's smaller than the largest integer
733
// register to see which ones need promotion.
734
unsigned LegalIntReg = LargestIntReg;
735
for (unsigned IntReg = LargestIntReg - 1;
736
IntReg >= (unsigned)MVT::i1; --IntReg) {
737
EVT IVT = (MVT::SimpleValueType)IntReg;
738
if (isTypeLegal(IVT)) {
739
LegalIntReg = IntReg;
741
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
742
(MVT::SimpleValueType)LegalIntReg;
743
ValueTypeActions.setTypeAction(IVT, Promote);
747
// ppcf128 type is really two f64's.
748
if (!isTypeLegal(MVT::ppcf128)) {
749
NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
750
RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
751
TransformToType[MVT::ppcf128] = MVT::f64;
752
ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
755
// Decide how to handle f64. If the target does not have native f64 support,
756
// expand it to i64 and we will be generating soft float library calls.
757
if (!isTypeLegal(MVT::f64)) {
758
NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
759
RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
760
TransformToType[MVT::f64] = MVT::i64;
761
ValueTypeActions.setTypeAction(MVT::f64, Expand);
764
// Decide how to handle f32. If the target does not have native support for
765
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
766
if (!isTypeLegal(MVT::f32)) {
767
if (isTypeLegal(MVT::f64)) {
768
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
769
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
770
TransformToType[MVT::f32] = MVT::f64;
771
ValueTypeActions.setTypeAction(MVT::f32, Promote);
773
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
774
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
775
TransformToType[MVT::f32] = MVT::i32;
776
ValueTypeActions.setTypeAction(MVT::f32, Expand);
780
// Loop over all of the vector value types to see which need transformations.
781
for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
782
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
783
MVT VT = (MVT::SimpleValueType)i;
784
if (isTypeLegal(VT)) continue;
786
// Determine if there is a legal wider type. If so, we should promote to
787
// that wider vector type.
788
EVT EltVT = VT.getVectorElementType();
789
unsigned NElts = VT.getVectorNumElements();
791
bool IsLegalWiderType = false;
792
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
793
EVT SVT = (MVT::SimpleValueType)nVT;
794
if (SVT.getVectorElementType() == EltVT &&
795
SVT.getVectorNumElements() > NElts &&
796
isTypeSynthesizable(SVT)) {
797
TransformToType[i] = SVT;
798
RegisterTypeForVT[i] = SVT;
799
NumRegistersForVT[i] = 1;
800
ValueTypeActions.setTypeAction(VT, Promote);
801
IsLegalWiderType = true;
805
if (IsLegalWiderType) continue;
810
unsigned NumIntermediates;
811
NumRegistersForVT[i] =
812
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
814
RegisterTypeForVT[i] = RegisterVT;
816
EVT NVT = VT.getPow2VectorType();
818
// Type is already a power of 2. The default action is to split.
819
TransformToType[i] = MVT::Other;
820
ValueTypeActions.setTypeAction(VT, Expand);
822
TransformToType[i] = NVT;
823
ValueTypeActions.setTypeAction(VT, Promote);
827
// Determine the 'representative' register class for each value type.
828
// An representative register class is the largest (meaning one which is
829
// not a sub-register class / subreg register class) legal register class for
830
// a group of value types. For example, on i386, i8, i16, and i32
831
// representative would be GR32; while on x86_64 it's GR64.
832
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
833
const TargetRegisterClass* RRC;
835
tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
836
RepRegClassForVT[i] = RRC;
837
RepRegClassCostForVT[i] = Cost;
841
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
846
MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
847
return PointerTy.SimpleTy;
850
MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
851
return MVT::i32; // return the default value
854
/// getVectorTypeBreakdown - Vector types are broken down into some number of
855
/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
856
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
857
/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
859
/// This method returns the number of registers needed, and the VT for each
860
/// register. It also returns the VT and quantity of the intermediate values
861
/// before they are promoted/expanded.
863
unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
865
unsigned &NumIntermediates,
866
EVT &RegisterVT) const {
867
unsigned NumElts = VT.getVectorNumElements();
869
// If there is a wider vector type with the same element type as this one,
870
// we should widen to that legal vector type. This handles things like
871
// <2 x float> -> <4 x float>.
872
if (NumElts != 1 && getTypeAction(VT) == Promote) {
873
RegisterVT = getTypeToTransformTo(Context, VT);
874
if (isTypeLegal(RegisterVT)) {
875
IntermediateVT = RegisterVT;
876
NumIntermediates = 1;
881
// Figure out the right, legal destination reg to copy into.
882
EVT EltTy = VT.getVectorElementType();
884
unsigned NumVectorRegs = 1;
886
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
887
// could break down into LHS/RHS like LegalizeDAG does.
888
if (!isPowerOf2_32(NumElts)) {
889
NumVectorRegs = NumElts;
893
// Divide the input until we get to a supported size. This will always
894
// end with a scalar if the target doesn't support vectors.
895
while (NumElts > 1 && !isTypeLegal(
896
EVT::getVectorVT(Context, EltTy, NumElts))) {
901
NumIntermediates = NumVectorRegs;
903
EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
904
if (!isTypeLegal(NewVT))
906
IntermediateVT = NewVT;
908
EVT DestVT = getRegisterType(Context, NewVT);
910
if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
911
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
913
// Otherwise, promotion or legal types use the same number of registers as
914
// the vector decimated to the appropriate level.
915
return NumVectorRegs;
918
/// Get the EVTs and ArgFlags collections that represent the legalized return
919
/// type of the given function. This does not require a DAG or a return value,
920
/// and is suitable for use before any DAGs for the function are constructed.
921
/// TODO: Move this out of TargetLowering.cpp.
922
void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
923
SmallVectorImpl<ISD::OutputArg> &Outs,
924
const TargetLowering &TLI,
925
SmallVectorImpl<uint64_t> *Offsets) {
926
SmallVector<EVT, 4> ValueVTs;
927
ComputeValueVTs(TLI, ReturnType, ValueVTs);
928
unsigned NumValues = ValueVTs.size();
929
if (NumValues == 0) return;
932
for (unsigned j = 0, f = NumValues; j != f; ++j) {
933
EVT VT = ValueVTs[j];
934
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
936
if (attr & Attribute::SExt)
937
ExtendKind = ISD::SIGN_EXTEND;
938
else if (attr & Attribute::ZExt)
939
ExtendKind = ISD::ZERO_EXTEND;
941
// FIXME: C calling convention requires the return type to be promoted to
942
// at least 32-bit. But this is not necessary for non-C calling
943
// conventions. The frontend should mark functions whose return values
944
// require promoting with signext or zeroext attributes.
945
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
946
EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
947
if (VT.bitsLT(MinVT))
951
unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
952
EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
953
unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
954
PartVT.getTypeForEVT(ReturnType->getContext()));
956
// 'inreg' on function refers to return value
957
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
958
if (attr & Attribute::InReg)
961
// Propagate extension type if any
962
if (attr & Attribute::SExt)
964
else if (attr & Attribute::ZExt)
967
for (unsigned i = 0; i < NumParts; ++i) {
968
Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
970
Offsets->push_back(Offset);
977
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
978
/// function arguments in the caller parameter area. This is the actual
979
/// alignment, not its logarithm.
980
unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
981
return TD->getCallFrameTypeAlignment(Ty);
984
/// getJumpTableEncoding - Return the entry encoding for a jump table in the
985
/// current function. The returned value is a member of the
986
/// MachineJumpTableInfo::JTEntryKind enum.
987
unsigned TargetLowering::getJumpTableEncoding() const {
988
// In non-pic modes, just use the address of a block.
989
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
990
return MachineJumpTableInfo::EK_BlockAddress;
992
// In PIC mode, if the target supports a GPRel32 directive, use it.
993
if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
994
return MachineJumpTableInfo::EK_GPRel32BlockAddress;
996
// Otherwise, use a label difference.
997
return MachineJumpTableInfo::EK_LabelDifference32;
1000
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1001
SelectionDAG &DAG) const {
1002
// If our PIC model is GP relative, use the global offset table as the base.
1003
if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1004
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1008
/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1009
/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1012
TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1013
unsigned JTI,MCContext &Ctx) const{
1014
// The normal PIC reloc base is the label at the start of the jump table.
1015
return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1019
TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1020
// Assume that everything is safe in static mode.
1021
if (getTargetMachine().getRelocationModel() == Reloc::Static)
1024
// In dynamic-no-pic mode, assume that known defined values are safe.
1025
if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1027
!GA->getGlobal()->isDeclaration() &&
1028
!GA->getGlobal()->isWeakForLinker())
1031
// Otherwise assume nothing is safe.
1035
//===----------------------------------------------------------------------===//
1036
// Optimization Methods
1037
//===----------------------------------------------------------------------===//
1039
/// ShrinkDemandedConstant - Check to see if the specified operand of the
1040
/// specified instruction is a constant integer. If so, check to see if there
1041
/// are any bits set in the constant that are not demanded. If so, shrink the
1042
/// constant and return true.
1043
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1044
const APInt &Demanded) {
1045
DebugLoc dl = Op.getDebugLoc();
1047
// FIXME: ISD::SELECT, ISD::SELECT_CC
1048
switch (Op.getOpcode()) {
1053
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1054
if (!C) return false;
1056
if (Op.getOpcode() == ISD::XOR &&
1057
(C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1060
// if we can expand it to have all bits set, do it
1061
if (C->getAPIntValue().intersects(~Demanded)) {
1062
EVT VT = Op.getValueType();
1063
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1064
DAG.getConstant(Demanded &
1067
return CombineTo(Op, New);
1077
/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1078
/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1079
/// cast, but it could be generalized for targets with other types of
1080
/// implicit widening casts.
1082
TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1084
const APInt &Demanded,
1086
assert(Op.getNumOperands() == 2 &&
1087
"ShrinkDemandedOp only supports binary operators!");
1088
assert(Op.getNode()->getNumValues() == 1 &&
1089
"ShrinkDemandedOp only supports nodes with one result!");
1091
// Don't do this if the node has another user, which may require the
1093
if (!Op.getNode()->hasOneUse())
1096
// Search for the smallest integer type with free casts to and from
1097
// Op's type. For expedience, just check power-of-2 integer types.
1098
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1099
unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1100
if (!isPowerOf2_32(SmallVTBits))
1101
SmallVTBits = NextPowerOf2(SmallVTBits);
1102
for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1103
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1104
if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1105
TLI.isZExtFree(SmallVT, Op.getValueType())) {
1106
// We found a type with free casts.
1107
SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1108
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1109
Op.getNode()->getOperand(0)),
1110
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1111
Op.getNode()->getOperand(1)));
1112
SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1113
return CombineTo(Op, Z);
1119
/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1120
/// DemandedMask bits of the result of Op are ever used downstream. If we can
1121
/// use this information to simplify Op, create a new simplified DAG node and
1122
/// return true, returning the original and new nodes in Old and New. Otherwise,
1123
/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1124
/// the expression (used to simplify the caller). The KnownZero/One bits may
1125
/// only be accurate for those bits in the DemandedMask.
1126
bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1127
const APInt &DemandedMask,
1130
TargetLoweringOpt &TLO,
1131
unsigned Depth) const {
1132
unsigned BitWidth = DemandedMask.getBitWidth();
1133
assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1134
"Mask size mismatches value type size!");
1135
APInt NewMask = DemandedMask;
1136
DebugLoc dl = Op.getDebugLoc();
1138
// Don't know anything.
1139
KnownZero = KnownOne = APInt(BitWidth, 0);
1141
// Other users may use these bits.
1142
if (!Op.getNode()->hasOneUse()) {
1144
// If not at the root, Just compute the KnownZero/KnownOne bits to
1145
// simplify things downstream.
1146
TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1149
// If this is the root being simplified, allow it to have multiple uses,
1150
// just set the NewMask to all bits.
1151
NewMask = APInt::getAllOnesValue(BitWidth);
1152
} else if (DemandedMask == 0) {
1153
// Not demanding any bits from Op.
1154
if (Op.getOpcode() != ISD::UNDEF)
1155
return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1157
} else if (Depth == 6) { // Limit search depth.
1161
APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1162
switch (Op.getOpcode()) {
1164
// We know all of the bits for a constant!
1165
KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1166
KnownZero = ~KnownOne & NewMask;
1167
return false; // Don't fall through, will infinitely loop.
1169
// If the RHS is a constant, check to see if the LHS would be zero without
1170
// using the bits from the RHS. Below, we use knowledge about the RHS to
1171
// simplify the LHS, here we're using information from the LHS to simplify
1173
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1174
APInt LHSZero, LHSOne;
1175
TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1176
LHSZero, LHSOne, Depth+1);
1177
// If the LHS already has zeros where RHSC does, this and is dead.
1178
if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1179
return TLO.CombineTo(Op, Op.getOperand(0));
1180
// If any of the set bits in the RHS are known zero on the LHS, shrink
1182
if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1186
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1187
KnownOne, TLO, Depth+1))
1189
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1190
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1191
KnownZero2, KnownOne2, TLO, Depth+1))
1193
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1195
// If all of the demanded bits are known one on one side, return the other.
1196
// These bits cannot contribute to the result of the 'and'.
1197
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1198
return TLO.CombineTo(Op, Op.getOperand(0));
1199
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1200
return TLO.CombineTo(Op, Op.getOperand(1));
1201
// If all of the demanded bits in the inputs are known zeros, return zero.
1202
if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1203
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1204
// If the RHS is a constant, see if we can simplify it.
1205
if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1207
// If the operation can be done in a smaller type, do so.
1208
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1211
// Output known-1 bits are only known if set in both the LHS & RHS.
1212
KnownOne &= KnownOne2;
1213
// Output known-0 are known to be clear if zero in either the LHS | RHS.
1214
KnownZero |= KnownZero2;
1217
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1218
KnownOne, TLO, Depth+1))
1220
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1221
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1222
KnownZero2, KnownOne2, TLO, Depth+1))
1224
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1226
// If all of the demanded bits are known zero on one side, return the other.
1227
// These bits cannot contribute to the result of the 'or'.
1228
if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1229
return TLO.CombineTo(Op, Op.getOperand(0));
1230
if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1231
return TLO.CombineTo(Op, Op.getOperand(1));
1232
// If all of the potentially set bits on one side are known to be set on
1233
// the other side, just use the 'other' side.
1234
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1235
return TLO.CombineTo(Op, Op.getOperand(0));
1236
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1237
return TLO.CombineTo(Op, Op.getOperand(1));
1238
// If the RHS is a constant, see if we can simplify it.
1239
if (TLO.ShrinkDemandedConstant(Op, NewMask))
1241
// If the operation can be done in a smaller type, do so.
1242
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1245
// Output known-0 bits are only known if clear in both the LHS & RHS.
1246
KnownZero &= KnownZero2;
1247
// Output known-1 are known to be set if set in either the LHS | RHS.
1248
KnownOne |= KnownOne2;
1251
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1252
KnownOne, TLO, Depth+1))
1254
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1255
if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1256
KnownOne2, TLO, Depth+1))
1258
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1260
// If all of the demanded bits are known zero on one side, return the other.
1261
// These bits cannot contribute to the result of the 'xor'.
1262
if ((KnownZero & NewMask) == NewMask)
1263
return TLO.CombineTo(Op, Op.getOperand(0));
1264
if ((KnownZero2 & NewMask) == NewMask)
1265
return TLO.CombineTo(Op, Op.getOperand(1));
1266
// If the operation can be done in a smaller type, do so.
1267
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1270
// If all of the unknown bits are known to be zero on one side or the other
1271
// (but not both) turn this into an *inclusive* or.
1272
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1273
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1274
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1278
// Output known-0 bits are known if clear or set in both the LHS & RHS.
1279
KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1280
// Output known-1 are known to be set if set in only one of the LHS, RHS.
1281
KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1283
// If all of the demanded bits on one side are known, and all of the set
1284
// bits on that side are also known to be set on the other side, turn this
1285
// into an AND, as we know the bits will be cleared.
1286
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1287
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1288
if ((KnownOne & KnownOne2) == KnownOne) {
1289
EVT VT = Op.getValueType();
1290
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1291
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1292
Op.getOperand(0), ANDC));
1296
// If the RHS is a constant, see if we can simplify it.
1297
// for XOR, we prefer to force bits to 1 if they will make a -1.
1298
// if we can't force bits, try to shrink constant
1299
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1300
APInt Expanded = C->getAPIntValue() | (~NewMask);
1301
// if we can expand it to have all bits set, do it
1302
if (Expanded.isAllOnesValue()) {
1303
if (Expanded != C->getAPIntValue()) {
1304
EVT VT = Op.getValueType();
1305
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1306
TLO.DAG.getConstant(Expanded, VT));
1307
return TLO.CombineTo(Op, New);
1309
// if it already has all the bits set, nothing to change
1310
// but don't shrink either!
1311
} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1316
KnownZero = KnownZeroOut;
1317
KnownOne = KnownOneOut;
1320
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1321
KnownOne, TLO, Depth+1))
1323
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1324
KnownOne2, TLO, Depth+1))
1326
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1327
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1329
// If the operands are constants, see if we can simplify them.
1330
if (TLO.ShrinkDemandedConstant(Op, NewMask))
1333
// Only known if known in both the LHS and RHS.
1334
KnownOne &= KnownOne2;
1335
KnownZero &= KnownZero2;
1337
case ISD::SELECT_CC:
1338
if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1339
KnownOne, TLO, Depth+1))
1341
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1342
KnownOne2, TLO, Depth+1))
1344
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1345
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1347
// If the operands are constants, see if we can simplify them.
1348
if (TLO.ShrinkDemandedConstant(Op, NewMask))
1351
// Only known if known in both the LHS and RHS.
1352
KnownOne &= KnownOne2;
1353
KnownZero &= KnownZero2;
1356
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1357
unsigned ShAmt = SA->getZExtValue();
1358
SDValue InOp = Op.getOperand(0);
1360
// If the shift count is an invalid immediate, don't do anything.
1361
if (ShAmt >= BitWidth)
1364
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1365
// single shift. We can do this if the bottom bits (which are shifted
1366
// out) are never demanded.
1367
if (InOp.getOpcode() == ISD::SRL &&
1368
isa<ConstantSDNode>(InOp.getOperand(1))) {
1369
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1370
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1371
unsigned Opc = ISD::SHL;
1372
int Diff = ShAmt-C1;
1379
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1380
EVT VT = Op.getValueType();
1381
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1382
InOp.getOperand(0), NewSA));
1386
if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1387
KnownZero, KnownOne, TLO, Depth+1))
1390
// Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1391
// are not demanded. This will likely allow the anyext to be folded away.
1392
if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1393
SDValue InnerOp = InOp.getNode()->getOperand(0);
1394
EVT InnerVT = InnerOp.getValueType();
1395
if ((APInt::getHighBitsSet(BitWidth,
1396
BitWidth - InnerVT.getSizeInBits()) &
1397
DemandedMask) == 0 &&
1398
isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1399
EVT ShTy = getShiftAmountTy();
1400
if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1403
TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1404
TLO.DAG.getConstant(ShAmt, ShTy));
1407
TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1412
KnownZero <<= SA->getZExtValue();
1413
KnownOne <<= SA->getZExtValue();
1414
// low bits known zero.
1415
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1419
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1420
EVT VT = Op.getValueType();
1421
unsigned ShAmt = SA->getZExtValue();
1422
unsigned VTSize = VT.getSizeInBits();
1423
SDValue InOp = Op.getOperand(0);
1425
// If the shift count is an invalid immediate, don't do anything.
1426
if (ShAmt >= BitWidth)
1429
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1430
// single shift. We can do this if the top bits (which are shifted out)
1431
// are never demanded.
1432
if (InOp.getOpcode() == ISD::SHL &&
1433
isa<ConstantSDNode>(InOp.getOperand(1))) {
1434
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1435
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1436
unsigned Opc = ISD::SRL;
1437
int Diff = ShAmt-C1;
1444
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1445
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1446
InOp.getOperand(0), NewSA));
1450
// Compute the new bits that are at the top now.
1451
if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1452
KnownZero, KnownOne, TLO, Depth+1))
1454
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1455
KnownZero = KnownZero.lshr(ShAmt);
1456
KnownOne = KnownOne.lshr(ShAmt);
1458
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1459
KnownZero |= HighBits; // High bits known zero.
1463
// If this is an arithmetic shift right and only the low-bit is set, we can
1464
// always convert this into a logical shr, even if the shift amount is
1465
// variable. The low bit of the shift cannot be an input sign bit unless
1466
// the shift amount is >= the size of the datatype, which is undefined.
1467
if (DemandedMask == 1)
1468
return TLO.CombineTo(Op,
1469
TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1470
Op.getOperand(0), Op.getOperand(1)));
1472
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1473
EVT VT = Op.getValueType();
1474
unsigned ShAmt = SA->getZExtValue();
1476
// If the shift count is an invalid immediate, don't do anything.
1477
if (ShAmt >= BitWidth)
1480
APInt InDemandedMask = (NewMask << ShAmt);
1482
// If any of the demanded bits are produced by the sign extension, we also
1483
// demand the input sign bit.
1484
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1485
if (HighBits.intersects(NewMask))
1486
InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1488
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1489
KnownZero, KnownOne, TLO, Depth+1))
1491
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1492
KnownZero = KnownZero.lshr(ShAmt);
1493
KnownOne = KnownOne.lshr(ShAmt);
1495
// Handle the sign bit, adjusted to where it is now in the mask.
1496
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1498
// If the input sign bit is known to be zero, or if none of the top bits
1499
// are demanded, turn this into an unsigned shift right.
1500
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1501
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1504
} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1505
KnownOne |= HighBits;
1509
case ISD::SIGN_EXTEND_INREG: {
1510
EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1512
// Sign extension. Compute the demanded bits in the result that are not
1513
// present in the input.
1515
APInt::getHighBitsSet(BitWidth,
1516
BitWidth - EVT.getScalarType().getSizeInBits());
1518
// If none of the extended bits are demanded, eliminate the sextinreg.
1519
if ((NewBits & NewMask) == 0)
1520
return TLO.CombineTo(Op, Op.getOperand(0));
1522
APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1523
InSignBit.zext(BitWidth);
1524
APInt InputDemandedBits =
1525
APInt::getLowBitsSet(BitWidth,
1526
EVT.getScalarType().getSizeInBits()) &
1529
// Since the sign extended bits are demanded, we know that the sign
1531
InputDemandedBits |= InSignBit;
1533
if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1534
KnownZero, KnownOne, TLO, Depth+1))
1536
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1538
// If the sign bit of the input is known set or clear, then we know the
1539
// top bits of the result.
1541
// If the input sign bit is known zero, convert this into a zero extension.
1542
if (KnownZero.intersects(InSignBit))
1543
return TLO.CombineTo(Op,
1544
TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1546
if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1547
KnownOne |= NewBits;
1548
KnownZero &= ~NewBits;
1549
} else { // Input sign bit unknown
1550
KnownZero &= ~NewBits;
1551
KnownOne &= ~NewBits;
1555
case ISD::ZERO_EXTEND: {
1556
unsigned OperandBitWidth =
1557
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1558
APInt InMask = NewMask;
1559
InMask.trunc(OperandBitWidth);
1561
// If none of the top bits are demanded, convert this into an any_extend.
1563
APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1564
if (!NewBits.intersects(NewMask))
1565
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1569
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1570
KnownZero, KnownOne, TLO, Depth+1))
1572
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1573
KnownZero.zext(BitWidth);
1574
KnownOne.zext(BitWidth);
1575
KnownZero |= NewBits;
1578
case ISD::SIGN_EXTEND: {
1579
EVT InVT = Op.getOperand(0).getValueType();
1580
unsigned InBits = InVT.getScalarType().getSizeInBits();
1581
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1582
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1583
APInt NewBits = ~InMask & NewMask;
1585
// If none of the top bits are demanded, convert this into an any_extend.
1587
return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1591
// Since some of the sign extended bits are demanded, we know that the sign
1593
APInt InDemandedBits = InMask & NewMask;
1594
InDemandedBits |= InSignBit;
1595
InDemandedBits.trunc(InBits);
1597
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1598
KnownOne, TLO, Depth+1))
1600
KnownZero.zext(BitWidth);
1601
KnownOne.zext(BitWidth);
1603
// If the sign bit is known zero, convert this to a zero extend.
1604
if (KnownZero.intersects(InSignBit))
1605
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1609
// If the sign bit is known one, the top bits match.
1610
if (KnownOne.intersects(InSignBit)) {
1611
KnownOne |= NewBits;
1612
KnownZero &= ~NewBits;
1613
} else { // Otherwise, top bits aren't known.
1614
KnownOne &= ~NewBits;
1615
KnownZero &= ~NewBits;
1619
case ISD::ANY_EXTEND: {
1620
unsigned OperandBitWidth =
1621
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1622
APInt InMask = NewMask;
1623
InMask.trunc(OperandBitWidth);
1624
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1625
KnownZero, KnownOne, TLO, Depth+1))
1627
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1628
KnownZero.zext(BitWidth);
1629
KnownOne.zext(BitWidth);
1632
case ISD::TRUNCATE: {
1633
// Simplify the input, using demanded bit information, and compute the known
1634
// zero/one bits live out.
1635
unsigned OperandBitWidth =
1636
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1637
APInt TruncMask = NewMask;
1638
TruncMask.zext(OperandBitWidth);
1639
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1640
KnownZero, KnownOne, TLO, Depth+1))
1642
KnownZero.trunc(BitWidth);
1643
KnownOne.trunc(BitWidth);
1645
// If the input is only used by this truncate, see if we can shrink it based
1646
// on the known demanded bits.
1647
if (Op.getOperand(0).getNode()->hasOneUse()) {
1648
SDValue In = Op.getOperand(0);
1649
switch (In.getOpcode()) {
1652
// Shrink SRL by a constant if none of the high bits shifted in are
1654
if (TLO.LegalTypes() &&
1655
!isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1656
// Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1659
ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1662
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1663
OperandBitWidth - BitWidth);
1664
HighBits = HighBits.lshr(ShAmt->getZExtValue());
1665
HighBits.trunc(BitWidth);
1667
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1668
// None of the shifted in bits are needed. Add a truncate of the
1669
// shift input, then shift it.
1670
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1673
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1682
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1685
case ISD::AssertZext: {
1686
// Demand all the bits of the input that are demanded in the output.
1687
// The low bits are obvious; the high bits are demanded because we're
1688
// asserting that they're zero here.
1689
if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1690
KnownZero, KnownOne, TLO, Depth+1))
1692
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1694
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1695
APInt InMask = APInt::getLowBitsSet(BitWidth,
1696
VT.getSizeInBits());
1697
KnownZero |= ~InMask & NewMask;
1700
case ISD::BIT_CONVERT:
1702
// If this is an FP->Int bitcast and if the sign bit is the only thing that
1703
// is demanded, turn this into a FGETSIGN.
1704
if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1705
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1706
!MVT::isVector(Op.getOperand(0).getValueType())) {
1707
// Only do this xform if FGETSIGN is valid or if before legalize.
1708
if (!TLO.AfterLegalize ||
1709
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1710
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
1711
// place. We expect the SHL to be eliminated by other optimizations.
1712
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1714
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1715
SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1716
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1725
// Add, Sub, and Mul don't demand any bits in positions beyond that
1726
// of the highest bit demanded of them.
1727
APInt LoMask = APInt::getLowBitsSet(BitWidth,
1728
BitWidth - NewMask.countLeadingZeros());
1729
if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1730
KnownOne2, TLO, Depth+1))
1732
if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1733
KnownOne2, TLO, Depth+1))
1735
// See if the operation should be performed at a smaller bit width.
1736
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1741
// Just use ComputeMaskedBits to compute output bits.
1742
TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1746
// If we know the value of all of the demanded bits, return this as a
1748
if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1749
return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1754
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1755
/// in Mask are known to be either zero or one and return them in the
1756
/// KnownZero/KnownOne bitsets.
1757
void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1761
const SelectionDAG &DAG,
1762
unsigned Depth) const {
1763
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1764
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1765
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1766
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1767
"Should use MaskedValueIsZero if you don't know whether Op"
1768
" is a target node!");
1769
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1772
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1773
/// targets that want to expose additional information about sign bits to the
1775
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1776
unsigned Depth) const {
1777
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1778
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1779
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1780
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1781
"Should use ComputeNumSignBits if you don't know whether Op"
1782
" is a target node!");
1786
/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1787
/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1788
/// determine which bit is set.
1790
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1791
// A left-shift of a constant one will have exactly one bit set, because
1792
// shifting the bit off the end is undefined.
1793
if (Val.getOpcode() == ISD::SHL)
1794
if (ConstantSDNode *C =
1795
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1796
if (C->getAPIntValue() == 1)
1799
// Similarly, a right-shift of a constant sign-bit will have exactly
1801
if (Val.getOpcode() == ISD::SRL)
1802
if (ConstantSDNode *C =
1803
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1804
if (C->getAPIntValue().isSignBit())
1807
// More could be done here, though the above checks are enough
1808
// to handle some common cases.
1810
// Fall back to ComputeMaskedBits to catch other known cases.
1811
EVT OpVT = Val.getValueType();
1812
unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1813
APInt Mask = APInt::getAllOnesValue(BitWidth);
1814
APInt KnownZero, KnownOne;
1815
DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1816
return (KnownZero.countPopulation() == BitWidth - 1) &&
1817
(KnownOne.countPopulation() == 1);
1820
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1821
/// and cc. If it is unable to simplify it, return a null SDValue.
1823
TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1824
ISD::CondCode Cond, bool foldBooleans,
1825
DAGCombinerInfo &DCI, DebugLoc dl) const {
1826
SelectionDAG &DAG = DCI.DAG;
1827
LLVMContext &Context = *DAG.getContext();
1829
// These setcc operations always fold.
1833
case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1835
case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1838
if (isa<ConstantSDNode>(N0.getNode())) {
1839
// Ensure that the constant occurs on the RHS, and fold constant
1841
return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1844
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1845
const APInt &C1 = N1C->getAPIntValue();
1847
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1848
// equality comparison, then we're just comparing whether X itself is
1850
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1851
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1852
N0.getOperand(1).getOpcode() == ISD::Constant) {
1854
= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1855
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1856
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1857
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1858
// (srl (ctlz x), 5) == 0 -> X != 0
1859
// (srl (ctlz x), 5) != 1 -> X != 0
1862
// (srl (ctlz x), 5) != 0 -> X == 0
1863
// (srl (ctlz x), 5) == 1 -> X == 0
1866
SDValue Zero = DAG.getConstant(0, N0.getValueType());
1867
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1872
// If the LHS is '(and load, const)', the RHS is 0,
1873
// the test is for equality or unsigned, and all 1 bits of the const are
1874
// in the same partial word, see if we can shorten the load.
1875
if (DCI.isBeforeLegalize() &&
1876
N0.getOpcode() == ISD::AND && C1 == 0 &&
1877
N0.getNode()->hasOneUse() &&
1878
isa<LoadSDNode>(N0.getOperand(0)) &&
1879
N0.getOperand(0).getNode()->hasOneUse() &&
1880
isa<ConstantSDNode>(N0.getOperand(1))) {
1881
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1883
unsigned bestWidth = 0, bestOffset = 0;
1884
if (!Lod->isVolatile() && Lod->isUnindexed()) {
1885
unsigned origWidth = N0.getValueType().getSizeInBits();
1886
unsigned maskWidth = origWidth;
1887
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1888
// 8 bits, but have to be careful...
1889
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1890
origWidth = Lod->getMemoryVT().getSizeInBits();
1892
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1893
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1894
APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1895
for (unsigned offset=0; offset<origWidth/width; offset++) {
1896
if ((newMask & Mask) == Mask) {
1897
if (!TD->isLittleEndian())
1898
bestOffset = (origWidth/width - offset - 1) * (width/8);
1900
bestOffset = (uint64_t)offset * (width/8);
1901
bestMask = Mask.lshr(offset * (width/8) * 8);
1905
newMask = newMask << width;
1910
EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1911
if (newVT.isRound()) {
1912
EVT PtrType = Lod->getOperand(1).getValueType();
1913
SDValue Ptr = Lod->getBasePtr();
1914
if (bestOffset != 0)
1915
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1916
DAG.getConstant(bestOffset, PtrType));
1917
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1918
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1920
Lod->getSrcValueOffset() + bestOffset,
1921
false, false, NewAlign);
1922
return DAG.getSetCC(dl, VT,
1923
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1924
DAG.getConstant(bestMask.trunc(bestWidth),
1926
DAG.getConstant(0LL, newVT), Cond);
1931
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1932
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1933
unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1935
// If the comparison constant has bits in the upper part, the
1936
// zero-extended value could never match.
1937
if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1938
C1.getBitWidth() - InSize))) {
1942
case ISD::SETEQ: return DAG.getConstant(0, VT);
1945
case ISD::SETNE: return DAG.getConstant(1, VT);
1948
// True if the sign bit of C1 is set.
1949
return DAG.getConstant(C1.isNegative(), VT);
1952
// True if the sign bit of C1 isn't set.
1953
return DAG.getConstant(C1.isNonNegative(), VT);
1959
// Otherwise, we can perform the comparison with the low bits.
1967
EVT newVT = N0.getOperand(0).getValueType();
1968
if (DCI.isBeforeLegalizeOps() ||
1969
(isOperationLegal(ISD::SETCC, newVT) &&
1970
getCondCodeAction(Cond, newVT)==Legal))
1971
return DAG.getSetCC(dl, VT, N0.getOperand(0),
1972
DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1977
break; // todo, be more careful with signed comparisons
1979
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1980
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1981
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1982
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1983
EVT ExtDstTy = N0.getValueType();
1984
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1986
// If the constant doesn't fit into the number of bits for the source of
1987
// the sign extension, it is impossible for both sides to be equal.
1988
if (C1.getMinSignedBits() > ExtSrcTyBits)
1989
return DAG.getConstant(Cond == ISD::SETNE, VT);
1992
EVT Op0Ty = N0.getOperand(0).getValueType();
1993
if (Op0Ty == ExtSrcTy) {
1994
ZextOp = N0.getOperand(0);
1996
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1997
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1998
DAG.getConstant(Imm, Op0Ty));
2000
if (!DCI.isCalledByLegalizer())
2001
DCI.AddToWorklist(ZextOp.getNode());
2002
// Otherwise, make this a use of a zext.
2003
return DAG.getSetCC(dl, VT, ZextOp,
2004
DAG.getConstant(C1 & APInt::getLowBitsSet(
2009
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2010
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2011
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2012
if (N0.getOpcode() == ISD::SETCC &&
2013
isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2014
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2016
return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2017
// Invert the condition.
2018
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2019
CC = ISD::getSetCCInverse(CC,
2020
N0.getOperand(0).getValueType().isInteger());
2021
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2024
if ((N0.getOpcode() == ISD::XOR ||
2025
(N0.getOpcode() == ISD::AND &&
2026
N0.getOperand(0).getOpcode() == ISD::XOR &&
2027
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2028
isa<ConstantSDNode>(N0.getOperand(1)) &&
2029
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2030
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2031
// can only do this if the top bits are known zero.
2032
unsigned BitWidth = N0.getValueSizeInBits();
2033
if (DAG.MaskedValueIsZero(N0,
2034
APInt::getHighBitsSet(BitWidth,
2036
// Okay, get the un-inverted input value.
2038
if (N0.getOpcode() == ISD::XOR)
2039
Val = N0.getOperand(0);
2041
assert(N0.getOpcode() == ISD::AND &&
2042
N0.getOperand(0).getOpcode() == ISD::XOR);
2043
// ((X^1)&1)^1 -> X & 1
2044
Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2045
N0.getOperand(0).getOperand(0),
2049
return DAG.getSetCC(dl, VT, Val, N1,
2050
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2052
} else if (N1C->getAPIntValue() == 1 &&
2054
getBooleanContents() == ZeroOrOneBooleanContent)) {
2056
if (Op0.getOpcode() == ISD::TRUNCATE)
2057
Op0 = Op0.getOperand(0);
2059
if ((Op0.getOpcode() == ISD::XOR) &&
2060
Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2061
Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2062
// (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2063
Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2064
return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2066
} else if (Op0.getOpcode() == ISD::AND &&
2067
isa<ConstantSDNode>(Op0.getOperand(1)) &&
2068
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2069
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2070
if (Op0.getValueType().bitsGT(VT))
2071
Op0 = DAG.getNode(ISD::AND, dl, VT,
2072
DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2073
DAG.getConstant(1, VT));
2074
else if (Op0.getValueType().bitsLT(VT))
2075
Op0 = DAG.getNode(ISD::AND, dl, VT,
2076
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2077
DAG.getConstant(1, VT));
2079
return DAG.getSetCC(dl, VT, Op0,
2080
DAG.getConstant(0, Op0.getValueType()),
2081
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2086
APInt MinVal, MaxVal;
2087
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2088
if (ISD::isSignedIntSetCC(Cond)) {
2089
MinVal = APInt::getSignedMinValue(OperandBitSize);
2090
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2092
MinVal = APInt::getMinValue(OperandBitSize);
2093
MaxVal = APInt::getMaxValue(OperandBitSize);
2096
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
2097
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2098
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2099
// X >= C0 --> X > (C0-1)
2100
return DAG.getSetCC(dl, VT, N0,
2101
DAG.getConstant(C1-1, N1.getValueType()),
2102
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2105
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2106
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2107
// X <= C0 --> X < (C0+1)
2108
return DAG.getSetCC(dl, VT, N0,
2109
DAG.getConstant(C1+1, N1.getValueType()),
2110
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2113
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2114
return DAG.getConstant(0, VT); // X < MIN --> false
2115
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2116
return DAG.getConstant(1, VT); // X >= MIN --> true
2117
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2118
return DAG.getConstant(0, VT); // X > MAX --> false
2119
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2120
return DAG.getConstant(1, VT); // X <= MAX --> true
2122
// Canonicalize setgt X, Min --> setne X, Min
2123
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2124
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2125
// Canonicalize setlt X, Max --> setne X, Max
2126
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2127
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2129
// If we have setult X, 1, turn it into seteq X, 0
2130
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2131
return DAG.getSetCC(dl, VT, N0,
2132
DAG.getConstant(MinVal, N0.getValueType()),
2134
// If we have setugt X, Max-1, turn it into seteq X, Max
2135
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2136
return DAG.getSetCC(dl, VT, N0,
2137
DAG.getConstant(MaxVal, N0.getValueType()),
2140
// If we have "setcc X, C0", check to see if we can shrink the immediate
2143
// SETUGT X, SINTMAX -> SETLT X, 0
2144
if (Cond == ISD::SETUGT &&
2145
C1 == APInt::getSignedMaxValue(OperandBitSize))
2146
return DAG.getSetCC(dl, VT, N0,
2147
DAG.getConstant(0, N1.getValueType()),
2150
// SETULT X, SINTMIN -> SETGT X, -1
2151
if (Cond == ISD::SETULT &&
2152
C1 == APInt::getSignedMinValue(OperandBitSize)) {
2153
SDValue ConstMinusOne =
2154
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2156
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2159
// Fold bit comparisons when we can.
2160
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2161
(VT == N0.getValueType() ||
2162
(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2163
N0.getOpcode() == ISD::AND)
2164
if (ConstantSDNode *AndRHS =
2165
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2166
EVT ShiftTy = DCI.isBeforeLegalize() ?
2167
getPointerTy() : getShiftAmountTy();
2168
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2169
// Perform the xform if the AND RHS is a single bit.
2170
if (AndRHS->getAPIntValue().isPowerOf2()) {
2171
return DAG.getNode(ISD::TRUNCATE, dl, VT,
2172
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2173
DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2175
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2176
// (X & 8) == 8 --> (X & 8) >> 3
2177
// Perform the xform if C1 is a single bit.
2178
if (C1.isPowerOf2()) {
2179
return DAG.getNode(ISD::TRUNCATE, dl, VT,
2180
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2181
DAG.getConstant(C1.logBase2(), ShiftTy)));
2187
if (isa<ConstantFPSDNode>(N0.getNode())) {
2188
// Constant fold or commute setcc.
2189
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2190
if (O.getNode()) return O;
2191
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2192
// If the RHS of an FP comparison is a constant, simplify it away in
2194
if (CFP->getValueAPF().isNaN()) {
2195
// If an operand is known to be a nan, we can fold it.
2196
switch (ISD::getUnorderedFlavor(Cond)) {
2197
default: llvm_unreachable("Unknown flavor!");
2198
case 0: // Known false.
2199
return DAG.getConstant(0, VT);
2200
case 1: // Known true.
2201
return DAG.getConstant(1, VT);
2202
case 2: // Undefined.
2203
return DAG.getUNDEF(VT);
2207
// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2208
// constant if knowing that the operand is non-nan is enough. We prefer to
2209
// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2211
if (Cond == ISD::SETO || Cond == ISD::SETUO)
2212
return DAG.getSetCC(dl, VT, N0, N0, Cond);
2214
// If the condition is not legal, see if we can find an equivalent one
2216
if (!isCondCodeLegal(Cond, N0.getValueType())) {
2217
// If the comparison was an awkward floating-point == or != and one of
2218
// the comparison operands is infinity or negative infinity, convert the
2219
// condition to a less-awkward <= or >=.
2220
if (CFP->getValueAPF().isInfinity()) {
2221
if (CFP->getValueAPF().isNegative()) {
2222
if (Cond == ISD::SETOEQ &&
2223
isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2224
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2225
if (Cond == ISD::SETUEQ &&
2226
isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2227
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2228
if (Cond == ISD::SETUNE &&
2229
isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2230
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2231
if (Cond == ISD::SETONE &&
2232
isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2233
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2235
if (Cond == ISD::SETOEQ &&
2236
isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2237
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2238
if (Cond == ISD::SETUEQ &&
2239
isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2240
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2241
if (Cond == ISD::SETUNE &&
2242
isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2243
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2244
if (Cond == ISD::SETONE &&
2245
isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2246
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2253
// We can always fold X == X for integer setcc's.
2254
if (N0.getValueType().isInteger())
2255
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2256
unsigned UOF = ISD::getUnorderedFlavor(Cond);
2257
if (UOF == 2) // FP operators that are undefined on NaNs.
2258
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2259
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2260
return DAG.getConstant(UOF, VT);
2261
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2262
// if it is not already.
2263
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2264
if (NewCond != Cond)
2265
return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2268
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2269
N0.getValueType().isInteger()) {
2270
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2271
N0.getOpcode() == ISD::XOR) {
2272
// Simplify (X+Y) == (X+Z) --> Y == Z
2273
if (N0.getOpcode() == N1.getOpcode()) {
2274
if (N0.getOperand(0) == N1.getOperand(0))
2275
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2276
if (N0.getOperand(1) == N1.getOperand(1))
2277
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2278
if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2279
// If X op Y == Y op X, try other combinations.
2280
if (N0.getOperand(0) == N1.getOperand(1))
2281
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2283
if (N0.getOperand(1) == N1.getOperand(0))
2284
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2289
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2290
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2291
// Turn (X+C1) == C2 --> X == C2-C1
2292
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2293
return DAG.getSetCC(dl, VT, N0.getOperand(0),
2294
DAG.getConstant(RHSC->getAPIntValue()-
2295
LHSR->getAPIntValue(),
2296
N0.getValueType()), Cond);
2299
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2300
if (N0.getOpcode() == ISD::XOR)
2301
// If we know that all of the inverted bits are zero, don't bother
2302
// performing the inversion.
2303
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2305
DAG.getSetCC(dl, VT, N0.getOperand(0),
2306
DAG.getConstant(LHSR->getAPIntValue() ^
2307
RHSC->getAPIntValue(),
2312
// Turn (C1-X) == C2 --> X == C1-C2
2313
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2314
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2316
DAG.getSetCC(dl, VT, N0.getOperand(1),
2317
DAG.getConstant(SUBC->getAPIntValue() -
2318
RHSC->getAPIntValue(),
2325
// Simplify (X+Z) == X --> Z == 0
2326
if (N0.getOperand(0) == N1)
2327
return DAG.getSetCC(dl, VT, N0.getOperand(1),
2328
DAG.getConstant(0, N0.getValueType()), Cond);
2329
if (N0.getOperand(1) == N1) {
2330
if (DAG.isCommutativeBinOp(N0.getOpcode()))
2331
return DAG.getSetCC(dl, VT, N0.getOperand(0),
2332
DAG.getConstant(0, N0.getValueType()), Cond);
2333
else if (N0.getNode()->hasOneUse()) {
2334
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2335
// (Z-X) == X --> Z == X<<1
2336
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2338
DAG.getConstant(1, getShiftAmountTy()));
2339
if (!DCI.isCalledByLegalizer())
2340
DCI.AddToWorklist(SH.getNode());
2341
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2346
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2347
N1.getOpcode() == ISD::XOR) {
2348
// Simplify X == (X+Z) --> Z == 0
2349
if (N1.getOperand(0) == N0) {
2350
return DAG.getSetCC(dl, VT, N1.getOperand(1),
2351
DAG.getConstant(0, N1.getValueType()), Cond);
2352
} else if (N1.getOperand(1) == N0) {
2353
if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2354
return DAG.getSetCC(dl, VT, N1.getOperand(0),
2355
DAG.getConstant(0, N1.getValueType()), Cond);
2356
} else if (N1.getNode()->hasOneUse()) {
2357
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2358
// X == (Z-X) --> X<<1 == Z
2359
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2360
DAG.getConstant(1, getShiftAmountTy()));
2361
if (!DCI.isCalledByLegalizer())
2362
DCI.AddToWorklist(SH.getNode());
2363
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2368
// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2369
// Note that where y is variable and is known to have at most
2370
// one bit set (for example, if it is z&1) we cannot do this;
2371
// the expressions are not equivalent when y==0.
2372
if (N0.getOpcode() == ISD::AND)
2373
if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2374
if (ValueHasExactlyOneBitSet(N1, DAG)) {
2375
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2376
SDValue Zero = DAG.getConstant(0, N1.getValueType());
2377
return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2380
if (N1.getOpcode() == ISD::AND)
2381
if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2382
if (ValueHasExactlyOneBitSet(N0, DAG)) {
2383
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2384
SDValue Zero = DAG.getConstant(0, N0.getValueType());
2385
return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2390
// Fold away ALL boolean setcc's.
2392
if (N0.getValueType() == MVT::i1 && foldBooleans) {
2394
default: llvm_unreachable("Unknown integer setcc!");
2395
case ISD::SETEQ: // X == Y -> ~(X^Y)
2396
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2397
N0 = DAG.getNOT(dl, Temp, MVT::i1);
2398
if (!DCI.isCalledByLegalizer())
2399
DCI.AddToWorklist(Temp.getNode());
2401
case ISD::SETNE: // X != Y --> (X^Y)
2402
N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2404
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2405
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2406
Temp = DAG.getNOT(dl, N0, MVT::i1);
2407
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2408
if (!DCI.isCalledByLegalizer())
2409
DCI.AddToWorklist(Temp.getNode());
2411
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2412
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2413
Temp = DAG.getNOT(dl, N1, MVT::i1);
2414
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2415
if (!DCI.isCalledByLegalizer())
2416
DCI.AddToWorklist(Temp.getNode());
2418
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2419
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2420
Temp = DAG.getNOT(dl, N0, MVT::i1);
2421
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2422
if (!DCI.isCalledByLegalizer())
2423
DCI.AddToWorklist(Temp.getNode());
2425
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2426
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2427
Temp = DAG.getNOT(dl, N1, MVT::i1);
2428
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2431
if (VT != MVT::i1) {
2432
if (!DCI.isCalledByLegalizer())
2433
DCI.AddToWorklist(N0.getNode());
2434
// FIXME: If running after legalize, we probably can't do this.
2435
N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2440
// Could not fold it.
2444
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2445
/// node is a GlobalAddress + offset.
2446
bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
2447
int64_t &Offset) const {
2448
if (isa<GlobalAddressSDNode>(N)) {
2449
GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2450
GA = GASD->getGlobal();
2451
Offset += GASD->getOffset();
2455
if (N->getOpcode() == ISD::ADD) {
2456
SDValue N1 = N->getOperand(0);
2457
SDValue N2 = N->getOperand(1);
2458
if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2459
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2461
Offset += V->getSExtValue();
2464
} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2465
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2467
Offset += V->getSExtValue();
2476
SDValue TargetLowering::
2477
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2478
// Default implementation: no optimization.
2482
//===----------------------------------------------------------------------===//
2483
// Inline Assembler Implementation Methods
2484
//===----------------------------------------------------------------------===//
2487
TargetLowering::ConstraintType
2488
TargetLowering::getConstraintType(const std::string &Constraint) const {
2489
// FIXME: lots more standard ones to handle.
2490
if (Constraint.size() == 1) {
2491
switch (Constraint[0]) {
2493
case 'r': return C_RegisterClass;
2495
case 'o': // offsetable
2496
case 'V': // not offsetable
2498
case 'i': // Simple Integer or Relocatable Constant
2499
case 'n': // Simple Integer
2500
case 's': // Relocatable Constant
2501
case 'X': // Allow ANY value.
2502
case 'I': // Target registers.
2514
if (Constraint.size() > 1 && Constraint[0] == '{' &&
2515
Constraint[Constraint.size()-1] == '}')
2520
/// LowerXConstraint - try to replace an X constraint, which matches anything,
2521
/// with another that has more specific requirements based on the type of the
2522
/// corresponding operand.
2523
const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2524
if (ConstraintVT.isInteger())
2526
if (ConstraintVT.isFloatingPoint())
2527
return "f"; // works for many targets
2531
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2532
/// vector. If it is invalid, don't add anything to Ops.
2533
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2534
char ConstraintLetter,
2535
std::vector<SDValue> &Ops,
2536
SelectionDAG &DAG) const {
2537
switch (ConstraintLetter) {
2539
case 'X': // Allows any operand; labels (basic block) use this.
2540
if (Op.getOpcode() == ISD::BasicBlock) {
2545
case 'i': // Simple Integer or Relocatable Constant
2546
case 'n': // Simple Integer
2547
case 's': { // Relocatable Constant
2548
// These operands are interested in values of the form (GV+C), where C may
2549
// be folded in as an offset of GV, or it may be explicitly added. Also, it
2550
// is possible and fine if either GV or C are missing.
2551
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2552
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2554
// If we have "(add GV, C)", pull out GV/C
2555
if (Op.getOpcode() == ISD::ADD) {
2556
C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2557
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2558
if (C == 0 || GA == 0) {
2559
C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2560
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2562
if (C == 0 || GA == 0)
2566
// If we find a valid operand, map to the TargetXXX version so that the
2567
// value itself doesn't get selected.
2568
if (GA) { // Either &GV or &GV+C
2569
if (ConstraintLetter != 'n') {
2570
int64_t Offs = GA->getOffset();
2571
if (C) Offs += C->getZExtValue();
2572
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2573
C ? C->getDebugLoc() : DebugLoc(),
2574
Op.getValueType(), Offs));
2578
if (C) { // just C, no GV.
2579
// Simple constants are not allowed for 's'.
2580
if (ConstraintLetter != 's') {
2581
// gcc prints these as sign extended. Sign extend value to 64 bits
2582
// now; without this it would get ZExt'd later in
2583
// ScheduleDAGSDNodes::EmitNode, which is very generic.
2584
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2594
std::vector<unsigned> TargetLowering::
2595
getRegClassForInlineAsmConstraint(const std::string &Constraint,
2597
return std::vector<unsigned>();
2601
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2602
getRegForInlineAsmConstraint(const std::string &Constraint,
2604
if (Constraint[0] != '{')
2605
return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2606
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2608
// Remove the braces from around the name.
2609
StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2611
// Figure out which register class contains this reg.
2612
const TargetRegisterInfo *RI = TM.getRegisterInfo();
2613
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2614
E = RI->regclass_end(); RCI != E; ++RCI) {
2615
const TargetRegisterClass *RC = *RCI;
2617
// If none of the value types for this register class are valid, we
2618
// can't use it. For example, 64-bit reg classes on 32-bit targets.
2619
bool isLegal = false;
2620
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2622
if (isTypeLegal(*I)) {
2628
if (!isLegal) continue;
2630
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2632
if (RegName.equals_lower(RI->getName(*I)))
2633
return std::make_pair(*I, RC);
2637
return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2640
//===----------------------------------------------------------------------===//
2641
// Constraint Selection.
2643
/// isMatchingInputConstraint - Return true of this is an input operand that is
2644
/// a matching constraint like "4".
2645
bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2646
assert(!ConstraintCode.empty() && "No known constraint!");
2647
return isdigit(ConstraintCode[0]);
2650
/// getMatchedOperand - If this is an input matching constraint, this method
2651
/// returns the output operand it matches.
2652
unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2653
assert(!ConstraintCode.empty() && "No known constraint!");
2654
return atoi(ConstraintCode.c_str());
2658
/// getConstraintGenerality - Return an integer indicating how general CT
2660
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2662
default: llvm_unreachable("Unknown constraint type!");
2663
case TargetLowering::C_Other:
2664
case TargetLowering::C_Unknown:
2666
case TargetLowering::C_Register:
2668
case TargetLowering::C_RegisterClass:
2670
case TargetLowering::C_Memory:
2675
/// ChooseConstraint - If there are multiple different constraints that we
2676
/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2677
/// This is somewhat tricky: constraints fall into four classes:
2678
/// Other -> immediates and magic values
2679
/// Register -> one specific register
2680
/// RegisterClass -> a group of regs
2681
/// Memory -> memory
2682
/// Ideally, we would pick the most specific constraint possible: if we have
2683
/// something that fits into a register, we would pick it. The problem here
2684
/// is that if we have something that could either be in a register or in
2685
/// memory that use of the register could cause selection of *other*
2686
/// operands to fail: they might only succeed if we pick memory. Because of
2687
/// this the heuristic we use is:
2689
/// 1) If there is an 'other' constraint, and if the operand is valid for
2690
/// that constraint, use it. This makes us take advantage of 'i'
2691
/// constraints when available.
2692
/// 2) Otherwise, pick the most general constraint present. This prefers
2693
/// 'm' over 'r', for example.
2695
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2696
const TargetLowering &TLI,
2697
SDValue Op, SelectionDAG *DAG) {
2698
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2699
unsigned BestIdx = 0;
2700
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2701
int BestGenerality = -1;
2703
// Loop over the options, keeping track of the most general one.
2704
for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2705
TargetLowering::ConstraintType CType =
2706
TLI.getConstraintType(OpInfo.Codes[i]);
2708
// If this is an 'other' constraint, see if the operand is valid for it.
2709
// For example, on X86 we might have an 'rI' constraint. If the operand
2710
// is an integer in the range [0..31] we want to use I (saving a load
2711
// of a register), otherwise we must use 'r'.
2712
if (CType == TargetLowering::C_Other && Op.getNode()) {
2713
assert(OpInfo.Codes[i].size() == 1 &&
2714
"Unhandled multi-letter 'other' constraint");
2715
std::vector<SDValue> ResultOps;
2716
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
2718
if (!ResultOps.empty()) {
2725
// Things with matching constraints can only be registers, per gcc
2726
// documentation. This mainly affects "g" constraints.
2727
if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2730
// This constraint letter is more general than the previous one, use it.
2731
int Generality = getConstraintGenerality(CType);
2732
if (Generality > BestGenerality) {
2735
BestGenerality = Generality;
2739
OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2740
OpInfo.ConstraintType = BestType;
2743
/// ComputeConstraintToUse - Determines the constraint code and constraint
2744
/// type to use for the specific AsmOperandInfo, setting
2745
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2746
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2748
SelectionDAG *DAG) const {
2749
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2751
// Single-letter constraints ('r') are very common.
2752
if (OpInfo.Codes.size() == 1) {
2753
OpInfo.ConstraintCode = OpInfo.Codes[0];
2754
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2756
ChooseConstraint(OpInfo, *this, Op, DAG);
2759
// 'X' matches anything.
2760
if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2761
// Labels and constants are handled elsewhere ('X' is the only thing
2762
// that matches labels). For Functions, the type here is the type of
2763
// the result, which is not what we want to look at; leave them alone.
2764
Value *v = OpInfo.CallOperandVal;
2765
if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2766
OpInfo.CallOperandVal = v;
2770
// Otherwise, try to resolve it to something we know about by looking at
2771
// the actual operand type.
2772
if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2773
OpInfo.ConstraintCode = Repl;
2774
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2779
//===----------------------------------------------------------------------===//
2780
// Loop Strength Reduction hooks
2781
//===----------------------------------------------------------------------===//
2783
/// isLegalAddressingMode - Return true if the addressing mode represented
2784
/// by AM is legal for this target, for a load/store of the specified type.
2785
bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2786
const Type *Ty) const {
2787
// The default implementation of this implements a conservative RISCy, r+r and
2790
// Allows a sign-extended 16-bit immediate field.
2791
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2794
// No global is ever allowed as a base.
2798
// Only support r+r,
2800
case 0: // "r+i" or just "i", depending on HasBaseReg.
2803
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2805
// Otherwise we have r+r or r+i.
2808
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2810
// Allow 2*r as r+r.
2817
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2818
/// return a DAG expression to select that will generate the same value by
2819
/// multiplying by a magic number. See:
2820
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2821
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2822
std::vector<SDNode*>* Created) const {
2823
EVT VT = N->getValueType(0);
2824
DebugLoc dl= N->getDebugLoc();
2826
// Check to see if we can do this.
2827
// FIXME: We should be more aggressive here.
2828
if (!isTypeLegal(VT))
2831
APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2832
APInt::ms magics = d.magic();
2834
// Multiply the numerator (operand 0) by the magic value
2835
// FIXME: We should support doing a MUL in a wider type
2837
if (isOperationLegalOrCustom(ISD::MULHS, VT))
2838
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2839
DAG.getConstant(magics.m, VT));
2840
else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2841
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2843
DAG.getConstant(magics.m, VT)).getNode(), 1);
2845
return SDValue(); // No mulhs or equvialent
2846
// If d > 0 and m < 0, add the numerator
2847
if (d.isStrictlyPositive() && magics.m.isNegative()) {
2848
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2850
Created->push_back(Q.getNode());
2852
// If d < 0 and m > 0, subtract the numerator.
2853
if (d.isNegative() && magics.m.isStrictlyPositive()) {
2854
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2856
Created->push_back(Q.getNode());
2858
// Shift right algebraic if shift value is nonzero
2860
Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2861
DAG.getConstant(magics.s, getShiftAmountTy()));
2863
Created->push_back(Q.getNode());
2865
// Extract the sign bit and add it to the quotient
2867
DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2868
getShiftAmountTy()));
2870
Created->push_back(T.getNode());
2871
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2874
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2875
/// return a DAG expression to select that will generate the same value by
2876
/// multiplying by a magic number. See:
2877
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2878
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2879
std::vector<SDNode*>* Created) const {
2880
EVT VT = N->getValueType(0);
2881
DebugLoc dl = N->getDebugLoc();
2883
// Check to see if we can do this.
2884
// FIXME: We should be more aggressive here.
2885
if (!isTypeLegal(VT))
2888
// FIXME: We should use a narrower constant when the upper
2889
// bits are known to be zero.
2890
ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2891
APInt::mu magics = N1C->getAPIntValue().magicu();
2893
// Multiply the numerator (operand 0) by the magic value
2894
// FIXME: We should support doing a MUL in a wider type
2896
if (isOperationLegalOrCustom(ISD::MULHU, VT))
2897
Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2898
DAG.getConstant(magics.m, VT));
2899
else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2900
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2902
DAG.getConstant(magics.m, VT)).getNode(), 1);
2904
return SDValue(); // No mulhu or equvialent
2906
Created->push_back(Q.getNode());
2908
if (magics.a == 0) {
2909
assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2910
"We shouldn't generate an undefined shift!");
2911
return DAG.getNode(ISD::SRL, dl, VT, Q,
2912
DAG.getConstant(magics.s, getShiftAmountTy()));
2914
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2916
Created->push_back(NPQ.getNode());
2917
NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2918
DAG.getConstant(1, getShiftAmountTy()));
2920
Created->push_back(NPQ.getNode());
2921
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2923
Created->push_back(NPQ.getNode());
2924
return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2925
DAG.getConstant(magics.s-1, getShiftAmountTy()));
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
