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//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This implements the ScheduleDAG class, which is a base class used by
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// scheduling implementation classes.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "SDNodeDbgValue.h"
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#include "ScheduleDAGSDNodes.h"
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#include "InstrEmitter.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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STATISTIC(LoadsClustered, "Number of loads clustered together");
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ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
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/// Run - perform scheduling.
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void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
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MachineBasicBlock::iterator insertPos) {
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ScheduleDAG::Run(bb, insertPos);
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
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const SUnit *Addr = 0;
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SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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SUnit *SU = &SUnits.back();
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const TargetLowering &TLI = DAG->getTargetLoweringInfo();
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(N->isMachineOpcode() &&
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N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
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SU->SchedulingPref = Sched::None;
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SU->SchedulingPref = TLI.getSchedulingPreference(N);
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SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
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SUnit *SU = NewSUnit(Old->getNode());
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SU->OrigNode = Old->OrigNode;
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SU->Latency = Old->Latency;
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
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SU->SchedulingPref = Old->SchedulingPref;
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/// CheckForPhysRegDependency - Check if the dependency between def and use of
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/// a specified operand is a physical register dependency. If so, returns the
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/// register and the cost of copying the register.
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static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
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const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII,
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unsigned &PhysReg, int &Cost) {
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if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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unsigned ResNo = User->getOperand(2).getResNo();
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if (Def->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
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if (ResNo >= II.getNumDefs() &&
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II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
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const TargetRegisterClass *RC =
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TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
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Cost = RC->getCopyCost();
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static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag,
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SmallVector<EVT, 4> VTs;
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SDNode *FlagDestNode = Flag.getNode();
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// Don't add a flag from a node to itself.
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if (FlagDestNode == N) return;
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// Don't add a flag to something which already has a flag.
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if (N->getValueType(N->getNumValues() - 1) == MVT::Flag) return;
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for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
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VTs.push_back(N->getValueType(I));
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VTs.push_back(MVT::Flag);
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SmallVector<SDValue, 4> Ops;
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for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
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Ops.push_back(N->getOperand(I));
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SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
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MachineSDNode::mmo_iterator Begin = 0, End = 0;
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MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
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// Store memory references.
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Begin = MN->memoperands_begin();
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End = MN->memoperands_end();
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DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
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// Reset the memory references
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MN->setMemRefs(Begin, End);
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/// ClusterNeighboringLoads - Force nearby loads together by "flagging" them.
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/// This function finds loads of the same base and different offsets. If the
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/// offsets are not far apart (target specific), it add MVT::Flag inputs and
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/// outputs to ensure they are scheduled together and in order. This
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/// optimization may benefit some targets by improving cache locality.
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void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
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unsigned NumOps = Node->getNumOperands();
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if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
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Chain = Node->getOperand(NumOps-1).getNode();
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// Look for other loads of the same chain. Find loads that are loading from
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// the same base pointer and different offsets.
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SmallPtrSet<SDNode*, 16> Visited;
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SmallVector<int64_t, 4> Offsets;
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DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
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bool Cluster = false;
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for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
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if (User == Node || !Visited.insert(User))
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int64_t Offset1, Offset2;
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if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
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// FIXME: Should be ok if they addresses are identical. But earlier
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// optimizations really should have eliminated one of the loads.
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if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
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Offsets.push_back(Offset1);
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O2SMap.insert(std::make_pair(Offset2, User));
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Offsets.push_back(Offset2);
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if (Offset2 < Offset1)
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// Sort them in increasing order.
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std::sort(Offsets.begin(), Offsets.end());
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// Check if the loads are close enough.
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SmallVector<SDNode*, 4> Loads;
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unsigned NumLoads = 0;
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int64_t BaseOff = Offsets[0];
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SDNode *BaseLoad = O2SMap[BaseOff];
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Loads.push_back(BaseLoad);
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for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
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int64_t Offset = Offsets[i];
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SDNode *Load = O2SMap[Offset];
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if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
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break; // Stop right here. Ignore loads that are further away.
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Loads.push_back(Load);
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// Cluster loads by adding MVT::Flag outputs and inputs. This also
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// ensure they are scheduled in order of increasing addresses.
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SDNode *Lead = Loads[0];
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AddFlags(Lead, SDValue(0, 0), true, DAG);
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SDValue InFlag = SDValue(Lead, Lead->getNumValues() - 1);
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for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
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bool OutFlag = I < E - 1;
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SDNode *Load = Loads[I];
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AddFlags(Load, InFlag, OutFlag, DAG);
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InFlag = SDValue(Load, Load->getNumValues() - 1);
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/// ClusterNodes - Cluster certain nodes which should be scheduled together.
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void ScheduleDAGSDNodes::ClusterNodes() {
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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if (!Node || !Node->isMachineOpcode())
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unsigned Opc = Node->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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// Cluster loads from "near" addresses into combined SUnits.
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ClusterNeighboringLoads(Node);
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void ScheduleDAGSDNodes::BuildSchedUnits() {
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// During scheduling, the NodeId field of SDNode is used to map SDNodes
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// to their associated SUnits by holding SUnits table indices. A value
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// of -1 means the SDNode does not yet have an associated SUnit.
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unsigned NumNodes = 0;
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for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
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E = DAG->allnodes_end(); NI != E; ++NI) {
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// FIXME: Multiply by 2 because we may clone nodes during scheduling.
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// This is a temporary workaround.
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SUnits.reserve(NumNodes * 2);
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// Add all nodes in depth first order.
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SmallVector<SDNode*, 64> Worklist;
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SmallPtrSet<SDNode*, 64> Visited;
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Worklist.push_back(DAG->getRoot().getNode());
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Visited.insert(DAG->getRoot().getNode());
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while (!Worklist.empty()) {
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SDNode *NI = Worklist.pop_back_val();
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// Add all operands to the worklist unless they've already been added.
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for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
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if (Visited.insert(NI->getOperand(i).getNode()))
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Worklist.push_back(NI->getOperand(i).getNode());
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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// If this node has already been processed, stop now.
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if (NI->getNodeId() != -1) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is flagged to this node, if so, add them to flagged
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// nodes. Nodes can have at most one flag input and one flag output. Flags
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// are required to be the last operand and result of a node.
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// Scan up to find flagged preds.
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while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
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N = N->getOperand(N->getNumOperands()-1).getNode();
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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// Scan down to find any flagged succs.
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while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
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SDValue FlagVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Flag result.
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bool HasFlagUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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if (FlagVal.isOperandOf(*UI)) {
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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if (!HasFlagUse) break;
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// If there are flag operands involved, N is now the bottom-most node
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// of the sequence of nodes that are flagged together.
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NodeSUnit->setNode(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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// Assign the Latency field of NodeSUnit using target-provided information.
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ComputeLatency(NodeSUnit);
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void ScheduleDAGSDNodes::AddSchedEdges() {
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const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->getNode();
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if (MainNode->isMachineOpcode()) {
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unsigned Opc = MainNode->getMachineOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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if (TID.isCommutable())
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SU->isCommutable = true;
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// Find all predecessors and successors of the group.
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
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if (N->isMachineOpcode() &&
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TII->get(N->getMachineOpcode()).getImplicitDefs()) {
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SU->hasPhysRegClobbers = true;
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unsigned NumUsed = InstrEmitter::CountResults(N);
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while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
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--NumUsed; // Skip over unused values at the end.
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if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
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SU->hasPhysRegDefs = true;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).getNode();
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = &SUnits[OpN->getNodeId()];
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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EVT OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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unsigned PhysReg = 0;
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// Determine if this is a physical register dependency.
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CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
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assert((PhysReg == 0 || !isChain) &&
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"Chain dependence via physreg data?");
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// FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
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// emits a copy from the physical register to a virtual register unless
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// it requires a cross class copy (cost < 0). That means we are only
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// treating "expensive to copy" register dependency as physical register
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// dependency. This may change in the future though.
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// If this is a ctrl dep, latency is 1.
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unsigned OpLatency = isChain ? 1 : OpSU->Latency;
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const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
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if (!isChain && !UnitLatencies) {
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ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// flagged together nodes with a single SUnit.
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void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
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// Cluster certain nodes which should be scheduled together.
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// Populate the SUnits array.
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// Compute all the scheduling dependencies between nodes.
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void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
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// Check to see if the scheduler cares about latencies.
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if (ForceUnitLatencies()) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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if (InstrItins.isEmpty()) {
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
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if (N->isMachineOpcode()) {
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SU->Latency += InstrItins.
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getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
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void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
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unsigned OpIdx, SDep& dep) const{
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// Check to see if the scheduler cares about latencies.
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if (ForceUnitLatencies())
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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if (InstrItins.isEmpty())
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if (dep.getKind() != SDep::Data)
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unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
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if (Def->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
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if (DefIdx >= II.getNumDefs())
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int DefCycle = InstrItins.getOperandCycle(II.getSchedClass(), DefIdx);
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if (Use->isMachineOpcode()) {
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const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass();
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UseCycle = InstrItins.getOperandCycle(UseClass, OpIdx);
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int Latency = DefCycle - UseCycle + 1;
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dep.setLatency(Latency);
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void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
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if (!SU->getNode()) {
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dbgs() << "PHYS REG COPY\n";
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SU->getNode()->dump(DAG);
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SmallVector<SDNode *, 4> FlaggedNodes;
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for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
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FlaggedNodes.push_back(N);
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while (!FlaggedNodes.empty()) {
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FlaggedNodes.back()->dump(DAG);
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FlaggedNodes.pop_back();
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bool operator()(const std::pair<unsigned, MachineInstr*> &A,
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const std::pair<unsigned, MachineInstr*> &B) {
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return A.first < B.first;
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// ProcessSourceNode - Process nodes with source order numbers. These are added
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// to a vector which EmitSchedule uses to determine how to insert dbg_value
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// instructions in the right order.
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static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
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InstrEmitter &Emitter,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
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SmallSet<unsigned, 8> &Seen) {
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unsigned Order = DAG->GetOrdering(N);
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if (!Order || !Seen.insert(Order))
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MachineBasicBlock *BB = Emitter.getBlock();
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if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
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// Did not insert any instruction.
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Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
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Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
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if (!N->getHasDebugValue())
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// Opportunistically insert immediate dbg_value uses, i.e. those with source
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// order number right after the N.
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MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
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SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
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for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
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if (DVs[i]->isInvalidated())
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unsigned DVOrder = DVs[i]->getOrder();
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if (DVOrder == ++Order) {
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MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
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Orders.push_back(std::make_pair(DVOrder, DbgMI));
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BB->insert(InsertPos, DbgMI);
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DVs[i]->setIsInvalidated();
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/// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
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InstrEmitter Emitter(BB, InsertPos);
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DenseMap<SDValue, unsigned> VRBaseMap;
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DenseMap<SUnit*, unsigned> CopyVRBaseMap;
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SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
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SmallSet<unsigned, 8> Seen;
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bool HasDbg = DAG->hasDebugValues();
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// If this is the first BB, emit byval parameter dbg_value's.
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if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
563
SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
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SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
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for (; PDI != PDE; ++PDI) {
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MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
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BB->insert(InsertPos, DbgMI);
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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SUnit *SU = Sequence[i];
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// Null SUnit* is a noop.
580
// For pre-regalloc scheduling, create instructions corresponding to the
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// SDNode and any flagged SDNodes and append them to the block.
582
if (!SU->getNode()) {
584
EmitPhysRegCopy(SU, CopyVRBaseMap);
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SmallVector<SDNode *, 4> FlaggedNodes;
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for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
590
N = N->getFlaggedNode())
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FlaggedNodes.push_back(N);
592
while (!FlaggedNodes.empty()) {
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SDNode *N = FlaggedNodes.back();
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Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
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// Remember the source order of the inserted instruction.
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ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
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FlaggedNodes.pop_back();
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Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
603
// Remember the source order of the inserted instruction.
605
ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
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// Insert all the dbg_values which have not already been inserted in source
612
MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
614
// Sort the source order instructions and use the order to insert debug
616
std::sort(Orders.begin(), Orders.end(), OrderSorter());
618
SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
619
SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
620
// Now emit the rest according to source order.
621
unsigned LastOrder = 0;
622
for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
623
unsigned Order = Orders[i].first;
624
MachineInstr *MI = Orders[i].second;
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// Insert all SDDbgValue's whose order(s) are before "Order".
629
unsigned LastDIOrder = 0;
632
(*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
634
assert((*DI)->getOrder() >= LastDIOrder &&
635
"SDDbgValue nodes must be in source order!");
636
LastDIOrder = (*DI)->getOrder();
638
if ((*DI)->isInvalidated())
640
MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
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// Insert to start of the BB (after PHIs).
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BB->insert(BBBegin, DbgMI);
646
// Insert at the instruction, which may be in a different
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// block, if the block was split by a custom inserter.
648
MachineBasicBlock::iterator Pos = MI;
649
MI->getParent()->insert(llvm::next(Pos), DbgMI);
655
// Add trailing DbgValue's before the terminator. FIXME: May want to add
656
// some of them before one or more conditional branches?
658
MachineBasicBlock *InsertBB = Emitter.getBlock();
659
MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
660
if (!(*DI)->isInvalidated()) {
661
MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
663
InsertBB->insert(Pos, DbgMI);
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BB = Emitter.getBlock();
670
InsertPos = Emitter.getInsertPos();
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
