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//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This implements the ScheduleDAGInstrs class, which implements re-scheduling
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/Operator.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallSet.h"
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), Defs(TRI->getNumRegs()),
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Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) {
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MFI = mf.getFrameInfo();
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/// Run - perform scheduling.
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void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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InsertPosIndex = endcount;
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ScheduleDAG::Run(bb, end);
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/// getUnderlyingObjectFromInt - This is the function that does the work of
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/// looking through basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObjectFromInt(const Value *V) {
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if (const Operator *U = dyn_cast<Operator>(V)) {
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// If we find a ptrtoint, we can transfer control back to the
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// regular getUnderlyingObjectFromInt.
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if (U->getOpcode() == Instruction::PtrToInt)
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return U->getOperand(0);
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// If we find an add of a constant or a multiplied value, it's
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// likely that the other operand will lead us to the base
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// object. We don't have to worry about the case where the
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// object address is somehow being computed by the multiply,
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// because our callers only care when the result is an
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// identifibale object.
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if (U->getOpcode() != Instruction::Add ||
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(!isa<ConstantInt>(U->getOperand(1)) &&
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Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
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assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
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/// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject
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/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObject(const Value *V) {
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// First just call Value::getUnderlyingObject to let it do what it does.
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V = V->getUnderlyingObject();
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// If it found an inttoptr, use special code to continue climing.
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if (Operator::getOpcode(V) != Instruction::IntToPtr)
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const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
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// If that succeeded in finding a pointer, continue the search.
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if (!O->getType()->isPointerTy())
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/// getUnderlyingObjectForInstr - If this machine instr has memory reference
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/// information and it can be tracked to a normal reference to a known
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/// object, return the Value for that object. Otherwise return null.
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static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
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const MachineFrameInfo *MFI,
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if (!MI->hasOneMemOperand() ||
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!(*MI->memoperands_begin())->getValue() ||
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(*MI->memoperands_begin())->isVolatile())
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const Value *V = (*MI->memoperands_begin())->getValue();
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V = getUnderlyingObject(V);
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if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
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// For now, ignore PseudoSourceValues which may alias LLVM IR values
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// because the code that uses this function has no way to cope with
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if (PSV->isAliased(MFI))
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MayAlias = PSV->mayAlias(MFI);
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if (isIdentifiedObject(V))
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void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
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if (MachineLoop *ML = MLI.getLoopFor(BB))
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if (BB == ML->getLoopLatch()) {
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MachineBasicBlock *Header = ML->getHeader();
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for (MachineBasicBlock::livein_iterator I = Header->livein_begin(),
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E = Header->livein_end(); I != E; ++I)
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LoopLiveInRegs.insert(*I);
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LoopRegs.VisitLoop(ML);
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void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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// We'll be allocating one SUnit for each instruction, plus one for
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// the region exit node.
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SUnits.reserve(BB->size());
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// We build scheduling units by walking a block's instruction list from bottom
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// Remember where a generic side-effecting instruction is as we procede.
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SUnit *BarrierChain = 0, *AliasChain = 0;
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// Memory references to specific known memory locations are tracked
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// so that they can be given more precise dependencies. We track
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// separately the known memory locations that may alias and those
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// that are known not to alias
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std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
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std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
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// Keep track of dangling debug references to registers.
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std::vector<std::pair<MachineInstr*, unsigned> >
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DanglingDebugValue(TRI->getNumRegs(),
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std::make_pair(static_cast<MachineInstr*>(0), 0));
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Ask the target if address-backscheduling is desirable, and if so how much.
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const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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// Remove any stale debug info; sometimes BuildSchedGraph is called again
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// without emitting the info from the previous call.
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// Walk the list of instructions, from bottom moving up.
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for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
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MachineInstr *MI = prior(MII);
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// DBG_VALUE does not have SUnit's built, so just remember these for later
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if (MI->isDebugValue()) {
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if (MI->getNumOperands()==3 && MI->getOperand(0).isReg() &&
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MI->getOperand(0).getReg())
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DanglingDebugValue[MI->getOperand(0).getReg()] =
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std::make_pair(MI, DbgValueVec.size());
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DbgValueVec.push_back(MI);
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const TargetInstrDesc &TID = MI->getDesc();
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assert(!TID.isTerminator() && !MI->isLabel() &&
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"Cannot schedule terminators or labels!");
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// Create the SUnit for this MI.
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SUnit *SU = NewSUnit(MI);
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// Assign the Latency field of SU using target-provided information.
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// Add register-based dependencies (data, anti, and output).
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for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
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SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
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DbgValueVec[DanglingDebugValue[Reg].second] = 0;
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DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
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std::vector<SUnit *> &UseList = Uses[Reg];
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std::vector<SUnit *> &DefList = Defs[Reg];
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// target we want to allow the defining instruction to issue
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// in the same cycle as the using instruction.
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// TODO: Using a latency of 1 here for output dependencies assumes
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// there's no cost for reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(Reg)))
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DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(*Alias)))
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DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
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// Add any data dependencies.
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unsigned DataLatency = SU->Latency;
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// TODO: Do this for register aliases too.
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// TODO: Perhaps we should get rid of
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// SpecialAddressLatency and just move this into
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// adjustSchedDependency for the targets that care about it.
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if (SpecialAddressLatency != 0 && !UnitLatencies) {
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MachineInstr *UseMI = UseSU->getInstr();
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
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assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
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if ((UseTID.mayLoad() || UseTID.mayStore()) &&
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(unsigned)RegUseIndex < UseTID.getNumOperands() &&
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UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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// If a def is going to wrap back around to the top of the loop,
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if (!UnitLatencies && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseTID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artifical edge.
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ExitSU.addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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LoopRegs.Deps.erase(I);
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DefList.push_back(SU);
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UseList.push_back(SU);
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// Add chain dependencies.
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// Chain dependencies used to enforce memory order should have
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// latency of 0 (except for true dependency of Store followed by
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// aliased Load... we estimate that with a single cycle of latency
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// assuming the hardware will bypass)
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// Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
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// after stack slots are lowered to actual addresses.
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// TODO: Use an AliasAnalysis and do real alias-analysis queries, and
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// produce more precise dependence information.
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#define STORE_LOAD_LATENCY 1
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unsigned TrueMemOrderLatency = 0;
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if (TID.isCall() || TID.hasUnmodeledSideEffects() ||
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(MI->hasVolatileMemoryRef() &&
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(!TID.mayLoad() || !MI->isInvariantLoad(AA)))) {
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// Be conservative with these and add dependencies on all memory
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// references, even those that are known to not alias.
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for (std::map<const Value *, SUnit *>::iterator I =
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NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
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I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
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NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
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for (unsigned i = 0, e = I->second.size(); i != e; ++i)
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I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
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NonAliasMemDefs.clear();
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NonAliasMemUses.clear();
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// Add SU to the barrier chain.
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BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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// Chain all possibly aliasing memory references though SU.
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AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
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for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
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E = AliasMemDefs.end(); I != E; ++I) {
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I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
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AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
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for (unsigned i = 0, e = I->second.size(); i != e; ++i)
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I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
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PendingLoads.clear();
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AliasMemDefs.clear();
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AliasMemUses.clear();
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} else if (TID.mayStore()) {
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bool MayAlias = true;
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TrueMemOrderLatency = STORE_LOAD_LATENCY;
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if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
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// A store to a specific PseudoSourceValue. Add precise dependencies.
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// Record the def in MemDefs, first adding a dep if there is
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std::map<const Value *, SUnit *>::iterator I =
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((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
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std::map<const Value *, SUnit *>::iterator IE =
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((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
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I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
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/*isNormalMemory=*/true));
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AliasMemDefs[V] = SU;
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NonAliasMemDefs[V] = SU;
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// Handle the uses in MemUses, if there are any.
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std::map<const Value *, std::vector<SUnit *> >::iterator J =
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((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
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std::map<const Value *, std::vector<SUnit *> >::iterator JE =
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((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
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for (unsigned i = 0, e = J->second.size(); i != e; ++i)
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J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
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/*Reg=*/0, /*isNormalMemory=*/true));
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// Add dependencies from all the PendingLoads, i.e. loads
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// with no underlying object.
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
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// Add dependence on alias chain, if needed.
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AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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// Add dependence on barrier chain, if needed.
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BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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// Treat all other stores conservatively.
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goto new_alias_chain;
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} else if (TID.mayLoad()) {
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bool MayAlias = true;
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TrueMemOrderLatency = 0;
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if (MI->isInvariantLoad(AA)) {
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// Invariant load, no chain dependencies needed!
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getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
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// A load from a specific PseudoSourceValue. Add precise dependencies.
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std::map<const Value *, SUnit *>::iterator I =
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((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
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std::map<const Value *, SUnit *>::iterator IE =
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((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
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I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
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/*isNormalMemory=*/true));
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AliasMemUses[V].push_back(SU);
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NonAliasMemUses[V].push_back(SU);
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// A load with no underlying object. Depend on all
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// potentially aliasing stores.
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for (std::map<const Value *, SUnit *>::iterator I =
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AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
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I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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PendingLoads.push_back(SU);
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// Add dependencies on alias and barrier chains, if needed.
481
if (MayAlias && AliasChain)
482
AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
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for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
493
PendingLoads.clear();
496
void ScheduleDAGInstrs::FinishBlock() {
500
void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
501
const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
503
// Compute the latency for the node.
505
InstrItins.getStageLatency(SU->getInstr()->getDesc().getSchedClass());
507
// Simplistic target-independent heuristic: assume that loads take
509
if (InstrItins.isEmpty())
510
if (SU->getInstr()->getDesc().mayLoad())
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void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
516
const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
517
if (InstrItins.isEmpty())
520
// For a data dependency with a known register...
521
if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
524
const unsigned Reg = dep.getReg();
526
// ... find the definition of the register in the defining
528
MachineInstr *DefMI = Def->getInstr();
529
int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
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int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(),
534
MachineInstr *UseMI = Use->getInstr();
535
const unsigned UseClass = UseMI->getDesc().getSchedClass();
537
// For all uses of the register, calculate the maxmimum latency
539
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
540
const MachineOperand &MO = UseMI->getOperand(i);
541
if (!MO.isReg() || !MO.isUse())
543
unsigned MOReg = MO.getReg();
547
int UseCycle = InstrItins.getOperandCycle(UseClass, i);
549
Latency = std::max(Latency, DefCycle - UseCycle + 1);
552
// If we found a latency, then replace the existing dependence latency.
554
dep.setLatency(Latency);
559
void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
560
SU->getInstr()->dump();
563
std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
565
raw_string_ostream oss(s);
568
else if (SU == &ExitSU)
571
SU->getInstr()->print(oss);
575
// EmitSchedule - Emit the machine code in scheduled order.
576
MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
577
// For MachineInstr-based scheduling, we're rescheduling the instructions in
578
// the block, so start by removing them from the block.
579
while (Begin != InsertPos) {
580
MachineBasicBlock::iterator I = Begin;
585
// First reinsert any remaining debug_values; these are either constants,
586
// or refer to live-in registers. The beginning of the block is the right
587
// place for the latter. The former might reasonably be placed elsewhere
588
// using some kind of ordering algorithm, but right now it doesn't matter.
589
for (int i = DbgValueVec.size()-1; i>=0; --i)
591
BB->insert(InsertPos, DbgValueVec[i]);
593
// Then re-insert them according to the given schedule.
594
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
595
SUnit *SU = Sequence[i];
597
// Null SUnit* is a noop.
602
BB->insert(InsertPos, SU->getInstr());
603
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
604
BB->insert(InsertPos, SU->DbgInstrList[i]);
607
// Update the Begin iterator, as the first instruction in the block
608
// may have been scheduled later.
609
if (!DbgValueVec.empty()) {
610
for (int i = DbgValueVec.size()-1; i>=0; --i)
611
if (DbgValueVec[i]!=0) {
612
Begin = DbgValueVec[DbgValueVec.size()-1];
615
} else if (!Sequence.empty())
616
Begin = Sequence[0]->getInstr();
added
removed
libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
