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//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains code to lower X86 MachineInstrs to their corresponding
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//===----------------------------------------------------------------------===//
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#include "X86MCInstLower.h"
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#include "X86AsmPrinter.h"
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#include "X86COFFMachineModuleInfo.h"
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#include "X86MCAsmInfo.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/Type.h"
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X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
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X86AsmPrinter &asmprinter)
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: Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
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MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
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MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
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return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
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MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
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return static_cast<const X86TargetLowering*>(TM.getTargetLowering())->
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getPICBaseSymbol(&MF, Ctx);
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/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
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/// operand to an MCSymbol.
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MCSymbol *X86MCInstLower::
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GetSymbolFromOperand(const MachineOperand &MO) const {
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assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
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SmallString<128> Name;
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assert(MO.isSymbol());
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Name += MAI.getGlobalPrefix();
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Name += MO.getSymbolName();
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const GlobalValue *GV = MO.getGlobal();
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bool isImplicitlyPrivate = false;
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if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
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MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
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MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
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isImplicitlyPrivate = true;
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Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
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// If the target flags on the operand changes the name of the symbol, do that
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// before we return the symbol.
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switch (MO.getTargetFlags()) {
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case X86II::MO_DLLIMPORT: {
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// Handle dllimport linkage.
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const char *Prefix = "__imp_";
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Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
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Name += "$non_lazy_ptr";
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getHiddenGVStubEntry(Sym);
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if (StubSym.getPointer() == 0) {
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assert(MO.isGlobal() && "Extern symbol not handled yet");
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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case X86II::MO_DARWIN_STUB: {
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MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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getMachOMMI().getFnStubEntry(Sym);
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if (StubSym.getPointer())
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MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(MO.getGlobal()),
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!MO.getGlobal()->hasInternalLinkage());
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Name.erase(Name.end()-5, Name.end());
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MachineModuleInfoImpl::
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StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
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return Ctx.GetOrCreateSymbol(Name.str());
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MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MCSymbol *Sym) const {
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// FIXME: We would like an efficient form for this, so we don't have to do a
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// lot of extra uniquing.
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const MCExpr *Expr = 0;
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MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
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switch (MO.getTargetFlags()) {
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default: llvm_unreachable("Unknown target flag on GV operand");
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case X86II::MO_NO_FLAG: // No flag.
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// These affect the name of the symbol, not any suffix.
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case X86II::MO_DARWIN_NONLAZY:
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case X86II::MO_DLLIMPORT:
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case X86II::MO_DARWIN_STUB:
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case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
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case X86II::MO_TLVP_PIC_BASE:
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Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
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// Subtract the pic base.
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Expr = MCBinaryExpr::CreateSub(Expr,
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MCSymbolRefExpr::Create(GetPICBaseSymbol(),
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case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
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case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
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case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
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case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
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case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
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case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
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case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
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case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
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case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
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case X86II::MO_PIC_BASE_OFFSET:
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
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Expr = MCSymbolRefExpr::Create(Sym, Ctx);
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// Subtract the pic base.
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Expr = MCBinaryExpr::CreateSub(Expr,
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MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
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if (MO.isJTI() && MAI.hasSetDirective()) {
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// If .set directive is supported, use it to reduce the number of
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// relocations the assembler will generate for differences between
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// local labels. This is only safe when the symbols are in the same
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// section so we are restricting it to jumptable references.
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MCSymbol *Label = Ctx.CreateTempSymbol();
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AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
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Expr = MCSymbolRefExpr::Create(Label, Ctx);
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Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(Expr,
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MCConstantExpr::Create(MO.getOffset(), Ctx),
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return MCOperand::CreateExpr(Expr);
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static void lower_subreg32(MCInst *MI, unsigned OpNo) {
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// Convert registers in the addr mode according to subreg32.
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unsigned Reg = MI->getOperand(OpNo).getReg();
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MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
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static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
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// Convert registers in the addr mode according to subreg64.
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for (unsigned i = 0; i != 4; ++i) {
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if (!MI->getOperand(OpNo+i).isReg()) continue;
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unsigned Reg = MI->getOperand(OpNo+i).getReg();
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if (Reg == 0) continue;
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MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
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/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
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static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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lower_subreg32(&OutMI, 0);
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/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
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static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
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OutMI.setOpcode(NewOpc);
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OutMI.addOperand(OutMI.getOperand(0));
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OutMI.addOperand(OutMI.getOperand(0));
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/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
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/// a short fixed-register form.
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static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
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unsigned ImmOp = Inst.getNumOperands() - 1;
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
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((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
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Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
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Inst.getNumOperands() == 2) && "Unexpected instruction!");
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// Check whether the destination register can be fixed.
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unsigned Reg = Inst.getOperand(0).getReg();
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if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
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// If so, rewrite the instruction.
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MCOperand Saved = Inst.getOperand(ImmOp);
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Inst.setOpcode(Opcode);
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Inst.addOperand(Saved);
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/// \brief Simplify things like MOV32rm to MOV32o32a.
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static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
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// Don't make these simplifications in 64-bit mode; other assemblers don't
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// perform them because they make the code larger.
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if (Printer.getSubtarget().is64Bit())
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bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
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unsigned AddrBase = IsStore;
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unsigned RegOp = IsStore ? 0 : 5;
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unsigned AddrOp = AddrBase + 3;
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assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
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Inst.getOperand(AddrBase + 0).isReg() && // base
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Inst.getOperand(AddrBase + 1).isImm() && // scale
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Inst.getOperand(AddrBase + 2).isReg() && // index register
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(Inst.getOperand(AddrOp).isExpr() || // address
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Inst.getOperand(AddrOp).isImm())&&
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Inst.getOperand(AddrBase + 4).isReg() && // segment
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"Unexpected instruction!");
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// Check whether the destination register can be fixed.
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unsigned Reg = Inst.getOperand(RegOp).getReg();
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if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
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// Check whether this is an absolute address.
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// FIXME: We know TLVP symbol refs aren't, but there should be a better way
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bool Absolute = true;
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if (Inst.getOperand(AddrOp).isExpr()) {
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const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
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if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
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if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
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(Inst.getOperand(AddrBase + 0).getReg() != 0 ||
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Inst.getOperand(AddrBase + 2).getReg() != 0 ||
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Inst.getOperand(AddrBase + 4).getReg() != 0 ||
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Inst.getOperand(AddrBase + 1).getImm() != 1))
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// If so, rewrite the instruction.
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MCOperand Saved = Inst.getOperand(AddrOp);
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Inst.setOpcode(Opcode);
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Inst.addOperand(Saved);
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void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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switch (MO.getType()) {
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) continue;
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MCOp = MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), Ctx));
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case MachineOperand::MO_GlobalAddress:
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MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
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case MachineOperand::MO_ExternalSymbol:
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MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
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case MachineOperand::MO_JumpTableIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
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case MachineOperand::MO_BlockAddress:
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MCOp = LowerSymbolOperand(MO,
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AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
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OutMI.addOperand(MCOp);
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// Handle a few special cases to eliminate operand modifiers.
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switch (OutMI.getOpcode()) {
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case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
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lower_lea64_32mem(&OutMI, 1);
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// LEA should have a segment register, but it must be empty.
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assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
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"Unexpected # of LEA operands");
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assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
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"LEA has segment specified!");
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case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
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case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
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case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
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case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
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case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
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case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
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case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
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case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
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case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
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case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
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case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
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case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
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case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
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case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
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case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
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case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
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case X86::MMX_V_SETALLONES:
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LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
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case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
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case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
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case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
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case X86::AVX_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::VXORPSrr); break;
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case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
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case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break;
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case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
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case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
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LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
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LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
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LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
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LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
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// TAILJMPr64, [WIN]CALL64r, [WIN]CALL64pcrel32 - These instructions have
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// register inputs modeled as normal uses instead of implicit uses. As such,
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// truncate off all but the first operand (the callee). FIXME: Change isel.
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case X86::TAILJMPr64:
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case X86::CALL64pcrel32:
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case X86::WINCALL64r:
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case X86::WINCALL64pcrel32: {
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unsigned Opcode = OutMI.getOpcode();
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MCOperand Saved = OutMI.getOperand(0);
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OutMI.setOpcode(Opcode);
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OutMI.addOperand(Saved);
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// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
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case X86::TAILJMPd64: {
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switch (OutMI.getOpcode()) {
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default: assert(0 && "Invalid opcode");
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case X86::TAILJMPr: Opcode = X86::JMP32r; break;
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case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
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MCOperand Saved = OutMI.getOperand(0);
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OutMI.setOpcode(Opcode);
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OutMI.addOperand(Saved);
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// The assembler backend wants to see branches in their small form and relax
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// them to their large form. The JIT can only handle the large form because
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// it does not do relaxation. For now, translate the large form to the
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case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
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case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
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case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
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case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
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case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
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case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
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case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
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case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
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case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
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case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
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case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
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case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
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case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
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case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
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case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
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case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
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case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
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// We don't currently select the correct instruction form for instructions
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// which have a short %eax, etc. form. Handle this by custom lowering, for
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// Note, we are currently not handling the following instructions:
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// MOV64ao8, MOV64o8a
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// XCHG16ar, XCHG32ar, XCHG64ar
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case X86::MOV8mr_NOREX:
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case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
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case X86::MOV8rm_NOREX:
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case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
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case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
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case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
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case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
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case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
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case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
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case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
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case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
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case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
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case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
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case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
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case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
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case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
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case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
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case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
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case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
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case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
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case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
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case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
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case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
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case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
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case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
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case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
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case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
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case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
497
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
498
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
499
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
500
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
501
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
502
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
503
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
504
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
505
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
506
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
507
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
508
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
509
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
510
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
511
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
512
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
517
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
518
X86MCInstLower MCInstLowering(Mang, *MF, *this);
519
switch (MI->getOpcode()) {
520
case TargetOpcode::DBG_VALUE:
521
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
523
raw_string_ostream OS(TmpStr);
524
PrintDebugValueComment(MI, OS);
525
OutStreamer.EmitRawText(StringRef(OS.str()));
529
// Emit nothing here but a comment if we can.
530
case X86::Int_MemBarrier:
531
if (OutStreamer.hasRawTextSupport())
532
OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
537
case X86::TAILJMPd64:
538
// Lower these as normal, but add some comments.
539
OutStreamer.AddComment("TAILCALL");
542
case X86::MOVPC32r: {
544
// This is a pseudo op for a two instruction sequence with a label, which
551
MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
552
TmpInst.setOpcode(X86::CALLpcrel32);
553
// FIXME: We would like an efficient form for this, so we don't have to do a
554
// lot of extra uniquing.
555
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
557
OutStreamer.EmitInstruction(TmpInst);
560
OutStreamer.EmitLabel(PICBase);
563
TmpInst.setOpcode(X86::POP32r);
564
TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
565
OutStreamer.EmitInstruction(TmpInst);
570
// Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
571
if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
574
// Okay, we have something like:
575
// EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
577
// For this, we want to print something like:
578
// MYGLOBAL + (. - PICBASE)
579
// However, we can't generate a ".", so just emit a new label here and refer
581
MCSymbol *DotSym = OutContext.CreateTempSymbol();
582
OutStreamer.EmitLabel(DotSym);
584
// Now that we have emitted the label, lower the complex operand expression.
585
MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
587
const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
588
const MCExpr *PICBase =
589
MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
590
DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
592
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
593
DotExpr, OutContext);
596
TmpInst.setOpcode(X86::ADD32ri);
597
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
598
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
599
TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
600
OutStreamer.EmitInstruction(TmpInst);
606
MCInstLowering.Lower(MI, TmpInst);
607
OutStreamer.EmitInstruction(TmpInst);