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//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//===----------------------------------------------------------------------===//
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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OS << "namespace llvm {\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
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OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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if (!Namespace.empty())
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const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
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if (!SubRegIndices.empty()) {
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OS << "\n// Subregister indices\n";
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Namespace = SubRegIndices[0]->getValueAsString("Namespace");
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoSubRegister,\n";
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for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
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OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
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OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
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if (!Namespace.empty())
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OS << "} // End llvm namespace \n";
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void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
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EmitSourceFileHeader("Register Information Header Fragment", OS);
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const std::string &TargetName = Target.getName();
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std::string ClassName = TargetName + "GenRegisterInfo";
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OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
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OS << "#include <string>\n\n";
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OS << "namespace llvm {\n\n";
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OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
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<< " explicit " << ClassName
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<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
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<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
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<< "unsigned Flavour) const;\n"
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<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
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<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
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<< " { return false; }\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
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<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register classes\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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OS << " " << RegisterClasses[i].getName() << "RegClassID";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const std::string &Name = RegisterClasses[i].getName();
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// Output the register class definition.
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OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
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<< " " << Name << "Class();\n"
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<< RegisterClasses[i].MethodProtos << " };\n";
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// Output the extern for the instance.
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OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
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// Output the extern for the pointer to the instance (should remove).
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OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
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<< Name << "RegClass;\n";
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OS << "} // end of namespace " << TargetName << "\n\n";
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OS << "} // End llvm namespace \n";
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static void addSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
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errs() << "Error: recursive sub-register relationship between"
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<< " register " << getQualifiedName(R)
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<< " and its sub-registers?\n";
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if (!SuperRegs[R].insert(S).second)
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SubRegs[S].insert(R);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SuperRegs.count(S))
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for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
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E = SuperRegs[S].end(); I != E; ++I)
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addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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static void addSubSuperReg(Record *R, Record *S,
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std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
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std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
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errs() << "Error: recursive sub-register relationship between"
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<< " register " << getQualifiedName(R)
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<< " and its sub-registers?\n";
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if (!SubRegs[R].insert(S).second)
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addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
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Aliases[R].insert(S);
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Aliases[S].insert(R);
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if (SubRegs.count(S))
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for (std::set<Record*>::iterator I = SubRegs[S].begin(),
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E = SubRegs[S].end(); I != E; ++I)
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addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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struct RegisterMaps {
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// Map SubRegIndex -> Register
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typedef std::map<Record*, Record*, LessRecord> SubRegMap;
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// Map Register -> SubRegMap
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typedef std::map<Record*, SubRegMap> SubRegMaps;
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SubRegMap &inferSubRegIndices(Record *Reg);
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// Composite SubRegIndex instances.
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// Map (SubRegIndex,SubRegIndex) -> SubRegIndex
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typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
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CompositeMap Composite;
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// Compute SubRegIndex compositions after inferSubRegIndices has run on all
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void computeComposites();
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// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
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RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
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SubRegMap &SRM = SubReg[Reg];
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std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
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std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
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if (SubRegs.size() != Indices.size())
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throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
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// First insert the direct subregs and make sure they are fully indexed.
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for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
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if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
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throw "SubRegIndex " + Indices[i]->getName()
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+ " appears twice in Register " + Reg->getName();
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inferSubRegIndices(SubRegs[i]);
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// Keep track of inherited subregs and how they can be reached.
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// Register -> (SubRegIndex, SubRegIndex)
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typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
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// Clone inherited subregs. Here the order is important - earlier subregs take
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for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
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SubRegMap &M = SubReg[SubRegs[i]];
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for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
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if (!SRM.insert(*si).second)
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Orphans[si->second] = std::make_pair(Indices[i], si->first);
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// Finally process the composites.
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ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
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for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
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DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
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throw "Invalid dag '" + Comps->getElement(i)->getAsString()
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+ "' in CompositeIndices";
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DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
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if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw "Invalid SubClassIndex in " + Pat->getAsString();
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// Resolve list of subreg indices into R2.
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for (DagInit::const_arg_iterator di = Pat->arg_begin(),
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de = Pat->arg_end(); di != de; ++di) {
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DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw "Invalid SubClassIndex in " + Pat->getAsString();
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SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
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if (ni == SubReg[R2].end())
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throw "Composite " + Pat->getAsString() + " refers to bad index in "
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// Insert composite index. Allow overriding inherited indices etc.
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SRM[BaseIdxInit->getDef()] = R2;
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// R2 is now directly addressable, no longer an orphan.
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// Now, Orphans contains the inherited subregisters without a direct index.
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if (!Orphans.empty()) {
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errs() << "Error: Register " << getQualifiedName(Reg)
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<< " inherited subregisters without an index:\n";
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for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
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errs() << " " << getQualifiedName(i->first)
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<< " = " << i->second.first->getName()
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<< ", " << i->second.second->getName() << "\n";
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void RegisterMaps::computeComposites() {
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for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
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Record *Reg1 = sri->first;
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const SubRegMap &SRM1 = sri->second;
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for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
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Record *Idx1 = i1->first;
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Record *Reg2 = i1->second;
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// Ignore identity compositions.
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// If Reg2 has no subregs, Idx1 doesn't compose.
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if (!SubReg.count(Reg2))
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const SubRegMap &SRM2 = SubReg[Reg2];
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// Try composing Idx1 with another SubRegIndex.
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for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
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std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
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Record *Reg3 = i2->second;
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// OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
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for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
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// Ignore identity compositions.
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if (i1d->second == Reg3) {
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std::pair<CompositeMap::iterator,bool> Ins =
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Composite.insert(std::make_pair(IdxPair, i1d->first));
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// Conflicting composition?
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if (!Ins.second && Ins.first->second != i1d->first) {
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errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
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<< " and " << getQualifiedName(IdxPair.second)
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<< " compose ambiguously as "
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<< getQualifiedName(Ins.first->second) << " or "
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<< getQualifiedName(i1d->first) << "\n";
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// We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
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// compositions, so remove any mappings of that form.
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for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
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CompositeMap::iterator j = i;
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if (j->first.second == j->second)
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class RegisterSorter {
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std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
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RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
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: RegisterSubRegs(RS) {}
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bool operator()(Record *RegA, Record *RegB) {
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// B is sub-register of A.
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return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
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// RegisterInfoEmitter::run - Main register file description emitter.
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void RegisterInfoEmitter::run(raw_ostream &OS) {
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CodeGenTarget Target;
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EmitSourceFileHeader("Register Information Source Fragment", OS);
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OS << "namespace llvm {\n\n";
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// Start out by emitting each of the register classes... to do this, we build
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// a set of registers which belong to a register class, this is to ensure that
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// each register is only in a single register class.
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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// Loop over all of the register classes... emitting each one.
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OS << "namespace { // Register classes...\n";
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// RegClassesBelongedTo - Keep track of which register classes each reg
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std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
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// Emit the register enum value arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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<< " static const unsigned " << Name
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for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
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Record *Reg = RC.Elements[i];
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OS << getQualifiedName(Reg) << ", ";
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// Keep track of which regclasses this register is in.
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RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
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// Emit the ValueType arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName() + "VTs";
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// Emit the register list now.
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<< " Register Class Value Types...\n"
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<< " static const EVT " << Name
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for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
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OS << getEnumName(RC.VTs[i]) << ", ";
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OS << "MVT::Other\n };\n\n";
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OS << "} // end anonymous namespace\n\n";
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// Now that all of the structs have been emitted, emit the instances.
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register class instances\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " " << RegisterClasses[i].getName() << "Class\t"
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<< RegisterClasses[i].getName() << "RegClass;\n";
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std::map<unsigned, std::set<unsigned> > SuperClassMap;
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std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
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unsigned NumSubRegIndices = Target.getSubRegIndices().size();
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if (NumSubRegIndices) {
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// Emit the sub-register classes for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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std::vector<Record*> SRC(NumSubRegIndices);
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for (DenseMap<Record*,Record*>::const_iterator
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i = RC.SubRegClasses.begin(),
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e = RC.SubRegClasses.end(); i != e; ++i) {
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unsigned idx = Target.getSubRegIndexNo(i->first);
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SRC.at(idx-1) = i->second;
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// Find the register class number of i->second for SuperRegClassMap.
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for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
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if (RC2.TheDef == i->second) {
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SuperRegClassMap[rc2].insert(rc);
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Sub-register Classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "SubRegClasses[] = {\n ";
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for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
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OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
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// Emit the super-register classes for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Super-register Classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "SuperRegClasses[] = {\n ";
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std::map<unsigned, std::set<unsigned> >::iterator I =
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SuperRegClassMap.find(rc);
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if (I != SuperRegClassMap.end()) {
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for (std::set<unsigned>::iterator II = I->second.begin(),
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EE = I->second.end(); II != EE; ++II) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << (!Empty ? ", " : "") << "NULL";
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// No subregindices in this target
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OS << " static const TargetRegisterClass* const "
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<< "NullRegClasses[] = { NULL };\n\n";
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// Emit the sub-classes array for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Register Class sub-classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "Subclasses[] = {\n ";
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for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
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// Sub-classes are used to determine if a virtual register can be used
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// as an instruction operand, or if it must be copied first.
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if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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std::map<unsigned, std::set<unsigned> >::iterator SCMI =
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SuperClassMap.find(rc2);
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if (SCMI == SuperClassMap.end()) {
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SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
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SCMI = SuperClassMap.find(rc2);
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SCMI->second.insert(rc);
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OS << (!Empty ? ", " : "") << "NULL";
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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<< " Register Class super-classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "Superclasses[] = {\n ";
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std::map<unsigned, std::set<unsigned> >::iterator I =
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SuperClassMap.find(rc);
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if (I != SuperClassMap.end()) {
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for (std::set<unsigned>::iterator II = I->second.begin(),
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EE = I->second.end(); II != EE; ++II) {
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const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << (!Empty ? ", " : "") << "NULL";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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OS << RC.MethodBodies << "\n";
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OS << RC.getName() << "Class::" << RC.getName()
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<< "Class() : TargetRegisterClass("
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<< RC.getName() + "RegClassID" << ", "
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<< '\"' << RC.getName() << "\", "
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<< RC.getName() + "VTs" << ", "
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<< RC.getName() + "Subclasses" << ", "
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<< RC.getName() + "Superclasses" << ", "
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<< (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
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<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
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<< RC.SpillSize/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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<< RC.CopyCost << ", "
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<< RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
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OS << "\nnamespace {\n";
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OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
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// Emit register sub-registers / super-registers, aliases...
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std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
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std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
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std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
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typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
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// Add information that R aliases all of the elements in the list... and
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// that everything in the list aliases R.
595
for (unsigned j = 0, e = LI.size(); j != e; ++j) {
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if (RegisterAliases[R].count(Reg))
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errs() << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg)
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<< " specified multiple times!\n";
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RegisterAliases[R].insert(Reg);
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if (RegisterAliases[Reg].count(R))
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errs() << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg)
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<< " specified multiple times!\n";
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RegisterAliases[Reg].insert(R);
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// Process sub-register sets.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
615
// Process sub-register set and add aliases information.
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for (unsigned j = 0, e = LI.size(); j != e; ++j) {
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Record *SubReg = LI[j];
618
if (RegisterSubRegs[R].count(SubReg))
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errs() << "Warning: register " << getQualifiedName(SubReg)
620
<< " specified as a sub-register of " << getQualifiedName(R)
621
<< " multiple times!\n";
622
addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
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// Print the SubregHashTable, a simple quadratically probed
628
// hash table for determining if a register is a subregister
629
// of another register.
630
unsigned NumSubRegs = 0;
631
std::map<Record*, unsigned> RegNo;
632
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
633
RegNo[Regs[i].TheDef] = i;
634
NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
637
unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
638
unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
639
std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
641
unsigned hashMisses = 0;
643
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
644
Record* R = Regs[i].TheDef;
645
for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
646
E = RegisterSubRegs[R].end(); I != E; ++I) {
648
// We have to increase the indices of both registers by one when
649
// computing the hash because, in the generated code, there
650
// will be an extra empty slot at register 0.
651
size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
652
unsigned ProbeAmt = 2;
653
while (SubregHashTable[index*2] != ~0U &&
654
SubregHashTable[index*2+1] != ~0U) {
655
index = (index + ProbeAmt) & (SubregHashTableSize-1);
661
SubregHashTable[index*2] = i;
662
SubregHashTable[index*2+1] = RegNo[RJ];
666
OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
668
if (SubregHashTableSize) {
669
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
671
OS << " const unsigned SubregHashTable[] = { ";
672
for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
674
// Insert spaces for nice formatting.
677
if (SubregHashTable[2*i] != ~0U) {
678
OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
679
<< getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
681
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
685
unsigned Idx = SubregHashTableSize*2-2;
686
if (SubregHashTable[Idx] != ~0U) {
688
<< getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
689
<< getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
691
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
694
OS << " const unsigned SubregHashTableSize = "
695
<< SubregHashTableSize << ";\n";
697
OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
698
<< " const unsigned SubregHashTableSize = 1;\n";
701
delete [] SubregHashTable;
704
// Print the AliasHashTable, a simple quadratically probed
705
// hash table for determining if a register aliases another register.
706
unsigned NumAliases = 0;
708
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
709
RegNo[Regs[i].TheDef] = i;
710
NumAliases += RegisterAliases[Regs[i].TheDef].size();
713
unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
714
unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
715
std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
719
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
720
Record* R = Regs[i].TheDef;
721
for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
722
E = RegisterAliases[R].end(); I != E; ++I) {
724
// We have to increase the indices of both registers by one when
725
// computing the hash because, in the generated code, there
726
// will be an extra empty slot at register 0.
727
size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
728
unsigned ProbeAmt = 2;
729
while (AliasesHashTable[index*2] != ~0U &&
730
AliasesHashTable[index*2+1] != ~0U) {
731
index = (index + ProbeAmt) & (AliasesHashTableSize-1);
737
AliasesHashTable[index*2] = i;
738
AliasesHashTable[index*2+1] = RegNo[RJ];
742
OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
744
if (AliasesHashTableSize) {
745
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
747
OS << " const unsigned AliasesHashTable[] = { ";
748
for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
750
// Insert spaces for nice formatting.
753
if (AliasesHashTable[2*i] != ~0U) {
754
OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
755
<< getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
757
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
761
unsigned Idx = AliasesHashTableSize*2-2;
762
if (AliasesHashTable[Idx] != ~0U) {
764
<< getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
765
<< getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
767
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
770
OS << " const unsigned AliasesHashTableSize = "
771
<< AliasesHashTableSize << ";\n";
773
OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
774
<< " const unsigned AliasesHashTableSize = 1;\n";
777
delete [] AliasesHashTable;
779
if (!RegisterAliases.empty())
780
OS << "\n\n // Register Alias Sets...\n";
782
// Emit the empty alias list
783
OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
784
// Loop over all of the registers which have aliases, emitting the alias list
786
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
787
I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
788
if (I->second.empty())
790
OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
791
for (std::set<Record*>::iterator ASI = I->second.begin(),
792
E = I->second.end(); ASI != E; ++ASI)
793
OS << getQualifiedName(*ASI) << ", ";
797
if (!RegisterSubRegs.empty())
798
OS << "\n\n // Register Sub-registers Sets...\n";
800
// Emit the empty sub-registers list
801
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
802
// Loop over all of the registers which have sub-registers, emitting the
803
// sub-registers list to memory.
804
for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
805
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
806
if (I->second.empty())
808
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
809
std::vector<Record*> SubRegsVector;
810
for (std::set<Record*>::iterator ASI = I->second.begin(),
811
E = I->second.end(); ASI != E; ++ASI)
812
SubRegsVector.push_back(*ASI);
813
RegisterSorter RS(RegisterSubRegs);
814
std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
815
for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
816
OS << getQualifiedName(SubRegsVector[i]) << ", ";
820
if (!RegisterSuperRegs.empty())
821
OS << "\n\n // Register Super-registers Sets...\n";
823
// Emit the empty super-registers list
824
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
825
// Loop over all of the registers which have super-registers, emitting the
826
// super-registers list to memory.
827
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
828
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
829
if (I->second.empty())
831
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
833
std::vector<Record*> SuperRegsVector;
834
for (std::set<Record*>::iterator ASI = I->second.begin(),
835
E = I->second.end(); ASI != E; ++ASI)
836
SuperRegsVector.push_back(*ASI);
837
RegisterSorter RS(RegisterSubRegs);
838
std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
839
for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
840
OS << getQualifiedName(SuperRegsVector[i]) << ", ";
844
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
845
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
847
// Now that register alias and sub-registers sets have been emitted, emit the
848
// register descriptors now.
849
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
850
const CodeGenRegister &Reg = Regs[i];
852
OS << Reg.getName() << "\",\t";
853
if (!RegisterAliases[Reg.TheDef].empty())
854
OS << Reg.getName() << "_AliasSet,\t";
856
OS << "Empty_AliasSet,\t";
857
if (!RegisterSubRegs[Reg.TheDef].empty())
858
OS << Reg.getName() << "_SubRegsSet,\t";
860
OS << "Empty_SubRegsSet,\t";
861
if (!RegisterSuperRegs[Reg.TheDef].empty())
862
OS << Reg.getName() << "_SuperRegsSet },\n";
864
OS << "Empty_SuperRegsSet },\n";
866
OS << " };\n"; // End of register descriptors...
868
// Emit SubRegIndex names, skipping 0
869
const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
870
OS << "\n const char *const SubRegIndexTable[] = { \"";
871
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
872
OS << SubRegIndices[i]->getName();
877
OS << "}\n\n"; // End of anonymous namespace...
879
std::string ClassName = Target.getName() + "GenRegisterInfo";
881
// Calculate the mapping of subregister+index pairs to physical registers.
882
RegisterMaps RegMaps;
884
// Emit the subregister + index mapping function based on the information
886
OS << "unsigned " << ClassName
887
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
888
<< " switch (RegNo) {\n"
889
<< " default:\n return 0;\n";
890
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
891
RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
894
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
895
OS << " switch (Index) {\n";
896
OS << " default: return 0;\n";
897
for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
898
ie = SRM.end(); ii != ie; ++ii)
899
OS << " case " << getQualifiedName(ii->first)
900
<< ": return " << getQualifiedName(ii->second) << ";\n";
901
OS << " };\n" << " break;\n";
904
OS << " return 0;\n";
907
OS << "unsigned " << ClassName
908
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
909
<< " switch (RegNo) {\n"
910
<< " default:\n return 0;\n";
911
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
912
RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
915
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
916
for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
917
ie = SRM.end(); ii != ie; ++ii)
918
OS << " if (SubRegNo == " << getQualifiedName(ii->second)
919
<< ") return " << getQualifiedName(ii->first) << ";\n";
920
OS << " return 0;\n";
923
OS << " return 0;\n";
926
// Emit composeSubRegIndices
927
RegMaps.computeComposites();
928
OS << "unsigned " << ClassName
929
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
930
<< " switch (IdxA) {\n"
931
<< " default:\n return IdxB;\n";
932
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
934
for (unsigned j = 0; j != e; ++j) {
935
if (Record *Comp = RegMaps.Composite.lookup(
936
std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
938
OS << " case " << getQualifiedName(SubRegIndices[i])
939
<< ": switch(IdxB) {\n default: return IdxB;\n";
942
OS << " case " << getQualifiedName(SubRegIndices[j])
943
<< ": return " << getQualifiedName(Comp) << ";\n";
951
// Emit the constructor of the class...
952
OS << ClassName << "::" << ClassName
953
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
954
<< " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
955
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
956
<< " SubRegIndexTable,\n"
957
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
958
<< " SubregHashTable, SubregHashTableSize,\n"
959
<< " AliasesHashTable, AliasesHashTableSize) {\n"
962
// Collect all information about dwarf register numbers
964
// First, just pull all provided information to the map
965
unsigned maxLength = 0;
966
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
967
Record *Reg = Regs[i].TheDef;
968
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
969
maxLength = std::max((size_t)maxLength, RegNums.size());
970
if (DwarfRegNums.count(Reg))
971
errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
972
<< "specified multiple times\n";
973
DwarfRegNums[Reg] = RegNums;
976
// Now we know maximal length of number list. Append -1's, where needed
977
for (DwarfRegNumsMapTy::iterator
978
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
979
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
980
I->second.push_back(-1);
982
// Emit information about the dwarf register numbers.
983
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
984
<< "unsigned Flavour) const {\n"
985
<< " switch (Flavour) {\n"
987
<< " assert(0 && \"Unknown DWARF flavour\");\n"
990
for (unsigned i = 0, e = maxLength; i != e; ++i) {
991
OS << " case " << i << ":\n"
992
<< " switch (RegNum) {\n"
994
<< " assert(0 && \"Invalid RegNum\");\n"
997
// Sort by name to get a stable order.
1000
for (DwarfRegNumsMapTy::iterator
1001
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1002
int RegNo = I->second[i];
1004
OS << " case " << getQualifiedName(I->first) << ":\n"
1005
<< " return " << RegNo << ";\n";
1007
OS << " case " << getQualifiedName(I->first) << ":\n"
1008
<< " assert(0 && \"Invalid register for this mode\");\n"
1016
OS << "} // End llvm namespace \n";
added
removed
libclamav/c++/llvm/utils/TableGen/RegisterInfoEmitter.cpp
