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//===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across PowerPC chips sets
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def BPU : FuncUnit; // Branch unit
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def SLU : FuncUnit; // Store/load unit
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def SRU : FuncUnit; // special register unit
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def IU1 : FuncUnit; // integer unit 1 (simple)
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def IU2 : FuncUnit; // integer unit 2 (complex)
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def FPU1 : FuncUnit; // floating point unit 1
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def FPU2 : FuncUnit; // floating point unit 2
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def VPU : FuncUnit; // vector permutation unit
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def VIU1 : FuncUnit; // vector integer unit 1 (simple)
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def VIU2 : FuncUnit; // vector integer unit 2 (complex)
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def VFPU : FuncUnit; // vector floating point unit
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for PowerPC
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def IntGeneral : InstrItinClass;
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def IntCompare : InstrItinClass;
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def IntDivD : InstrItinClass;
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def IntDivW : InstrItinClass;
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def IntMFFS : InstrItinClass;
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def IntMFVSCR : InstrItinClass;
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def IntMTFSB0 : InstrItinClass;
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def IntMTSRD : InstrItinClass;
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def IntMulHD : InstrItinClass;
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def IntMulHW : InstrItinClass;
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def IntMulHWU : InstrItinClass;
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def IntMulLI : InstrItinClass;
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def IntRFID : InstrItinClass;
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def IntRotateD : InstrItinClass;
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def IntRotate : InstrItinClass;
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def IntShift : InstrItinClass;
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def IntTrapD : InstrItinClass;
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def IntTrapW : InstrItinClass;
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def BrB : InstrItinClass;
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def BrCR : InstrItinClass;
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def BrMCR : InstrItinClass;
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def BrMCRX : InstrItinClass;
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def LdStDCBA : InstrItinClass;
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def LdStDCBF : InstrItinClass;
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def LdStDCBI : InstrItinClass;
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def LdStGeneral : InstrItinClass;
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def LdStDSS : InstrItinClass;
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def LdStICBI : InstrItinClass;
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def LdStUX : InstrItinClass;
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def LdStLD : InstrItinClass;
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def LdStLDARX : InstrItinClass;
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def LdStLFD : InstrItinClass;
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def LdStLFDU : InstrItinClass;
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def LdStLHA : InstrItinClass;
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def LdStLMW : InstrItinClass;
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def LdStLVecX : InstrItinClass;
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def LdStLWA : InstrItinClass;
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def LdStLWARX : InstrItinClass;
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def LdStSLBIA : InstrItinClass;
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def LdStSLBIE : InstrItinClass;
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def LdStSTD : InstrItinClass;
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def LdStSTDCX : InstrItinClass;
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def LdStSTVEBX : InstrItinClass;
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def LdStSTWCX : InstrItinClass;
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def LdStSync : InstrItinClass;
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def SprISYNC : InstrItinClass;
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def SprMFSR : InstrItinClass;
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def SprMTMSR : InstrItinClass;
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def SprMTSR : InstrItinClass;
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def SprTLBSYNC : InstrItinClass;
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def SprMFCR : InstrItinClass;
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def SprMFMSR : InstrItinClass;
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def SprMFSPR : InstrItinClass;
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def SprMFTB : InstrItinClass;
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def SprMTSPR : InstrItinClass;
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def SprMTSRIN : InstrItinClass;
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def SprRFI : InstrItinClass;
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def SprSC : InstrItinClass;
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def FPGeneral : InstrItinClass;
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def FPCompare : InstrItinClass;
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def FPDivD : InstrItinClass;
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def FPDivS : InstrItinClass;
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def FPFused : InstrItinClass;
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def FPRes : InstrItinClass;
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def FPSqrt : InstrItinClass;
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def VecGeneral : InstrItinClass;
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def VecFP : InstrItinClass;
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def VecFPCompare : InstrItinClass;
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def VecComplex : InstrItinClass;
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def VecPerm : InstrItinClass;
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def VecFPRound : InstrItinClass;
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def VecVSL : InstrItinClass;
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def VecVSR : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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include "PPCScheduleG3.td"
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include "PPCScheduleG4.td"
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include "PPCScheduleG4Plus.td"
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include "PPCScheduleG5.td"
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//===----------------------------------------------------------------------===//
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// Instruction to itinerary class map - When add new opcodes to the supported
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// set, refer to the following table to determine which itinerary class the
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// opcode itinerary class
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// ====== ===============
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// dcbtst LdStGeneral
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// sthbrx LdStGeneral
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// stwbrx LdStGeneral
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// tlbsync SprTLBSYNC
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// vaddcuw VecGeneral
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// vaddsbs VecGeneral
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// vaddshs VecGeneral
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// vaddsws VecGeneral
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// vaddubm VecGeneral
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// vaddubs VecGeneral
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// vadduhm VecGeneral
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// vadduhs VecGeneral
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// vadduwm VecGeneral
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// vadduws VecGeneral
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// vcmpbfp VecFPCompare
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// vcmpeqfp VecFPCompare
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// vcmpequb VecGeneral
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// vcmpequh VecGeneral
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// vcmpequw VecGeneral
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// vcmpgefp VecFPCompare
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// vcmpgtfp VecFPCompare
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// vcmpgtsb VecGeneral
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// vcmpgtsh VecGeneral
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// vcmpgtsw VecGeneral
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// vcmpgtub VecGeneral
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// vcmpgtuh VecGeneral
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// vcmpgtuw VecGeneral
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// vmaxfp VecFPCompare
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// vmhaddshs VecComplex
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// vmhraddshs VecComplex
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// vminfp VecFPCompare
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// vmladduhm VecComplex
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// vmsummbm VecComplex
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// vmsumshm VecComplex
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// vmsumshs VecComplex
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// vmsumubm VecComplex
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// vmsumuhm VecComplex
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// vmsumuhs VecComplex
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// vmulesb VecComplex
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// vmulesh VecComplex
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// vmuleub VecComplex
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// vmuleuh VecComplex
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// vmulosb VecComplex
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// vmulosh VecComplex
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// vmuloub VecComplex
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// vmulouh VecComplex
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// vsubcuw VecGeneral
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// vsubsbs VecGeneral
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// vsubshs VecGeneral
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// vsubsws VecGeneral
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// vsububm VecGeneral
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// vsububs VecGeneral
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// vsubuhm VecGeneral
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// vsubuhs VecGeneral
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// vsubuwm VecGeneral
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// vsubuws VecGeneral
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// vsum2sws VecComplex
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// vsum4sbs VecComplex
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// vsum4shs VecComplex
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// vsum4ubs VecComplex
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// vsumsws VecComplex