2
#include "exec/gdbstub.h"
4
#include "qemu/host-utils.h"
5
#include "sysemu/arch_init.h"
6
#include "sysemu/sysemu.h"
7
#include "qemu/bitops.h"
9
#ifndef CONFIG_USER_ONLY
10
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11
int access_type, int is_user,
12
hwaddr *phys_ptr, int *prot,
13
target_ulong *page_size);
16
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
20
/* VFP data registers are always little-endian. */
21
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
23
stfq_le_p(buf, env->vfp.regs[reg]);
26
if (arm_feature(env, ARM_FEATURE_NEON)) {
27
/* Aliases for Q regs. */
30
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
31
stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
35
switch (reg - nregs) {
36
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
43
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
47
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
49
env->vfp.regs[reg] = ldfq_le_p(buf);
52
if (arm_feature(env, ARM_FEATURE_NEON)) {
55
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
56
env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
60
switch (reg - nregs) {
61
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
63
case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
68
static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
72
/* 128 bit FP register */
73
stfq_le_p(buf, env->vfp.regs[reg * 2]);
74
stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
78
stl_p(buf, vfp_get_fpsr(env));
82
stl_p(buf, vfp_get_fpcr(env));
89
static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
93
/* 128 bit FP register */
94
env->vfp.regs[reg * 2] = ldfq_le_p(buf);
95
env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
99
vfp_set_fpsr(env, ldl_p(buf));
103
vfp_set_fpcr(env, ldl_p(buf));
110
static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
113
if (ri->type & ARM_CP_64BIT) {
114
*value = CPREG_FIELD64(env, ri);
116
*value = CPREG_FIELD32(env, ri);
121
static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
124
if (ri->type & ARM_CP_64BIT) {
125
CPREG_FIELD64(env, ri) = value;
127
CPREG_FIELD32(env, ri) = value;
132
static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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/* Raw read of a coprocessor register (as needed for migration, etc)
136
* return true on success, false if the read is impossible for some reason.
138
if (ri->type & ARM_CP_CONST) {
140
} else if (ri->raw_readfn) {
141
return (ri->raw_readfn(env, ri, v) == 0);
142
} else if (ri->readfn) {
143
return (ri->readfn(env, ri, v) == 0);
145
if (ri->type & ARM_CP_64BIT) {
146
*v = CPREG_FIELD64(env, ri);
148
*v = CPREG_FIELD32(env, ri);
154
static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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/* Raw write of a coprocessor register (as needed for migration, etc).
158
* Return true on success, false if the write is impossible for some reason.
159
* Note that constant registers are treated as write-ignored; the
160
* caller should check for success by whether a readback gives the
163
if (ri->type & ARM_CP_CONST) {
165
} else if (ri->raw_writefn) {
166
return (ri->raw_writefn(env, ri, v) == 0);
167
} else if (ri->writefn) {
168
return (ri->writefn(env, ri, v) == 0);
170
if (ri->type & ARM_CP_64BIT) {
171
CPREG_FIELD64(env, ri) = v;
173
CPREG_FIELD32(env, ri) = v;
179
bool write_cpustate_to_list(ARMCPU *cpu)
181
/* Write the coprocessor state from cpu->env to the (index,value) list. */
185
for (i = 0; i < cpu->cpreg_array_len; i++) {
186
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
187
const ARMCPRegInfo *ri;
189
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
194
if (ri->type & ARM_CP_NO_MIGRATE) {
197
if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
201
cpu->cpreg_values[i] = v;
206
bool write_list_to_cpustate(ARMCPU *cpu)
211
for (i = 0; i < cpu->cpreg_array_len; i++) {
212
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
213
uint64_t v = cpu->cpreg_values[i];
215
const ARMCPRegInfo *ri;
217
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
222
if (ri->type & ARM_CP_NO_MIGRATE) {
225
/* Write value and confirm it reads back as written
226
* (to catch read-only registers and partially read-only
227
* registers where the incoming migration value doesn't match)
229
if (!write_raw_cp_reg(&cpu->env, ri, v) ||
230
!read_raw_cp_reg(&cpu->env, ri, &readback) ||
238
static void add_cpreg_to_list(gpointer key, gpointer opaque)
240
ARMCPU *cpu = opaque;
242
const ARMCPRegInfo *ri;
244
regidx = *(uint32_t *)key;
245
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
247
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
248
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
249
/* The value array need not be initialized at this point */
250
cpu->cpreg_array_len++;
254
static void count_cpreg(gpointer key, gpointer opaque)
256
ARMCPU *cpu = opaque;
258
const ARMCPRegInfo *ri;
260
regidx = *(uint32_t *)key;
261
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
263
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
264
cpu->cpreg_array_len++;
268
static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
270
uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
271
uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
282
static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
284
GList **plist = udata;
286
*plist = g_list_prepend(*plist, key);
289
void init_cpreg_list(ARMCPU *cpu)
291
/* Initialise the cpreg_tuples[] array based on the cp_regs hash.
292
* Note that we require cpreg_tuples[] to be sorted by key ID.
297
g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
299
keys = g_list_sort(keys, cpreg_key_compare);
301
cpu->cpreg_array_len = 0;
303
g_list_foreach(keys, count_cpreg, cpu);
305
arraylen = cpu->cpreg_array_len;
306
cpu->cpreg_indexes = g_new(uint64_t, arraylen);
307
cpu->cpreg_values = g_new(uint64_t, arraylen);
308
cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
309
cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
310
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
311
cpu->cpreg_array_len = 0;
313
g_list_foreach(keys, add_cpreg_to_list, cpu);
315
assert(cpu->cpreg_array_len == arraylen);
320
static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
322
env->cp15.c3 = value;
323
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
327
static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
329
if (env->cp15.c13_fcse != value) {
330
/* Unlike real hardware the qemu TLB uses virtual addresses,
331
* not modified virtual addresses, so this causes a TLB flush.
334
env->cp15.c13_fcse = value;
338
static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
341
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
342
/* For VMSA (when not using the LPAE long descriptor page table
343
* format) this register includes the ASID, so do a TLB flush.
344
* For PMSA it is purely a process ID and no action is needed.
348
env->cp15.c13_context = value;
352
static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
355
/* Invalidate all (TLBIALL) */
360
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
363
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
364
tlb_flush_page(env, value & TARGET_PAGE_MASK);
368
static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
371
/* Invalidate by ASID (TLBIASID) */
372
tlb_flush(env, value == 0);
376
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
379
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
380
tlb_flush_page(env, value & TARGET_PAGE_MASK);
384
static const ARMCPRegInfo cp_reginfo[] = {
385
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
386
* version" bits will read as a reserved value, which should cause
387
* Linux to not try to use the debug hardware.
389
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
390
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* MMU Domain access control / MPU write buffer control */
392
{ .name = "DACR", .cp = 15,
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.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
395
.resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
396
{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
398
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
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{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
401
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
402
/* ??? This covers not just the impdef TLB lockdown registers but also
403
* some v7VMSA registers relating to TEX remap, so it is overly broad.
405
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
406
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
407
/* MMU TLB control. Note that the wildcarding means we cover not just
408
* the unified TLB ops but also the dside/iside/inner-shareable variants.
410
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
411
.opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
412
.type = ARM_CP_NO_MIGRATE },
413
{ .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
414
.opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
415
.type = ARM_CP_NO_MIGRATE },
416
{ .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
417
.opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
418
.type = ARM_CP_NO_MIGRATE },
419
{ .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
420
.opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
421
.type = ARM_CP_NO_MIGRATE },
422
/* Cache maintenance ops; some of this space may be overridden later. */
423
{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
424
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
425
.type = ARM_CP_NOP | ARM_CP_OVERRIDE },
429
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
430
/* Not all pre-v6 cores implemented this WFI, so this is slightly
433
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
434
.access = PL1_W, .type = ARM_CP_WFI },
438
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
439
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
440
* is UNPREDICTABLE; we choose to NOP as most implementations do).
442
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
443
.access = PL1_W, .type = ARM_CP_WFI },
444
/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
445
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
446
* OMAPCP will override this space.
448
{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
449
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
451
{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
452
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
454
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
455
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
456
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
461
static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
463
if (env->cp15.c1_coproc != value) {
464
env->cp15.c1_coproc = value;
465
/* ??? Is this safe when called from within a TB? */
471
static const ARMCPRegInfo v6_cp_reginfo[] = {
472
/* prefetch by MVA in v6, NOP in v7 */
473
{ .name = "MVA_prefetch",
474
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
475
.access = PL1_W, .type = ARM_CP_NOP },
476
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
477
.access = PL0_W, .type = ARM_CP_NOP },
478
{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
479
.access = PL0_W, .type = ARM_CP_NOP },
480
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
481
.access = PL0_W, .type = ARM_CP_NOP },
482
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
483
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
485
/* Watchpoint Fault Address Register : should actually only be present
486
* for 1136, 1176, 11MPCore.
488
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
489
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
490
{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
491
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
492
.resetvalue = 0, .writefn = cpacr_write },
497
static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
500
/* Generic performance monitor register read function for where
501
* user access may be allowed by PMUSERENR.
503
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
506
*value = CPREG_FIELD32(env, ri);
510
static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
513
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
516
/* only the DP, X, D and E bits are writable */
517
env->cp15.c9_pmcr &= ~0x39;
518
env->cp15.c9_pmcr |= (value & 0x39);
522
static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
525
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
529
env->cp15.c9_pmcnten |= value;
533
static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
536
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
540
env->cp15.c9_pmcnten &= ~value;
544
static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
547
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
550
env->cp15.c9_pmovsr &= ~value;
554
static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
557
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
560
env->cp15.c9_pmxevtyper = value & 0xff;
564
static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
567
env->cp15.c9_pmuserenr = value & 1;
571
static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
574
/* We have no event counters so only the C bit can be changed */
576
env->cp15.c9_pminten |= value;
580
static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
584
env->cp15.c9_pminten &= ~value;
588
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
591
ARMCPU *cpu = arm_env_get_cpu(env);
592
*value = cpu->ccsidr[env->cp15.c0_cssel];
596
static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
599
env->cp15.c0_cssel = value & 0xf;
603
static const ARMCPRegInfo v7_cp_reginfo[] = {
604
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
607
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
608
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
609
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
610
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
611
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
612
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
613
.access = PL1_W, .type = ARM_CP_NOP },
614
/* Performance monitors are implementation defined in v7,
615
* but with an ARM recommended set of registers, which we
616
* follow (although we don't actually implement any counters)
618
* Performance registers fall into three categories:
619
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
620
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
621
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
622
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
623
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
625
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
626
.access = PL0_RW, .resetvalue = 0,
627
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
628
.readfn = pmreg_read, .writefn = pmcntenset_write,
629
.raw_readfn = raw_read, .raw_writefn = raw_write },
630
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
631
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
632
.readfn = pmreg_read, .writefn = pmcntenclr_write,
633
.type = ARM_CP_NO_MIGRATE },
634
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
635
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
636
.readfn = pmreg_read, .writefn = pmovsr_write,
637
.raw_readfn = raw_read, .raw_writefn = raw_write },
638
/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
641
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
642
.access = PL0_W, .type = ARM_CP_NOP },
643
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
644
* We choose to RAZ/WI. XXX should respect PMUSERENR.
646
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
647
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
648
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
649
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
650
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
651
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
653
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
654
.readfn = pmreg_read, .writefn = pmxevtyper_write,
655
.raw_readfn = raw_read, .raw_writefn = raw_write },
656
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
657
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
658
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
659
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
660
.access = PL0_R | PL1_RW,
661
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
663
.writefn = pmuserenr_write, .raw_writefn = raw_write },
664
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
666
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
668
.writefn = pmintenset_write, .raw_writefn = raw_write },
669
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
670
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
671
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
672
.resetvalue = 0, .writefn = pmintenclr_write, },
673
{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
674
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
675
{ .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
676
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
677
.writefn = csselr_write, .resetvalue = 0 },
678
/* Auxiliary ID register: this actually has an IMPDEF value but for now
679
* just RAZ for all cores:
681
{ .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
682
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
686
static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
693
static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
696
/* This is a helper function because the user access rights
697
* depend on the value of the TEECR.
699
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
702
*value = env->teehbr;
706
static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
709
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
716
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
717
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
718
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
720
.writefn = teecr_write },
721
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
722
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
723
.resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
724
.readfn = teehbr_read, .writefn = teehbr_write },
728
static const ARMCPRegInfo v6k_cp_reginfo[] = {
729
{ .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
730
.opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
732
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
733
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
735
.fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
736
.resetfn = arm_cp_reset_ignore },
737
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
738
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
739
.access = PL0_R|PL1_W,
740
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
741
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
742
.access = PL0_R|PL1_W,
743
.fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
744
.resetfn = arm_cp_reset_ignore },
745
{ .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
746
.opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
748
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
752
#ifndef CONFIG_USER_ONLY
754
static uint64_t gt_get_countervalue(CPUARMState *env)
756
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
759
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
761
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
764
/* Timer enabled: calculate and set current ISTATUS, irq, and
765
* reset timer to when ISTATUS next has to change
767
uint64_t count = gt_get_countervalue(&cpu->env);
768
/* Note that this must be unsigned 64 bit arithmetic: */
769
int istatus = count >= gt->cval;
772
gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
773
qemu_set_irq(cpu->gt_timer_outputs[timeridx],
774
(istatus && !(gt->ctl & 2)));
776
/* Next transition is when count rolls back over to zero */
777
nexttick = UINT64_MAX;
779
/* Next transition is when we hit cval */
782
/* Note that the desired next expiry time might be beyond the
783
* signed-64-bit range of a QEMUTimer -- in this case we just
784
* set the timer for as far in the future as possible. When the
785
* timer expires we will reset the timer for any remaining period.
787
if (nexttick > INT64_MAX / GTIMER_SCALE) {
788
nexttick = INT64_MAX / GTIMER_SCALE;
790
timer_mod(cpu->gt_timer[timeridx], nexttick);
792
/* Timer disabled: ISTATUS and timer output always clear */
794
qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
795
timer_del(cpu->gt_timer[timeridx]);
799
static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
802
/* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
803
if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
806
*value = env->cp15.c14_cntfrq;
810
static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
812
ARMCPU *cpu = arm_env_get_cpu(env);
813
int timeridx = ri->opc1 & 1;
815
timer_del(cpu->gt_timer[timeridx]);
818
static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
821
int timeridx = ri->opc1 & 1;
823
if (arm_current_pl(env) == 0 &&
824
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
827
*value = gt_get_countervalue(env);
831
static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
834
int timeridx = ri->opc1 & 1;
836
if (arm_current_pl(env) == 0 &&
837
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
840
*value = env->cp15.c14_timer[timeridx].cval;
844
static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
847
int timeridx = ri->opc1 & 1;
849
env->cp15.c14_timer[timeridx].cval = value;
850
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
853
static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
856
int timeridx = ri->crm & 1;
858
if (arm_current_pl(env) == 0 &&
859
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
862
*value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
863
gt_get_countervalue(env));
867
static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
870
int timeridx = ri->crm & 1;
872
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
873
+ sextract64(value, 0, 32);
874
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
878
static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
881
int timeridx = ri->crm & 1;
883
if (arm_current_pl(env) == 0 &&
884
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
887
*value = env->cp15.c14_timer[timeridx].ctl;
891
static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
894
ARMCPU *cpu = arm_env_get_cpu(env);
895
int timeridx = ri->crm & 1;
896
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
898
env->cp15.c14_timer[timeridx].ctl = value & 3;
899
if ((oldval ^ value) & 1) {
901
gt_recalc_timer(cpu, timeridx);
902
} else if ((oldval & value) & 2) {
903
/* IMASK toggled: don't need to recalculate,
904
* just set the interrupt line based on ISTATUS
906
qemu_set_irq(cpu->gt_timer_outputs[timeridx],
907
(oldval & 4) && (value & 2));
912
void arm_gt_ptimer_cb(void *opaque)
914
ARMCPU *cpu = opaque;
916
gt_recalc_timer(cpu, GTIMER_PHYS);
919
void arm_gt_vtimer_cb(void *opaque)
921
ARMCPU *cpu = opaque;
923
gt_recalc_timer(cpu, GTIMER_VIRT);
926
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
927
/* Note that CNTFRQ is purely reads-as-written for the benefit
928
* of software; writing it doesn't actually change the timer frequency.
929
* Our reset value matches the fixed frequency we implement the timer at.
931
{ .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
932
.access = PL1_RW | PL0_R,
933
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
934
.resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
935
.readfn = gt_cntfrq_read, .raw_readfn = raw_read,
937
/* overall control: mostly access permissions */
938
{ .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
940
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
943
/* per-timer control */
944
{ .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
945
.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
946
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
948
.readfn = gt_ctl_read, .writefn = gt_ctl_write,
949
.raw_readfn = raw_read, .raw_writefn = raw_write,
951
{ .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
952
.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
953
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
955
.readfn = gt_ctl_read, .writefn = gt_ctl_write,
956
.raw_readfn = raw_read, .raw_writefn = raw_write,
958
/* TimerValue views: a 32 bit downcounting view of the underlying state */
959
{ .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
960
.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
961
.readfn = gt_tval_read, .writefn = gt_tval_write,
963
{ .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
964
.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
965
.readfn = gt_tval_read, .writefn = gt_tval_write,
967
/* The counter itself */
968
{ .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
969
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
970
.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
972
{ .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
973
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
974
.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
976
/* Comparison value, indicating when the timer goes off */
977
{ .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
978
.access = PL1_RW | PL0_R,
979
.type = ARM_CP_64BIT | ARM_CP_IO,
980
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
982
.readfn = gt_cval_read, .writefn = gt_cval_write,
983
.raw_readfn = raw_read, .raw_writefn = raw_write,
985
{ .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
986
.access = PL1_RW | PL0_R,
987
.type = ARM_CP_64BIT | ARM_CP_IO,
988
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
990
.readfn = gt_cval_read, .writefn = gt_cval_write,
991
.raw_readfn = raw_read, .raw_writefn = raw_write,
997
/* In user-mode none of the generic timer registers are accessible,
998
* and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
999
* so instead just don't register any of them.
1001
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1007
static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1009
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1010
env->cp15.c7_par = value;
1011
} else if (arm_feature(env, ARM_FEATURE_V7)) {
1012
env->cp15.c7_par = value & 0xfffff6ff;
1014
env->cp15.c7_par = value & 0xfffff1ff;
1019
#ifndef CONFIG_USER_ONLY
1020
/* get_phys_addr() isn't present for user-mode-only targets */
1022
/* Return true if extended addresses are enabled, ie this is an
1023
* LPAE implementation and we are using the long-descriptor translation
1024
* table format because the TTBCR EAE bit is set.
1026
static inline bool extended_addresses_enabled(CPUARMState *env)
1028
return arm_feature(env, ARM_FEATURE_LPAE)
1029
&& (env->cp15.c2_control & (1U << 31));
1032
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1035
target_ulong page_size;
1037
int ret, is_user = ri->opc2 & 2;
1038
int access_type = ri->opc2 & 1;
1041
/* Other states are only available with TrustZone */
1044
ret = get_phys_addr(env, value, access_type, is_user,
1045
&phys_addr, &prot, &page_size);
1046
if (extended_addresses_enabled(env)) {
1047
/* ret is a DFSR/IFSR value for the long descriptor
1048
* translation table format, but with WnR always clear.
1049
* Convert it to a 64-bit PAR.
1051
uint64_t par64 = (1 << 11); /* LPAE bit always set */
1053
par64 |= phys_addr & ~0xfffULL;
1054
/* We don't set the ATTR or SH fields in the PAR. */
1057
par64 |= (ret & 0x3f) << 1; /* FS */
1058
/* Note that S2WLK and FSTAGE are always zero, because we don't
1059
* implement virtualization and therefore there can't be a stage 2
1063
env->cp15.c7_par = par64;
1064
env->cp15.c7_par_hi = par64 >> 32;
1066
/* ret is a DFSR/IFSR value for the short descriptor
1067
* translation table format (with WnR always clear).
1068
* Convert it to a 32-bit PAR.
1071
/* We do not set any attribute bits in the PAR */
1072
if (page_size == (1 << 24)
1073
&& arm_feature(env, ARM_FEATURE_V7)) {
1074
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1076
env->cp15.c7_par = phys_addr & 0xfffff000;
1079
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1080
((ret & (12 << 1)) >> 6) |
1081
((ret & 0xf) << 1) | 1;
1083
env->cp15.c7_par_hi = 0;
1089
static const ARMCPRegInfo vapa_cp_reginfo[] = {
1090
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1091
.access = PL1_RW, .resetvalue = 0,
1092
.fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1093
.writefn = par_write },
1094
#ifndef CONFIG_USER_ONLY
1095
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1096
.access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1101
/* Return basic MPU access permission bits. */
1102
static uint32_t simple_mpu_ap_bits(uint32_t val)
1109
for (i = 0; i < 16; i += 2) {
1110
ret |= (val >> i) & mask;
1116
/* Pad basic MPU access permission bits to extended format. */
1117
static uint32_t extended_mpu_ap_bits(uint32_t val)
1124
for (i = 0; i < 16; i += 2) {
1125
ret |= (val & mask) << i;
1131
static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1134
env->cp15.c5_data = extended_mpu_ap_bits(value);
1138
static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1141
*value = simple_mpu_ap_bits(env->cp15.c5_data);
1145
static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1148
env->cp15.c5_insn = extended_mpu_ap_bits(value);
1152
static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1155
*value = simple_mpu_ap_bits(env->cp15.c5_insn);
1159
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1165
*value = env->cp15.c6_region[ri->crm];
1169
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1175
env->cp15.c6_region[ri->crm] = value;
1179
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1180
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1181
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1182
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1183
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1184
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1185
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1186
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1187
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1188
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1190
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1191
{ .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1193
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1194
{ .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1196
.fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1197
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1199
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1200
/* Protection region base and size registers */
1201
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1202
.opc2 = CP_ANY, .access = PL1_RW,
1203
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
1207
static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1210
int maskshift = extract32(value, 0, 3);
1212
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1213
value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1217
/* Note that we always calculate c2_mask and c2_base_mask, but
1218
* they are only used for short-descriptor tables (ie if EAE is 0);
1219
* for long-descriptor tables the TTBCR fields are used differently
1220
* and the c2_mask and c2_base_mask values are meaningless.
1222
env->cp15.c2_control = value;
1223
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1224
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1228
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1231
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1232
/* With LPAE the TTBCR could result in a change of ASID
1233
* via the TTBCR.A1 bit, so do a TLB flush.
1237
return vmsa_ttbcr_raw_write(env, ri, value);
1240
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1242
env->cp15.c2_base_mask = 0xffffc000u;
1243
env->cp15.c2_control = 0;
1244
env->cp15.c2_mask = 0;
1247
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1248
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1250
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1251
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1253
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1254
{ .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1256
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1257
{ .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1259
.fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
1260
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1261
.access = PL1_RW, .writefn = vmsa_ttbcr_write,
1262
.resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
1263
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1264
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1265
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1270
static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1273
env->cp15.c15_ticonfig = value & 0xe7;
1274
/* The OS_TYPE bit in this register changes the reported CPUID! */
1275
env->cp15.c0_cpuid = (value & (1 << 5)) ?
1276
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1280
static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1283
env->cp15.c15_threadid = value & 0xffff;
1287
static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1290
/* Wait-for-interrupt (deprecated) */
1291
cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1295
static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1298
/* On OMAP there are registers indicating the max/min index of dcache lines
1299
* containing a dirty line; cache flush operations have to reset these.
1301
env->cp15.c15_i_max = 0x000;
1302
env->cp15.c15_i_min = 0xff0;
1306
static const ARMCPRegInfo omap_cp_reginfo[] = {
1307
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1308
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1309
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1310
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1311
.access = PL1_RW, .type = ARM_CP_NOP },
1312
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1314
.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1315
.writefn = omap_ticonfig_write },
1316
{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1318
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1319
{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1320
.access = PL1_RW, .resetvalue = 0xff0,
1321
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1322
{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1324
.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1325
.writefn = omap_threadid_write },
1326
{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1327
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1328
.type = ARM_CP_NO_MIGRATE,
1329
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1330
/* TODO: Peripheral port remap register:
1331
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1332
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1335
{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1336
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1337
.type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1338
.writefn = omap_cachemaint_write },
1339
{ .name = "C9", .cp = 15, .crn = 9,
1340
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1341
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1345
static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1349
if (env->cp15.c15_cpar != value) {
1350
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
1352
env->cp15.c15_cpar = value;
1357
static const ARMCPRegInfo xscale_cp_reginfo[] = {
1358
{ .name = "XSCALE_CPAR",
1359
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1360
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1361
.writefn = xscale_cpar_write, },
1362
{ .name = "XSCALE_AUXCR",
1363
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1364
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1369
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1370
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
1371
* implementation of this implementation-defined space.
1372
* Ideally this should eventually disappear in favour of actually
1373
* implementing the correct behaviour for all cores.
1375
{ .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1376
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1377
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1382
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1383
/* Cache status: RAZ because we have no cache so it's always clean */
1384
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1385
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1390
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1391
/* We never have a a block transfer operation in progress */
1392
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1393
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1395
/* The cache ops themselves: these all NOP for QEMU */
1396
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1397
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1398
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1399
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1400
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1401
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1402
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1403
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1404
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1405
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1406
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1407
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1411
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1412
/* The cache test-and-clean instructions always return (1 << 30)
1413
* to indicate that there are no dirty cache lines.
1415
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1416
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1417
.resetvalue = (1 << 30) },
1418
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1419
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1420
.resetvalue = (1 << 30) },
1424
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1425
/* Ignore ReadBuffer accesses */
1426
{ .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1427
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1428
.access = PL1_RW, .resetvalue = 0,
1429
.type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1433
static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1436
CPUState *cs = CPU(arm_env_get_cpu(env));
1437
uint32_t mpidr = cs->cpu_index;
1438
/* We don't support setting cluster ID ([8..11])
1439
* so these bits always RAZ.
1441
if (arm_feature(env, ARM_FEATURE_V7MP)) {
1442
mpidr |= (1U << 31);
1443
/* Cores which are uniprocessor (non-coherent)
1444
* but still implement the MP extensions set
1445
* bit 30. (For instance, A9UP.) However we do
1446
* not currently model any of those cores.
1453
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1454
{ .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1455
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1459
static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1461
*value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1465
static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1467
env->cp15.c7_par_hi = value >> 32;
1468
env->cp15.c7_par = value;
1472
static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1474
env->cp15.c7_par_hi = 0;
1475
env->cp15.c7_par = 0;
1478
static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1481
*value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1485
static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1488
env->cp15.c2_base0_hi = value >> 32;
1489
env->cp15.c2_base0 = value;
1493
static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1496
/* Writes to the 64 bit format TTBRs may change the ASID */
1498
return ttbr064_raw_write(env, ri, value);
1501
static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1503
env->cp15.c2_base0_hi = 0;
1504
env->cp15.c2_base0 = 0;
1507
static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1510
*value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1514
static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1517
env->cp15.c2_base1_hi = value >> 32;
1518
env->cp15.c2_base1 = value;
1522
static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1524
env->cp15.c2_base1_hi = 0;
1525
env->cp15.c2_base1 = 0;
1528
static const ARMCPRegInfo lpae_cp_reginfo[] = {
1529
/* NOP AMAIR0/1: the override is because these clash with the rather
1530
* broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1532
{ .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1533
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1535
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1536
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1538
/* 64 bit access versions of the (dummy) debug registers */
1539
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1540
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1541
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1542
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1543
{ .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1544
.access = PL1_RW, .type = ARM_CP_64BIT,
1545
.readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1546
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1547
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1548
.writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1549
.resetfn = ttbr064_reset },
1550
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1551
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1552
.writefn = ttbr164_write, .resetfn = ttbr164_reset },
1556
static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1558
CPREG_FIELD32(env, ri) = value & ~0x1f;
1562
static const ARMCPRegInfo trustzone_cp_reginfo[] = {
1563
/* Dummy implementations of registers; we don't enforce the
1564
* 'secure mode only' access checks. TODO: revisit as part of
1565
* proper fake-trustzone support.
1567
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
1568
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
1570
{ .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
1571
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sedbg),
1573
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
1574
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_nseac),
1576
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1577
.access = PL1_RW, .writefn = vbar_write,
1578
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
1580
{ .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
1581
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar),
1582
.writefn = vbar_write, .resetvalue = 0 },
1586
static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1589
*value = vfp_get_fpcr(env);
1593
static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1596
vfp_set_fpcr(env, value);
1600
static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1603
*value = vfp_get_fpsr(env);
1607
static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1610
vfp_set_fpsr(env, value);
1614
static const ARMCPRegInfo v8_cp_reginfo[] = {
1615
/* Minimal set of EL0-visible registers. This will need to be expanded
1616
* significantly for system emulation of AArch64 CPUs.
1618
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
1619
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1620
.access = PL0_RW, .type = ARM_CP_NZCV },
1621
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
1622
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1623
.access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1624
{ .name = "FPSR", .state = ARM_CP_STATE_AA64,
1625
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1626
.access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1627
/* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1628
* It will eventually need to have a CPU-specified reset value.
1630
{ .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1631
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1632
.access = PL0_R, .type = ARM_CP_CONST,
1633
.resetvalue = 0x80030003 },
1634
/* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1635
* For system mode the DZP bit here will need to be computed, not constant.
1637
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1638
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1639
.access = PL0_R, .type = ARM_CP_CONST,
1640
.resetvalue = 0x10 },
1644
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1646
env->cp15.c1_sys = value;
1647
/* ??? Lots of these bits are not implemented. */
1648
/* This may enable/disable the MMU, so do a TLB flush. */
1653
void register_cp_regs_for_features(ARMCPU *cpu)
1655
/* Register all the coprocessor registers based on feature bits */
1656
CPUARMState *env = &cpu->env;
1657
if (arm_feature(env, ARM_FEATURE_M)) {
1658
/* M profile has no coprocessor registers */
1662
define_arm_cp_regs(cpu, cp_reginfo);
1663
if (arm_feature(env, ARM_FEATURE_V6)) {
1664
/* The ID registers all have impdef reset values */
1665
ARMCPRegInfo v6_idregs[] = {
1666
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1667
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1668
.resetvalue = cpu->id_pfr0 },
1669
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1670
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1671
.resetvalue = cpu->id_pfr1 },
1672
{ .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1673
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1674
.resetvalue = cpu->id_dfr0 },
1675
{ .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1676
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1677
.resetvalue = cpu->id_afr0 },
1678
{ .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1679
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1680
.resetvalue = cpu->id_mmfr0 },
1681
{ .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1682
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1683
.resetvalue = cpu->id_mmfr1 },
1684
{ .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1685
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1686
.resetvalue = cpu->id_mmfr2 },
1687
{ .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1688
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1689
.resetvalue = cpu->id_mmfr3 },
1690
{ .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1691
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1692
.resetvalue = cpu->id_isar0 },
1693
{ .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1694
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1695
.resetvalue = cpu->id_isar1 },
1696
{ .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1697
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1698
.resetvalue = cpu->id_isar2 },
1699
{ .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1700
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1701
.resetvalue = cpu->id_isar3 },
1702
{ .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1703
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1704
.resetvalue = cpu->id_isar4 },
1705
{ .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1706
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1707
.resetvalue = cpu->id_isar5 },
1708
/* 6..7 are as yet unallocated and must RAZ */
1709
{ .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1710
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1712
{ .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1713
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1717
define_arm_cp_regs(cpu, v6_idregs);
1718
define_arm_cp_regs(cpu, v6_cp_reginfo);
1720
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1722
if (arm_feature(env, ARM_FEATURE_V6K)) {
1723
define_arm_cp_regs(cpu, v6k_cp_reginfo);
1725
if (arm_feature(env, ARM_FEATURE_V7)) {
1726
/* v7 performance monitor control register: same implementor
1727
* field as main ID register, and we implement no event counters.
1729
ARMCPRegInfo pmcr = {
1730
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1731
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1732
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1733
.readfn = pmreg_read, .writefn = pmcr_write,
1734
.raw_readfn = raw_read, .raw_writefn = raw_write,
1736
ARMCPRegInfo clidr = {
1737
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1738
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1740
define_one_arm_cp_reg(cpu, &pmcr);
1741
define_one_arm_cp_reg(cpu, &clidr);
1742
define_arm_cp_regs(cpu, v7_cp_reginfo);
1744
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1746
if (arm_feature(env, ARM_FEATURE_V8)) {
1747
define_arm_cp_regs(cpu, v8_cp_reginfo);
1749
if (arm_feature(env, ARM_FEATURE_MPU)) {
1750
/* These are the MPU registers prior to PMSAv6. Any new
1751
* PMSA core later than the ARM946 will require that we
1752
* implement the PMSAv6 or PMSAv7 registers, which are
1753
* completely different.
1755
assert(!arm_feature(env, ARM_FEATURE_V6));
1756
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1758
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1760
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1761
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1763
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1764
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1766
if (arm_feature(env, ARM_FEATURE_VAPA)) {
1767
define_arm_cp_regs(cpu, vapa_cp_reginfo);
1769
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1770
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1772
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1773
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1775
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1776
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1778
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1779
define_arm_cp_regs(cpu, omap_cp_reginfo);
1781
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1782
define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1784
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1785
define_arm_cp_regs(cpu, xscale_cp_reginfo);
1787
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1788
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1790
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1791
define_arm_cp_regs(cpu, lpae_cp_reginfo);
1793
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
1794
define_arm_cp_regs(cpu, trustzone_cp_reginfo);
1796
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
1797
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
1798
* be read-only (ie write causes UNDEF exception).
1801
ARMCPRegInfo id_cp_reginfo[] = {
1802
/* Note that the MIDR isn't a simple constant register because
1803
* of the TI925 behaviour where writes to another register can
1804
* cause the MIDR value to change.
1806
* Unimplemented registers in the c15 0 0 0 space default to
1807
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1808
* and friends override accordingly.
1811
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1812
.access = PL1_R, .resetvalue = cpu->midr,
1813
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1814
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1815
.type = ARM_CP_OVERRIDE },
1817
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1818
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1820
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1821
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1823
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1824
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1825
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1827
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1828
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1830
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1831
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1833
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1834
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1836
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1837
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1839
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1840
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1843
ARMCPRegInfo crn0_wi_reginfo = {
1844
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1845
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1846
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
1848
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1849
arm_feature(env, ARM_FEATURE_STRONGARM)) {
1851
/* Register the blanket "writes ignored" value first to cover the
1852
* whole space. Then update the specific ID registers to allow write
1853
* access, so that they ignore writes rather than causing them to
1856
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1857
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1861
define_arm_cp_regs(cpu, id_cp_reginfo);
1864
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1865
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1868
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1869
ARMCPRegInfo auxcr = {
1870
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1871
.access = PL1_RW, .type = ARM_CP_CONST,
1872
.resetvalue = cpu->reset_auxcr
1874
define_one_arm_cp_reg(cpu, &auxcr);
1877
/* Generic registers whose values depend on the implementation */
1879
ARMCPRegInfo sctlr = {
1880
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1881
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1882
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1883
.raw_writefn = raw_write,
1885
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1886
/* Normally we would always end the TB on an SCTLR write, but Linux
1887
* arch/arm/mach-pxa/sleep.S expects two instructions following
1888
* an MMU enable to execute from cache. Imitate this behaviour.
1890
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1892
define_one_arm_cp_reg(cpu, &sctlr);
1896
ARMCPU *cpu_arm_init(const char *cpu_model)
1901
oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1905
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1907
/* TODO this should be set centrally, once possible */
1908
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1913
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1915
CPUState *cs = CPU(cpu);
1916
CPUARMState *env = &cpu->env;
1918
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1919
gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1920
aarch64_fpu_gdb_set_reg,
1921
34, "aarch64-fpu.xml", 0);
1922
} else if (arm_feature(env, ARM_FEATURE_NEON)) {
1923
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1924
51, "arm-neon.xml", 0);
1925
} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1926
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1927
35, "arm-vfp3.xml", 0);
1928
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
1929
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1930
19, "arm-vfp.xml", 0);
1934
/* Sort alphabetically by type name, except for "any". */
1935
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1937
ObjectClass *class_a = (ObjectClass *)a;
1938
ObjectClass *class_b = (ObjectClass *)b;
1939
const char *name_a, *name_b;
1941
name_a = object_class_get_name(class_a);
1942
name_b = object_class_get_name(class_b);
1943
if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1945
} else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1948
return strcmp(name_a, name_b);
1952
static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1954
ObjectClass *oc = data;
1955
CPUListState *s = user_data;
1956
const char *typename;
1959
typename = object_class_get_name(oc);
1960
name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1961
(*s->cpu_fprintf)(s->file, " %s\n",
1966
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1970
.cpu_fprintf = cpu_fprintf,
1974
list = object_class_get_list(TYPE_ARM_CPU, false);
1975
list = g_slist_sort(list, arm_cpu_list_compare);
1976
(*cpu_fprintf)(f, "Available CPUs:\n");
1977
g_slist_foreach(list, arm_cpu_list_entry, &s);
1980
/* The 'host' CPU type is dynamically registered only if KVM is
1981
* enabled, so we have to special-case it here:
1983
(*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1987
static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1989
ObjectClass *oc = data;
1990
CpuDefinitionInfoList **cpu_list = user_data;
1991
CpuDefinitionInfoList *entry;
1992
CpuDefinitionInfo *info;
1993
const char *typename;
1995
typename = object_class_get_name(oc);
1996
info = g_malloc0(sizeof(*info));
1997
info->name = g_strndup(typename,
1998
strlen(typename) - strlen("-" TYPE_ARM_CPU));
2000
entry = g_malloc0(sizeof(*entry));
2001
entry->value = info;
2002
entry->next = *cpu_list;
2006
CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2008
CpuDefinitionInfoList *cpu_list = NULL;
2011
list = object_class_get_list(TYPE_ARM_CPU, false);
2012
g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2018
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2019
void *opaque, int state,
2020
int crm, int opc1, int opc2)
2022
/* Private utility function for define_one_arm_cp_reg_with_opaque():
2023
* add a single reginfo struct to the hash table.
2025
uint32_t *key = g_new(uint32_t, 1);
2026
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2027
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2028
if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2029
/* The AArch32 view of a shared register sees the lower 32 bits
2030
* of a 64 bit backing field. It is not migratable as the AArch64
2031
* view handles that. AArch64 also handles reset.
2032
* We assume it is a cp15 register.
2035
r2->type |= ARM_CP_NO_MIGRATE;
2036
r2->resetfn = arm_cp_reset_ignore;
2037
#ifdef HOST_WORDS_BIGENDIAN
2038
if (r2->fieldoffset) {
2039
r2->fieldoffset += sizeof(uint32_t);
2043
if (state == ARM_CP_STATE_AA64) {
2044
/* To allow abbreviation of ARMCPRegInfo
2045
* definitions, we treat cp == 0 as equivalent to
2046
* the value for "standard guest-visible sysreg".
2049
r2->cp = CP_REG_ARM64_SYSREG_CP;
2051
*key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2052
r2->opc0, opc1, opc2);
2054
*key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2057
r2->opaque = opaque;
2059
/* Make sure reginfo passed to helpers for wildcarded regs
2060
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2065
/* By convention, for wildcarded registers only the first
2066
* entry is used for migration; the others are marked as
2067
* NO_MIGRATE so we don't try to transfer the register
2068
* multiple times. Special registers (ie NOP/WFI) are
2071
if ((r->type & ARM_CP_SPECIAL) ||
2072
((r->crm == CP_ANY) && crm != 0) ||
2073
((r->opc1 == CP_ANY) && opc1 != 0) ||
2074
((r->opc2 == CP_ANY) && opc2 != 0)) {
2075
r2->type |= ARM_CP_NO_MIGRATE;
2078
/* Overriding of an existing definition must be explicitly
2081
if (!(r->type & ARM_CP_OVERRIDE)) {
2082
ARMCPRegInfo *oldreg;
2083
oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2084
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2085
fprintf(stderr, "Register redefined: cp=%d %d bit "
2086
"crn=%d crm=%d opc1=%d opc2=%d, "
2087
"was %s, now %s\n", r2->cp, 32 + 32 * is64,
2088
r2->crn, r2->crm, r2->opc1, r2->opc2,
2089
oldreg->name, r2->name);
2090
g_assert_not_reached();
2093
g_hash_table_insert(cpu->cp_regs, key, r2);
2097
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2098
const ARMCPRegInfo *r, void *opaque)
2100
/* Define implementations of coprocessor registers.
2101
* We store these in a hashtable because typically
2102
* there are less than 150 registers in a space which
2103
* is 16*16*16*8*8 = 262144 in size.
2104
* Wildcarding is supported for the crm, opc1 and opc2 fields.
2105
* If a register is defined twice then the second definition is
2106
* used, so this can be used to define some generic registers and
2107
* then override them with implementation specific variations.
2108
* At least one of the original and the second definition should
2109
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2110
* against accidental use.
2112
* The state field defines whether the register is to be
2113
* visible in the AArch32 or AArch64 execution state. If the
2114
* state is set to ARM_CP_STATE_BOTH then we synthesise a
2115
* reginfo structure for the AArch32 view, which sees the lower
2116
* 32 bits of the 64 bit register.
2118
* Only registers visible in AArch64 may set r->opc0; opc0 cannot
2119
* be wildcarded. AArch64 registers are always considered to be 64
2120
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2121
* the register, if any.
2123
int crm, opc1, opc2, state;
2124
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2125
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2126
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2127
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2128
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2129
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2130
/* 64 bit registers have only CRm and Opc1 fields */
2131
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2132
/* op0 only exists in the AArch64 encodings */
2133
assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2134
/* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2135
assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2136
/* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2137
* encodes a minimum access level for the register. We roll this
2138
* runtime check into our general permission check code, so check
2139
* here that the reginfo's specified permissions are strict enough
2140
* to encompass the generic architectural permission check.
2142
if (r->state != ARM_CP_STATE_AA32) {
2145
case 0: case 1: case 2:
2158
/* unallocated encoding, so not possible */
2166
/* min_EL EL1, secure mode only (we don't check the latter) */
2170
/* broken reginfo with out-of-range opc1 */
2174
/* assert our permissions are not too lax (stricter is fine) */
2175
assert((r->access & ~mask) == 0);
2178
/* Check that the register definition has enough info to handle
2179
* reads and writes if they are permitted.
2181
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2182
if (r->access & PL3_R) {
2183
assert(r->fieldoffset || r->readfn);
2185
if (r->access & PL3_W) {
2186
assert(r->fieldoffset || r->writefn);
2189
/* Bad type field probably means missing sentinel at end of reg list */
2190
assert(cptype_valid(r->type));
2191
for (crm = crmmin; crm <= crmmax; crm++) {
2192
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2193
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2194
for (state = ARM_CP_STATE_AA32;
2195
state <= ARM_CP_STATE_AA64; state++) {
2196
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2199
add_cpreg_to_hashtable(cpu, r, opaque, state,
2207
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2208
const ARMCPRegInfo *regs, void *opaque)
2210
/* Define a whole list of registers */
2211
const ARMCPRegInfo *r;
2212
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2213
define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2217
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2219
return g_hash_table_lookup(cpregs, &encoded_cp);
2222
int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2225
/* Helper coprocessor write function for write-ignore registers */
2229
int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2231
/* Helper coprocessor write function for read-as-zero registers */
2236
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2238
/* Helper coprocessor reset function for do-nothing-on-reset registers */
2241
static int bad_mode_switch(CPUARMState *env, int mode)
2243
/* Return true if it is not valid for us to switch to
2244
* this CPU mode (ie all the UNPREDICTABLE cases in
2245
* the ARM ARM CPSRWriteByInstr pseudocode).
2248
case ARM_CPU_MODE_USR:
2249
case ARM_CPU_MODE_SYS:
2250
case ARM_CPU_MODE_SVC:
2251
case ARM_CPU_MODE_ABT:
2252
case ARM_CPU_MODE_UND:
2253
case ARM_CPU_MODE_IRQ:
2254
case ARM_CPU_MODE_FIQ:
2261
uint32_t cpsr_read(CPUARMState *env)
2264
ZF = (env->ZF == 0);
2265
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2266
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2267
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2268
| ((env->condexec_bits & 0xfc) << 8)
2272
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2274
if (mask & CPSR_NZCV) {
2275
env->ZF = (~val) & CPSR_Z;
2277
env->CF = (val >> 29) & 1;
2278
env->VF = (val << 3) & 0x80000000;
2281
env->QF = ((val & CPSR_Q) != 0);
2283
env->thumb = ((val & CPSR_T) != 0);
2284
if (mask & CPSR_IT_0_1) {
2285
env->condexec_bits &= ~3;
2286
env->condexec_bits |= (val >> 25) & 3;
2288
if (mask & CPSR_IT_2_7) {
2289
env->condexec_bits &= 3;
2290
env->condexec_bits |= (val >> 8) & 0xfc;
2292
if (mask & CPSR_GE) {
2293
env->GE = (val >> 16) & 0xf;
2296
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2297
if (bad_mode_switch(env, val & CPSR_M)) {
2298
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2299
* We choose to ignore the attempt and leave the CPSR M field
2304
switch_mode(env, val & CPSR_M);
2307
mask &= ~CACHED_CPSR_BITS;
2308
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2311
/* Sign/zero extend */
2312
uint32_t HELPER(sxtb16)(uint32_t x)
2315
res = (uint16_t)(int8_t)x;
2316
res |= (uint32_t)(int8_t)(x >> 16) << 16;
2320
uint32_t HELPER(uxtb16)(uint32_t x)
2323
res = (uint16_t)(uint8_t)x;
2324
res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2328
uint32_t HELPER(clz)(uint32_t x)
2333
int32_t HELPER(sdiv)(int32_t num, int32_t den)
2337
if (num == INT_MIN && den == -1)
2342
uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2349
uint32_t HELPER(rbit)(uint32_t x)
2351
x = ((x & 0xff000000) >> 24)
2352
| ((x & 0x00ff0000) >> 8)
2353
| ((x & 0x0000ff00) << 8)
2354
| ((x & 0x000000ff) << 24);
2355
x = ((x & 0xf0f0f0f0) >> 4)
2356
| ((x & 0x0f0f0f0f) << 4);
2357
x = ((x & 0x88888888) >> 3)
2358
| ((x & 0x44444444) >> 1)
2359
| ((x & 0x22222222) << 1)
2360
| ((x & 0x11111111) << 3);
2364
#if defined(CONFIG_USER_ONLY)
2366
void arm_cpu_do_interrupt(CPUState *cs)
2368
ARMCPU *cpu = ARM_CPU(cs);
2369
CPUARMState *env = &cpu->env;
2371
env->exception_index = -1;
2374
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2378
env->exception_index = EXCP_PREFETCH_ABORT;
2379
env->cp15.c6_insn = address;
2381
env->exception_index = EXCP_DATA_ABORT;
2382
env->cp15.c6_data = address;
2387
/* These should probably raise undefined insn exceptions. */
2388
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2390
cpu_abort(env, "v7m_mrs %d\n", reg);
2393
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2395
cpu_abort(env, "v7m_mrs %d\n", reg);
2399
void switch_mode(CPUARMState *env, int mode)
2401
if (mode != ARM_CPU_MODE_USR)
2402
cpu_abort(env, "Tried to switch out of user mode\n");
2405
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2407
cpu_abort(env, "banked r13 write\n");
2410
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2412
cpu_abort(env, "banked r13 read\n");
2418
/* Map CPU modes onto saved register banks. */
2419
int bank_number(int mode)
2422
case ARM_CPU_MODE_USR:
2423
case ARM_CPU_MODE_SYS:
2425
case ARM_CPU_MODE_SVC:
2427
case ARM_CPU_MODE_ABT:
2429
case ARM_CPU_MODE_UND:
2431
case ARM_CPU_MODE_IRQ:
2433
case ARM_CPU_MODE_FIQ:
2435
case ARM_CPU_MODE_SMC:
2438
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2441
void switch_mode(CPUARMState *env, int mode)
2446
old_mode = env->uncached_cpsr & CPSR_M;
2447
if (mode == old_mode)
2450
if (old_mode == ARM_CPU_MODE_FIQ) {
2451
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2452
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2453
} else if (mode == ARM_CPU_MODE_FIQ) {
2454
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2455
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2458
i = bank_number(old_mode);
2459
env->banked_r13[i] = env->regs[13];
2460
env->banked_r14[i] = env->regs[14];
2461
env->banked_spsr[i] = env->spsr;
2463
i = bank_number(mode);
2464
env->regs[13] = env->banked_r13[i];
2465
env->regs[14] = env->banked_r14[i];
2466
env->spsr = env->banked_spsr[i];
2469
static void v7m_push(CPUARMState *env, uint32_t val)
2472
stl_phys(env->regs[13], val);
2475
static uint32_t v7m_pop(CPUARMState *env)
2478
val = ldl_phys(env->regs[13]);
2483
/* Switch to V7M main or process stack pointer. */
2484
static void switch_v7m_sp(CPUARMState *env, int process)
2487
if (env->v7m.current_sp != process) {
2488
tmp = env->v7m.other_sp;
2489
env->v7m.other_sp = env->regs[13];
2490
env->regs[13] = tmp;
2491
env->v7m.current_sp = process;
2495
static void do_v7m_exception_exit(CPUARMState *env)
2500
type = env->regs[15];
2501
if (env->v7m.exception != 0)
2502
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2504
/* Switch to the target stack. */
2505
switch_v7m_sp(env, (type & 4) != 0);
2506
/* Pop registers. */
2507
env->regs[0] = v7m_pop(env);
2508
env->regs[1] = v7m_pop(env);
2509
env->regs[2] = v7m_pop(env);
2510
env->regs[3] = v7m_pop(env);
2511
env->regs[12] = v7m_pop(env);
2512
env->regs[14] = v7m_pop(env);
2513
env->regs[15] = v7m_pop(env);
2514
xpsr = v7m_pop(env);
2515
xpsr_write(env, xpsr, 0xfffffdff);
2516
/* Undo stack alignment. */
2519
/* ??? The exception return type specifies Thread/Handler mode. However
2520
this is also implied by the xPSR value. Not sure what to do
2521
if there is a mismatch. */
2522
/* ??? Likewise for mismatches between the CONTROL register and the stack
2526
/* Exception names for debug logging; note that not all of these
2527
* precisely correspond to architectural exceptions.
2529
static const char * const excnames[] = {
2530
[EXCP_UDEF] = "Undefined Instruction",
2532
[EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2533
[EXCP_DATA_ABORT] = "Data Abort",
2536
[EXCP_BKPT] = "Breakpoint",
2537
[EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2538
[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2539
[EXCP_STREX] = "QEMU intercept of STREX",
2542
static inline void arm_log_exception(int idx)
2544
if (qemu_loglevel_mask(CPU_LOG_INT)) {
2545
const char *exc = NULL;
2547
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2548
exc = excnames[idx];
2553
qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2557
void arm_v7m_cpu_do_interrupt(CPUState *cs)
2559
ARMCPU *cpu = ARM_CPU(cs);
2560
CPUARMState *env = &cpu->env;
2561
uint32_t xpsr = xpsr_read(env);
2565
arm_log_exception(env->exception_index);
2568
if (env->v7m.current_sp)
2570
if (env->v7m.exception == 0)
2573
/* For exceptions we just mark as pending on the NVIC, and let that
2575
/* TODO: Need to escalate if the current priority is higher than the
2576
one we're raising. */
2577
switch (env->exception_index) {
2579
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2582
/* The PC already points to the next instruction. */
2583
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2585
case EXCP_PREFETCH_ABORT:
2586
case EXCP_DATA_ABORT:
2587
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2590
if (semihosting_enabled) {
2592
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2595
env->regs[0] = do_arm_semihosting(env);
2596
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2600
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2603
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2605
case EXCP_EXCEPTION_EXIT:
2606
do_v7m_exception_exit(env);
2609
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2610
return; /* Never happens. Keep compiler happy. */
2613
/* Align stack pointer. */
2614
/* ??? Should only do this if Configuration Control Register
2615
STACKALIGN bit is set. */
2616
if (env->regs[13] & 4) {
2620
/* Switch to the handler mode. */
2621
v7m_push(env, xpsr);
2622
v7m_push(env, env->regs[15]);
2623
v7m_push(env, env->regs[14]);
2624
v7m_push(env, env->regs[12]);
2625
v7m_push(env, env->regs[3]);
2626
v7m_push(env, env->regs[2]);
2627
v7m_push(env, env->regs[1]);
2628
v7m_push(env, env->regs[0]);
2629
switch_v7m_sp(env, 0);
2631
env->condexec_bits = 0;
2633
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2634
env->regs[15] = addr & 0xfffffffe;
2635
env->thumb = addr & 1;
2638
/* Handle a CPU exception. */
2639
void arm_cpu_do_interrupt(CPUState *cs)
2641
ARMCPU *cpu = ARM_CPU(cs);
2642
CPUARMState *env = &cpu->env;
2650
arm_log_exception(env->exception_index);
2652
/* TODO: Vectored interrupt controller. */
2653
switch (env->exception_index) {
2655
new_mode = ARM_CPU_MODE_UND;
2664
if (semihosting_enabled) {
2665
/* Check for semihosting interrupt. */
2667
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2670
mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2673
/* Only intercept calls from privileged modes, to provide some
2674
semblance of security. */
2675
if (((mask == 0x123456 && !env->thumb)
2676
|| (mask == 0xab && env->thumb))
2677
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2678
env->regs[0] = do_arm_semihosting(env);
2679
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2683
new_mode = ARM_CPU_MODE_SVC;
2686
/* The PC already points to the next instruction. */
2690
/* See if this is a semihosting syscall. */
2691
if (env->thumb && semihosting_enabled) {
2692
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2694
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2696
env->regs[0] = do_arm_semihosting(env);
2697
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2701
env->cp15.c5_insn = 2;
2702
/* Fall through to prefetch abort. */
2703
case EXCP_PREFETCH_ABORT:
2704
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2705
env->cp15.c5_insn, env->cp15.c6_insn);
2706
new_mode = ARM_CPU_MODE_ABT;
2708
mask = CPSR_A | CPSR_I;
2711
case EXCP_DATA_ABORT:
2712
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2713
env->cp15.c5_data, env->cp15.c6_data);
2714
new_mode = ARM_CPU_MODE_ABT;
2716
mask = CPSR_A | CPSR_I;
2720
new_mode = ARM_CPU_MODE_IRQ;
2722
/* Disable IRQ and imprecise data aborts. */
2723
mask = CPSR_A | CPSR_I;
2727
new_mode = ARM_CPU_MODE_FIQ;
2729
/* Disable FIQ, IRQ and imprecise data aborts. */
2730
mask = CPSR_A | CPSR_I | CPSR_F;
2734
if (semihosting_enabled) {
2735
cpu_abort(env, "SMC handling under semihosting not implemented\n");
2738
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2739
env->cp15.c1_scr &= ~1;
2741
offset = env->thumb ? 2 : 0;
2742
new_mode = ARM_CPU_MODE_SMC;
2744
mask = CPSR_A | CPSR_I | CPSR_F;
2747
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2748
return; /* Never happens. Keep compiler happy. */
2750
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
2751
if (new_mode == ARM_CPU_MODE_SMC ||
2752
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2753
addr += env->cp15.c12_mvbar;
2755
if (env->cp15.c1_sys & (1 << 13)) {
2758
addr += env->cp15.c12_vbar;
2763
if (env->cp15.c1_sys & (1 << 13)) {
2767
switch_mode (env, new_mode);
2768
env->spsr = cpsr_read(env);
2769
/* Clear IT bits. */
2770
env->condexec_bits = 0;
2771
/* Switch to the new mode, and to the correct instruction set. */
2772
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2773
env->uncached_cpsr |= mask;
2774
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2775
* and we should just guard the thumb mode on V4 */
2776
if (arm_feature(env, ARM_FEATURE_V4T)) {
2777
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2779
env->regs[14] = env->regs[15] + offset;
2780
env->regs[15] = addr;
2781
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2784
/* Check section/page access permissions.
2785
Returns the page protection flags, or zero if the access is not
2787
static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2788
int access_type, int is_user)
2792
if (domain_prot == 3) {
2793
return PAGE_READ | PAGE_WRITE;
2796
if (access_type == 1)
2799
prot_ro = PAGE_READ;
2803
if (access_type == 1)
2805
switch ((env->cp15.c1_sys >> 8) & 3) {
2807
return is_user ? 0 : PAGE_READ;
2814
return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2819
return PAGE_READ | PAGE_WRITE;
2821
return PAGE_READ | PAGE_WRITE;
2822
case 4: /* Reserved. */
2825
return is_user ? 0 : prot_ro;
2829
if (!arm_feature (env, ARM_FEATURE_V6K))
2837
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2841
if (address & env->cp15.c2_mask)
2842
table = env->cp15.c2_base1 & 0xffffc000;
2844
table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2846
table |= (address >> 18) & 0x3ffc;
2850
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2851
int is_user, hwaddr *phys_ptr,
2852
int *prot, target_ulong *page_size)
2863
/* Pagetable walk. */
2864
/* Lookup l1 descriptor. */
2865
table = get_level1_table_address(env, address);
2866
desc = ldl_phys(table);
2868
domain = (desc >> 5) & 0x0f;
2869
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2871
/* Section translation fault. */
2875
if (domain_prot == 0 || domain_prot == 2) {
2877
code = 9; /* Section domain fault. */
2879
code = 11; /* Page domain fault. */
2884
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2885
ap = (desc >> 10) & 3;
2887
*page_size = 1024 * 1024;
2889
/* Lookup l2 entry. */
2891
/* Coarse pagetable. */
2892
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2894
/* Fine pagetable. */
2895
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2897
desc = ldl_phys(table);
2899
case 0: /* Page translation fault. */
2902
case 1: /* 64k page. */
2903
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2904
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2905
*page_size = 0x10000;
2907
case 2: /* 4k page. */
2908
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2909
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2910
*page_size = 0x1000;
2912
case 3: /* 1k page. */
2914
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2915
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2917
/* Page translation fault. */
2922
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2924
ap = (desc >> 4) & 3;
2928
/* Never happens, but compiler isn't smart enough to tell. */
2933
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
2935
/* Access permission fault. */
2939
*phys_ptr = phys_addr;
2942
return code | (domain << 4);
2945
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2946
int is_user, hwaddr *phys_ptr,
2947
int *prot, target_ulong *page_size)
2960
/* Pagetable walk. */
2961
/* Lookup l1 descriptor. */
2962
table = get_level1_table_address(env, address);
2963
desc = ldl_phys(table);
2965
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2966
/* Section translation fault, or attempt to use the encoding
2967
* which is Reserved on implementations without PXN.
2972
if ((type == 1) || !(desc & (1 << 18))) {
2973
/* Page or Section. */
2974
domain = (desc >> 5) & 0x0f;
2976
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2977
if (domain_prot == 0 || domain_prot == 2) {
2979
code = 9; /* Section domain fault. */
2981
code = 11; /* Page domain fault. */
2986
if (desc & (1 << 18)) {
2988
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2989
*page_size = 0x1000000;
2992
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2993
*page_size = 0x100000;
2995
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2996
xn = desc & (1 << 4);
3000
if (arm_feature(env, ARM_FEATURE_PXN)) {
3001
pxn = (desc >> 2) & 1;
3003
/* Lookup l2 entry. */
3004
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3005
desc = ldl_phys(table);
3006
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3008
case 0: /* Page translation fault. */
3011
case 1: /* 64k page. */
3012
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3013
xn = desc & (1 << 15);
3014
*page_size = 0x10000;
3016
case 2: case 3: /* 4k page. */
3017
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3019
*page_size = 0x1000;
3022
/* Never happens, but compiler isn't smart enough to tell. */
3027
if (domain_prot == 3) {
3028
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3030
if (pxn && !is_user) {
3033
if (xn && access_type == 2)
3036
/* The simplified model uses AP[0] as an access control bit. */
3037
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
3038
/* Access flag fault. */
3039
code = (code == 15) ? 6 : 3;
3042
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
3044
/* Access permission fault. */
3051
*phys_ptr = phys_addr;
3054
return code | (domain << 4);
3057
/* Fault type for long-descriptor MMU fault reporting; this corresponds
3058
* to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3061
translation_fault = 1,
3063
permission_fault = 3,
3066
static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3067
int access_type, int is_user,
3068
hwaddr *phys_ptr, int *prot,
3069
target_ulong *page_size_ptr)
3071
/* Read an LPAE long-descriptor translation table. */
3072
MMUFaultType fault_type = translation_fault;
3080
uint32_t tableattrs;
3081
target_ulong page_size;
3084
/* Determine whether this address is in the region controlled by
3085
* TTBR0 or TTBR1 (or if it is in neither region and should fault).
3086
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
3087
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3089
uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3090
uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3091
if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3092
/* there is a ttbr0 region and we are in it (high bits all zero) */
3094
} else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3095
/* there is a ttbr1 region and we are in it (high bits all one) */
3098
/* ttbr0 region is "everything not in the ttbr1 region" */
3101
/* ttbr1 region is "everything not in the ttbr0 region" */
3104
/* in the gap between the two regions, this is a Translation fault */
3105
fault_type = translation_fault;
3109
/* Note that QEMU ignores shareability and cacheability attributes,
3110
* so we don't need to do anything with the SH, ORGN, IRGN fields
3111
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3112
* ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3113
* implement any ASID-like capability so we can ignore it (instead
3114
* we will always flush the TLB any time the ASID is changed).
3116
if (ttbr_select == 0) {
3117
ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
3118
epd = extract32(env->cp15.c2_control, 7, 1);
3121
ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
3122
epd = extract32(env->cp15.c2_control, 23, 1);
3127
/* Translation table walk disabled => Translation fault on TLB miss */
3131
/* If the region is small enough we will skip straight to a 2nd level
3132
* lookup. This affects the number of bits of the address used in
3133
* combination with the TTBR to find the first descriptor. ('n' here
3134
* matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3135
* from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3144
/* Clear the vaddr bits which aren't part of the within-region address,
3145
* so that we don't have to special case things when calculating the
3146
* first descriptor address.
3148
address &= (0xffffffffU >> tsz);
3150
/* Now we can extract the actual base address from the TTBR */
3151
descaddr = extract64(ttbr, 0, 40);
3152
descaddr &= ~((1ULL << n) - 1);
3156
uint64_t descriptor;
3158
descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3159
descriptor = ldq_phys(descaddr);
3160
if (!(descriptor & 1) ||
3161
(!(descriptor & 2) && (level == 3))) {
3162
/* Invalid, or the Reserved level 3 encoding */
3165
descaddr = descriptor & 0xfffffff000ULL;
3167
if ((descriptor & 2) && (level < 3)) {
3168
/* Table entry. The top five bits are attributes which may
3169
* propagate down through lower levels of the table (and
3170
* which are all arranged so that 0 means "no effect", so
3171
* we can gather them up by ORing in the bits at each level).
3173
tableattrs |= extract64(descriptor, 59, 5);
3177
/* Block entry at level 1 or 2, or page entry at level 3.
3178
* These are basically the same thing, although the number
3179
* of bits we pull in from the vaddr varies.
3181
page_size = (1 << (39 - (9 * level)));
3182
descaddr |= (address & (page_size - 1));
3183
/* Extract attributes from the descriptor and merge with table attrs */
3184
attrs = extract64(descriptor, 2, 10)
3185
| (extract64(descriptor, 52, 12) << 10);
3186
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3187
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3188
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3189
* means "force PL1 access only", which means forcing AP[1] to 0.
3191
if (extract32(tableattrs, 2, 1)) {
3194
/* Since we're always in the Non-secure state, NSTable is ignored. */
3197
/* Here descaddr is the final physical address, and attributes
3200
fault_type = access_fault;
3201
if ((attrs & (1 << 8)) == 0) {
3205
fault_type = permission_fault;
3206
if (is_user && !(attrs & (1 << 4))) {
3207
/* Unprivileged access not enabled */
3210
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3211
if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3213
if (access_type == 2) {
3216
*prot &= ~PAGE_EXEC;
3218
if (attrs & (1 << 5)) {
3219
/* Write access forbidden */
3220
if (access_type == 1) {
3223
*prot &= ~PAGE_WRITE;
3226
*phys_ptr = descaddr;
3227
*page_size_ptr = page_size;
3231
/* Long-descriptor format IFSR/DFSR value */
3232
return (1 << 9) | (fault_type << 2) | level;
3235
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3236
int access_type, int is_user,
3237
hwaddr *phys_ptr, int *prot)
3243
*phys_ptr = address;
3244
for (n = 7; n >= 0; n--) {
3245
base = env->cp15.c6_region[n];
3246
if ((base & 1) == 0)
3248
mask = 1 << ((base >> 1) & 0x1f);
3249
/* Keep this shift separate from the above to avoid an
3250
(undefined) << 32. */
3251
mask = (mask << 1) - 1;
3252
if (((base ^ address) & ~mask) == 0)
3258
if (access_type == 2) {
3259
mask = env->cp15.c5_insn;
3261
mask = env->cp15.c5_data;
3263
mask = (mask >> (n * 4)) & 0xf;
3270
*prot = PAGE_READ | PAGE_WRITE;
3275
*prot |= PAGE_WRITE;
3278
*prot = PAGE_READ | PAGE_WRITE;
3289
/* Bad permission. */
3296
/* get_phys_addr - get the physical address for this virtual address
3298
* Find the physical address corresponding to the given virtual address,
3299
* by doing a translation table walk on MMU based systems or using the
3300
* MPU state on MPU based systems.
3302
* Returns 0 if the translation was successful. Otherwise, phys_ptr,
3303
* prot and page_size are not filled in, and the return value provides
3304
* information on why the translation aborted, in the format of a
3305
* DFSR/IFSR fault register, with the following caveats:
3306
* * we honour the short vs long DFSR format differences.
3307
* * the WnR bit is never set (the caller must do this).
3308
* * for MPU based systems we don't bother to return a full FSR format
3312
* @address: virtual address to get physical address for
3313
* @access_type: 0 for read, 1 for write, 2 for execute
3314
* @is_user: 0 for privileged access, 1 for user
3315
* @phys_ptr: set to the physical address corresponding to the virtual address
3316
* @prot: set to the permissions for the page containing phys_ptr
3317
* @page_size: set to the size of the page containing phys_ptr
3319
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
3320
int access_type, int is_user,
3321
hwaddr *phys_ptr, int *prot,
3322
target_ulong *page_size)
3324
/* Fast Context Switch Extension. */
3325
if (address < 0x02000000)
3326
address += env->cp15.c13_fcse;
3328
if ((env->cp15.c1_sys & 1) == 0) {
3329
/* MMU/MPU disabled. */
3330
*phys_ptr = address;
3331
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3332
*page_size = TARGET_PAGE_SIZE;
3334
} else if (arm_feature(env, ARM_FEATURE_MPU)) {
3335
*page_size = TARGET_PAGE_SIZE;
3336
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3338
} else if (extended_addresses_enabled(env)) {
3339
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3341
} else if (env->cp15.c1_sys & (1 << 23)) {
3342
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3345
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3350
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
3351
int access_type, int mmu_idx)
3354
target_ulong page_size;
3358
is_user = mmu_idx == MMU_USER_IDX;
3359
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3362
/* Map a single [sub]page. */
3363
phys_addr &= ~(hwaddr)0x3ff;
3364
address &= ~(uint32_t)0x3ff;
3365
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
3369
if (access_type == 2) {
3370
env->cp15.c5_insn = ret;
3371
env->cp15.c6_insn = address;
3372
env->exception_index = EXCP_PREFETCH_ABORT;
3374
env->cp15.c5_data = ret;
3375
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3376
env->cp15.c5_data |= (1 << 11);
3377
env->cp15.c6_data = address;
3378
env->exception_index = EXCP_DATA_ABORT;
3383
hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3385
ARMCPU *cpu = ARM_CPU(cs);
3387
target_ulong page_size;
3391
ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3400
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3402
if ((env->uncached_cpsr & CPSR_M) == mode) {
3403
env->regs[13] = val;
3405
env->banked_r13[bank_number(mode)] = val;
3409
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3411
if ((env->uncached_cpsr & CPSR_M) == mode) {
3412
return env->regs[13];
3414
return env->banked_r13[bank_number(mode)];
3418
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3422
return xpsr_read(env) & 0xf8000000;
3424
return xpsr_read(env) & 0xf80001ff;
3426
return xpsr_read(env) & 0xff00fc00;
3428
return xpsr_read(env) & 0xff00fdff;
3430
return xpsr_read(env) & 0x000001ff;
3432
return xpsr_read(env) & 0x0700fc00;
3434
return xpsr_read(env) & 0x0700edff;
3436
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3438
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3439
case 16: /* PRIMASK */
3440
return (env->uncached_cpsr & CPSR_I) != 0;
3441
case 17: /* BASEPRI */
3442
case 18: /* BASEPRI_MAX */
3443
return env->v7m.basepri;
3444
case 19: /* FAULTMASK */
3445
return (env->uncached_cpsr & CPSR_F) != 0;
3446
case 20: /* CONTROL */
3447
return env->v7m.control;
3449
/* ??? For debugging only. */
3450
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3455
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3459
xpsr_write(env, val, 0xf8000000);
3462
xpsr_write(env, val, 0xf8000000);
3465
xpsr_write(env, val, 0xfe00fc00);
3468
xpsr_write(env, val, 0xfe00fc00);
3471
/* IPSR bits are readonly. */
3474
xpsr_write(env, val, 0x0600fc00);
3477
xpsr_write(env, val, 0x0600fc00);
3480
if (env->v7m.current_sp)
3481
env->v7m.other_sp = val;
3483
env->regs[13] = val;
3486
if (env->v7m.current_sp)
3487
env->regs[13] = val;
3489
env->v7m.other_sp = val;
3491
case 16: /* PRIMASK */
3493
env->uncached_cpsr |= CPSR_I;
3495
env->uncached_cpsr &= ~CPSR_I;
3497
case 17: /* BASEPRI */
3498
env->v7m.basepri = val & 0xff;
3500
case 18: /* BASEPRI_MAX */
3502
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3503
env->v7m.basepri = val;
3505
case 19: /* FAULTMASK */
3507
env->uncached_cpsr |= CPSR_F;
3509
env->uncached_cpsr &= ~CPSR_F;
3511
case 20: /* CONTROL */
3512
env->v7m.control = val & 3;
3513
switch_v7m_sp(env, (val & 2) != 0);
3516
/* ??? For debugging only. */
3517
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3524
/* Note that signed overflow is undefined in C. The following routines are
3525
careful to use unsigned types where modulo arithmetic is required.
3526
Failure to do so _will_ break on newer gcc. */
3528
/* Signed saturating arithmetic. */
3530
/* Perform 16-bit signed saturating addition. */
3531
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3536
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3545
/* Perform 8-bit signed saturating addition. */
3546
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3551
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3560
/* Perform 16-bit signed saturating subtraction. */
3561
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3566
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3575
/* Perform 8-bit signed saturating subtraction. */
3576
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3581
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3590
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3591
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3592
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3593
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3596
#include "op_addsub.h"
3598
/* Unsigned saturating arithmetic. */
3599
static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3608
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3616
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3625
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3633
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3634
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3635
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3636
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3639
#include "op_addsub.h"
3641
/* Signed modulo arithmetic. */
3642
#define SARITH16(a, b, n, op) do { \
3644
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3645
RESULT(sum, n, 16); \
3647
ge |= 3 << (n * 2); \
3650
#define SARITH8(a, b, n, op) do { \
3652
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3653
RESULT(sum, n, 8); \
3659
#define ADD16(a, b, n) SARITH16(a, b, n, +)
3660
#define SUB16(a, b, n) SARITH16(a, b, n, -)
3661
#define ADD8(a, b, n) SARITH8(a, b, n, +)
3662
#define SUB8(a, b, n) SARITH8(a, b, n, -)
3666
#include "op_addsub.h"
3668
/* Unsigned modulo arithmetic. */
3669
#define ADD16(a, b, n) do { \
3671
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3672
RESULT(sum, n, 16); \
3673
if ((sum >> 16) == 1) \
3674
ge |= 3 << (n * 2); \
3677
#define ADD8(a, b, n) do { \
3679
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3680
RESULT(sum, n, 8); \
3681
if ((sum >> 8) == 1) \
3685
#define SUB16(a, b, n) do { \
3687
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3688
RESULT(sum, n, 16); \
3689
if ((sum >> 16) == 0) \
3690
ge |= 3 << (n * 2); \
3693
#define SUB8(a, b, n) do { \
3695
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3696
RESULT(sum, n, 8); \
3697
if ((sum >> 8) == 0) \
3704
#include "op_addsub.h"
3706
/* Halved signed arithmetic. */
3707
#define ADD16(a, b, n) \
3708
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3709
#define SUB16(a, b, n) \
3710
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3711
#define ADD8(a, b, n) \
3712
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3713
#define SUB8(a, b, n) \
3714
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3717
#include "op_addsub.h"
3719
/* Halved unsigned arithmetic. */
3720
#define ADD16(a, b, n) \
3721
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3722
#define SUB16(a, b, n) \
3723
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3724
#define ADD8(a, b, n) \
3725
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3726
#define SUB8(a, b, n) \
3727
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3730
#include "op_addsub.h"
3732
static inline uint8_t do_usad(uint8_t a, uint8_t b)
3740
/* Unsigned sum of absolute byte differences. */
3741
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3744
sum = do_usad(a, b);
3745
sum += do_usad(a >> 8, b >> 8);
3746
sum += do_usad(a >> 16, b >>16);
3747
sum += do_usad(a >> 24, b >> 24);
3751
/* For ARMv6 SEL instruction. */
3752
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3765
return (a & mask) | (b & ~mask);
3768
/* VFP support. We follow the convention used for VFP instructions:
3769
Single precision routines have a "s" suffix, double precision a
3772
/* Convert host exception flags to vfp form. */
3773
static inline int vfp_exceptbits_from_host(int host_bits)
3775
int target_bits = 0;
3777
if (host_bits & float_flag_invalid)
3779
if (host_bits & float_flag_divbyzero)
3781
if (host_bits & float_flag_overflow)
3783
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3785
if (host_bits & float_flag_inexact)
3786
target_bits |= 0x10;
3787
if (host_bits & float_flag_input_denormal)
3788
target_bits |= 0x80;
3792
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
3797
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3798
| (env->vfp.vec_len << 16)
3799
| (env->vfp.vec_stride << 20);
3800
i = get_float_exception_flags(&env->vfp.fp_status);
3801
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
3802
fpscr |= vfp_exceptbits_from_host(i);
3806
uint32_t vfp_get_fpscr(CPUARMState *env)
3808
return HELPER(vfp_get_fpscr)(env);
3811
/* Convert vfp exception flags to target form. */
3812
static inline int vfp_exceptbits_to_host(int target_bits)
3816
if (target_bits & 1)
3817
host_bits |= float_flag_invalid;
3818
if (target_bits & 2)
3819
host_bits |= float_flag_divbyzero;
3820
if (target_bits & 4)
3821
host_bits |= float_flag_overflow;
3822
if (target_bits & 8)
3823
host_bits |= float_flag_underflow;
3824
if (target_bits & 0x10)
3825
host_bits |= float_flag_inexact;
3826
if (target_bits & 0x80)
3827
host_bits |= float_flag_input_denormal;
3831
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
3836
changed = env->vfp.xregs[ARM_VFP_FPSCR];
3837
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3838
env->vfp.vec_len = (val >> 16) & 7;
3839
env->vfp.vec_stride = (val >> 20) & 3;
3842
if (changed & (3 << 22)) {
3843
i = (val >> 22) & 3;
3846
i = float_round_nearest_even;
3852
i = float_round_down;
3855
i = float_round_to_zero;
3858
set_float_rounding_mode(i, &env->vfp.fp_status);
3860
if (changed & (1 << 24)) {
3861
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3862
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3864
if (changed & (1 << 25))
3865
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
3867
i = vfp_exceptbits_to_host(val);
3868
set_float_exception_flags(i, &env->vfp.fp_status);
3869
set_float_exception_flags(0, &env->vfp.standard_fp_status);
3872
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3874
HELPER(vfp_set_fpscr)(env, val);
3877
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3879
#define VFP_BINOP(name) \
3880
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3882
float_status *fpst = fpstp; \
3883
return float32_ ## name(a, b, fpst); \
3885
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3887
float_status *fpst = fpstp; \
3888
return float64_ ## name(a, b, fpst); \
3896
float32 VFP_HELPER(neg, s)(float32 a)
3898
return float32_chs(a);
3901
float64 VFP_HELPER(neg, d)(float64 a)
3903
return float64_chs(a);
3906
float32 VFP_HELPER(abs, s)(float32 a)
3908
return float32_abs(a);
3911
float64 VFP_HELPER(abs, d)(float64 a)
3913
return float64_abs(a);
3916
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3918
return float32_sqrt(a, &env->vfp.fp_status);
3921
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3923
return float64_sqrt(a, &env->vfp.fp_status);
3926
/* XXX: check quiet/signaling case */
3927
#define DO_VFP_cmp(p, type) \
3928
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3931
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3932
case 0: flags = 0x6; break; \
3933
case -1: flags = 0x8; break; \
3934
case 1: flags = 0x2; break; \
3935
default: case 2: flags = 0x3; break; \
3937
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3938
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3940
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3943
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3944
case 0: flags = 0x6; break; \
3945
case -1: flags = 0x8; break; \
3946
case 1: flags = 0x2; break; \
3947
default: case 2: flags = 0x3; break; \
3949
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3950
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3952
DO_VFP_cmp(s, float32)
3953
DO_VFP_cmp(d, float64)
3956
/* Integer to float and float to integer conversions */
3958
#define CONV_ITOF(name, fsz, sign) \
3959
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3961
float_status *fpst = fpstp; \
3962
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3965
#define CONV_FTOI(name, fsz, sign, round) \
3966
uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3968
float_status *fpst = fpstp; \
3969
if (float##fsz##_is_any_nan(x)) { \
3970
float_raise(float_flag_invalid, fpst); \
3973
return float##fsz##_to_##sign##int32##round(x, fpst); \
3976
#define FLOAT_CONVS(name, p, fsz, sign) \
3977
CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3978
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3979
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3981
FLOAT_CONVS(si, s, 32, )
3982
FLOAT_CONVS(si, d, 64, )
3983
FLOAT_CONVS(ui, s, 32, u)
3984
FLOAT_CONVS(ui, d, 64, u)
3990
/* floating point conversion */
3991
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3993
float64 r = float32_to_float64(x, &env->vfp.fp_status);
3994
/* ARM requires that S<->D conversion of any kind of NaN generates
3995
* a quiet NaN by forcing the most significant frac bit to 1.
3997
return float64_maybe_silence_nan(r);
4000
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4002
float32 r = float64_to_float32(x, &env->vfp.fp_status);
4003
/* ARM requires that S<->D conversion of any kind of NaN generates
4004
* a quiet NaN by forcing the most significant frac bit to 1.
4006
return float32_maybe_silence_nan(r);
4009
/* VFP3 fixed point conversion. */
4010
#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
4011
float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
4014
float_status *fpst = fpstp; \
4016
tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
4017
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4019
uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
4022
float_status *fpst = fpstp; \
4024
if (float##fsz##_is_any_nan(x)) { \
4025
float_raise(float_flag_invalid, fpst); \
4028
tmp = float##fsz##_scalbn(x, shift, fpst); \
4029
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
4032
VFP_CONV_FIX(sh, d, 64, int16, )
4033
VFP_CONV_FIX(sl, d, 64, int32, )
4034
VFP_CONV_FIX(uh, d, 64, uint16, u)
4035
VFP_CONV_FIX(ul, d, 64, uint32, u)
4036
VFP_CONV_FIX(sh, s, 32, int16, )
4037
VFP_CONV_FIX(sl, s, 32, int32, )
4038
VFP_CONV_FIX(uh, s, 32, uint16, u)
4039
VFP_CONV_FIX(ul, s, 32, uint32, u)
4042
/* Half precision conversions. */
4043
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4045
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4046
float32 r = float16_to_float32(make_float16(a), ieee, s);
4048
return float32_maybe_silence_nan(r);
4053
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4055
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4056
float16 r = float32_to_float16(a, ieee, s);
4058
r = float16_maybe_silence_nan(r);
4060
return float16_val(r);
4063
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4065
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4068
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4070
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4073
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4075
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4078
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4080
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4083
#define float32_two make_float32(0x40000000)
4084
#define float32_three make_float32(0x40400000)
4085
#define float32_one_point_five make_float32(0x3fc00000)
4087
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4089
float_status *s = &env->vfp.standard_fp_status;
4090
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4091
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4092
if (!(float32_is_zero(a) || float32_is_zero(b))) {
4093
float_raise(float_flag_input_denormal, s);
4097
return float32_sub(float32_two, float32_mul(a, b, s), s);
4100
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4102
float_status *s = &env->vfp.standard_fp_status;
4104
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4105
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4106
if (!(float32_is_zero(a) || float32_is_zero(b))) {
4107
float_raise(float_flag_input_denormal, s);
4109
return float32_one_point_five;
4111
product = float32_mul(a, b, s);
4112
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4117
/* Constants 256 and 512 are used in some helpers; we avoid relying on
4118
* int->float conversions at run-time. */
4119
#define float64_256 make_float64(0x4070000000000000LL)
4120
#define float64_512 make_float64(0x4080000000000000LL)
4122
/* The algorithm that must be used to calculate the estimate
4123
* is specified by the ARM ARM.
4125
static float64 recip_estimate(float64 a, CPUARMState *env)
4127
/* These calculations mustn't set any fp exception flags,
4128
* so we use a local copy of the fp_status.
4130
float_status dummy_status = env->vfp.standard_fp_status;
4131
float_status *s = &dummy_status;
4132
/* q = (int)(a * 512.0) */
4133
float64 q = float64_mul(float64_512, a, s);
4134
int64_t q_int = float64_to_int64_round_to_zero(q, s);
4136
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
4137
q = int64_to_float64(q_int, s);
4138
q = float64_add(q, float64_half, s);
4139
q = float64_div(q, float64_512, s);
4140
q = float64_div(float64_one, q, s);
4142
/* s = (int)(256.0 * r + 0.5) */
4143
q = float64_mul(q, float64_256, s);
4144
q = float64_add(q, float64_half, s);
4145
q_int = float64_to_int64_round_to_zero(q, s);
4147
/* return (double)s / 256.0 */
4148
return float64_div(int64_to_float64(q_int, s), float64_256, s);
4151
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4153
float_status *s = &env->vfp.standard_fp_status;
4155
uint32_t val32 = float32_val(a);
4158
int a_exp = (val32 & 0x7f800000) >> 23;
4159
int sign = val32 & 0x80000000;
4161
if (float32_is_any_nan(a)) {
4162
if (float32_is_signaling_nan(a)) {
4163
float_raise(float_flag_invalid, s);
4165
return float32_default_nan;
4166
} else if (float32_is_infinity(a)) {
4167
return float32_set_sign(float32_zero, float32_is_neg(a));
4168
} else if (float32_is_zero_or_denormal(a)) {
4169
if (!float32_is_zero(a)) {
4170
float_raise(float_flag_input_denormal, s);
4172
float_raise(float_flag_divbyzero, s);
4173
return float32_set_sign(float32_infinity, float32_is_neg(a));
4174
} else if (a_exp >= 253) {
4175
float_raise(float_flag_underflow, s);
4176
return float32_set_sign(float32_zero, float32_is_neg(a));
4179
f64 = make_float64((0x3feULL << 52)
4180
| ((int64_t)(val32 & 0x7fffff) << 29));
4182
result_exp = 253 - a_exp;
4184
f64 = recip_estimate(f64, env);
4187
| ((result_exp & 0xff) << 23)
4188
| ((float64_val(f64) >> 29) & 0x7fffff);
4189
return make_float32(val32);
4192
/* The algorithm that must be used to calculate the estimate
4193
* is specified by the ARM ARM.
4195
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
4197
/* These calculations mustn't set any fp exception flags,
4198
* so we use a local copy of the fp_status.
4200
float_status dummy_status = env->vfp.standard_fp_status;
4201
float_status *s = &dummy_status;
4205
if (float64_lt(a, float64_half, s)) {
4206
/* range 0.25 <= a < 0.5 */
4208
/* a in units of 1/512 rounded down */
4209
/* q0 = (int)(a * 512.0); */
4210
q = float64_mul(float64_512, a, s);
4211
q_int = float64_to_int64_round_to_zero(q, s);
4213
/* reciprocal root r */
4214
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4215
q = int64_to_float64(q_int, s);
4216
q = float64_add(q, float64_half, s);
4217
q = float64_div(q, float64_512, s);
4218
q = float64_sqrt(q, s);
4219
q = float64_div(float64_one, q, s);
4221
/* range 0.5 <= a < 1.0 */
4223
/* a in units of 1/256 rounded down */
4224
/* q1 = (int)(a * 256.0); */
4225
q = float64_mul(float64_256, a, s);
4226
int64_t q_int = float64_to_int64_round_to_zero(q, s);
4228
/* reciprocal root r */
4229
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4230
q = int64_to_float64(q_int, s);
4231
q = float64_add(q, float64_half, s);
4232
q = float64_div(q, float64_256, s);
4233
q = float64_sqrt(q, s);
4234
q = float64_div(float64_one, q, s);
4236
/* r in units of 1/256 rounded to nearest */
4237
/* s = (int)(256.0 * r + 0.5); */
4239
q = float64_mul(q, float64_256,s );
4240
q = float64_add(q, float64_half, s);
4241
q_int = float64_to_int64_round_to_zero(q, s);
4243
/* return (double)s / 256.0;*/
4244
return float64_div(int64_to_float64(q_int, s), float64_256, s);
4247
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4249
float_status *s = &env->vfp.standard_fp_status;
4255
val = float32_val(a);
4257
if (float32_is_any_nan(a)) {
4258
if (float32_is_signaling_nan(a)) {
4259
float_raise(float_flag_invalid, s);
4261
return float32_default_nan;
4262
} else if (float32_is_zero_or_denormal(a)) {
4263
if (!float32_is_zero(a)) {
4264
float_raise(float_flag_input_denormal, s);
4266
float_raise(float_flag_divbyzero, s);
4267
return float32_set_sign(float32_infinity, float32_is_neg(a));
4268
} else if (float32_is_neg(a)) {
4269
float_raise(float_flag_invalid, s);
4270
return float32_default_nan;
4271
} else if (float32_is_infinity(a)) {
4272
return float32_zero;
4275
/* Normalize to a double-precision value between 0.25 and 1.0,
4276
* preserving the parity of the exponent. */
4277
if ((val & 0x800000) == 0) {
4278
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4280
| ((uint64_t)(val & 0x7fffff) << 29));
4282
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4284
| ((uint64_t)(val & 0x7fffff) << 29));
4287
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4289
f64 = recip_sqrt_estimate(f64, env);
4291
val64 = float64_val(f64);
4293
val = ((result_exp & 0xff) << 23)
4294
| ((val64 >> 29) & 0x7fffff);
4295
return make_float32(val);
4298
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4302
if ((a & 0x80000000) == 0) {
4306
f64 = make_float64((0x3feULL << 52)
4307
| ((int64_t)(a & 0x7fffffff) << 21));
4309
f64 = recip_estimate (f64, env);
4311
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4314
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4318
if ((a & 0xc0000000) == 0) {
4322
if (a & 0x80000000) {
4323
f64 = make_float64((0x3feULL << 52)
4324
| ((uint64_t)(a & 0x7fffffff) << 21));
4325
} else { /* bits 31-30 == '01' */
4326
f64 = make_float64((0x3fdULL << 52)
4327
| ((uint64_t)(a & 0x3fffffff) << 22));
4330
f64 = recip_sqrt_estimate(f64, env);
4332
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4335
/* VFPv4 fused multiply-accumulate */
4336
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4338
float_status *fpst = fpstp;
4339
return float32_muladd(a, b, c, 0, fpst);
4342
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4344
float_status *fpst = fpstp;
4345
return float64_muladd(a, b, c, 0, fpst);
4348
/* ARMv8 VMAXNM/VMINNM */
4349
float32 VFP_HELPER(maxnm, s)(float32 a, float32 b, void *fpstp)
4351
float_status *fpst = fpstp;
4352
return float32_maxnum(a, b, fpst);
4355
float64 VFP_HELPER(maxnm, d)(float64 a, float64 b, void *fpstp)
4357
float_status *fpst = fpstp;
4358
return float64_maxnum(a, b, fpst);
4361
float32 VFP_HELPER(minnm, s)(float32 a, float32 b, void *fpstp)
4363
float_status *fpst = fpstp;
4364
return float32_minnum(a, b, fpst);
4367
float64 VFP_HELPER(minnm, d)(float64 a, float64 b, void *fpstp)
4369
float_status *fpst = fpstp;
4370
return float64_minnum(a, b, fpst);
added
removed
.pc/ubuntu/arm64/0078-target-arm-Use-VFP_BINOP-macro-for-min-max-minnum-ma.patch/target-arm/helper.c
