← Back to branch summary

~ubuntu-branches/ubuntu/vivid/qemu/vivid

« back to all changes in this revision

Viewing changes to debian/patches/ubuntu/arm64/0127-target-arm-Add-support-for-AArch32-SIMD-VRINTX.patch

  • Committer: Package Import Robot
  • Author(s): dann frazier
  • Date: 2014-02-11 15:41:53 UTC
  • Revision ID: package-import@ubuntu.com-20140211154153-2d001tf0ium08u81
Tags: 1.7.0+dfsg-3ubuntu2
* Backport changes to enable qemu-user-static support for aarch64
* debian/control: add ppc64el to Architectures
* debian/rules: only install qemu-system-aarch64 on arm64.
  Fixes a FTBFS  when built twice in a row on non-arm64 due to a stale
  debian/qemu-system-aarch64 directory

Show diffs side-by-side

added added

removed removed

Lines of Context:
debian/patches/ubuntu/arm64/0127-target-arm-Add-support-for-AArch32-SIMD-VRINTX.patch
 
1
From 9ff0a967dfb7f4a583e93d6d3bbe562dfa9f16d7 Mon Sep 17 00:00:00 2001
 
2
From: Will Newton <will.newton@linaro.org>
 
3
Date: Fri, 31 Jan 2014 14:47:34 +0000
 
4
Subject: [PATCH 127/158] target-arm: Add support for AArch32 SIMD VRINTX
 
5
 
 
6
Add support for the AArch32 Advanced SIMD VRINTX instruction.
 
7
 
 
8
Signed-off-by: Will Newton <will.newton@linaro.org>
 
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 
11
---
 
12
 target-arm/translate.c | 11 ++++++++++-
 
13
 1 file changed, 10 insertions(+), 1 deletion(-)
 
14
 
 
15
diff --git a/target-arm/translate.c b/target-arm/translate.c
 
16
index d026024..dd478ae 100644
 
17
--- a/target-arm/translate.c
 
18
+++ b/target-arm/translate.c
 
19
@@ -4719,6 +4719,7 @@ static const uint8_t neon_3r_sizes[] = {
 
20
 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
 
21
 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 
22
 #define NEON_2RM_VSHLL 38
 
23
+#define NEON_2RM_VRINTX 41
 
24
 #define NEON_2RM_VCVT_F16_F32 44
 
25
 #define NEON_2RM_VCVT_F32_F16 46
 
26
 #define NEON_2RM_VRECPE 56
 
27
@@ -4734,7 +4735,7 @@ static int neon_2rm_is_float_op(int op)
 
28
 {
 
29
     /* Return true if this neon 2reg-misc op is float-to-float */
 
30
     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
 
31
-            op >= NEON_2RM_VRECPE_F);
 
32
+            op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F);
 
33
 }
 
34
 
 
35
 /* Each entry in this array has bit n set if the insn allows
 
36
@@ -4776,6 +4777,7 @@ static const uint8_t neon_2rm_sizes[] = {
 
37
     [NEON_2RM_VMOVN] = 0x7,
 
38
     [NEON_2RM_VQMOVN] = 0x7,
 
39
     [NEON_2RM_VSHLL] = 0x7,
 
40
+    [NEON_2RM_VRINTX] = 0x4,
 
41
     [NEON_2RM_VCVT_F16_F32] = 0x2,
 
42
     [NEON_2RM_VCVT_F32_F16] = 0x2,
 
43
     [NEON_2RM_VRECPE] = 0x4,
 
44
@@ -6466,6 +6468,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
 
45
                             }
 
46
                             neon_store_reg(rm, pass, tmp2);
 
47
                             break;
 
48
+                        case NEON_2RM_VRINTX:
 
49
+                        {
 
50
+                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
 
51
+                            gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
 
52
+                            tcg_temp_free_ptr(fpstatus);
 
53
+                            break;
 
54
+                        }
 
55
                         case NEON_2RM_VRECPE:
 
56
                             gen_helper_recpe_u32(tmp, tmp, cpu_env);
 
57
                             break;
 
58
-- 
 
59
1.9.rc1
 
60