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Viewing changes to debian/patches/ubuntu/arm64/0133-target-arm-A64-Add-SIMD-three-different-ABDL-instruc.patch

  • Committer: Package Import Robot
  • Author(s): dann frazier
  • Date: 2014-02-11 15:41:53 UTC
  • Revision ID: package-import@ubuntu.com-20140211154153-2d001tf0ium08u81
Tags: 1.7.0+dfsg-3ubuntu2
* Backport changes to enable qemu-user-static support for aarch64
* debian/control: add ppc64el to Architectures
* debian/rules: only install qemu-system-aarch64 on arm64.
  Fixes a FTBFS  when built twice in a row on non-arm64 due to a stale
  debian/qemu-system-aarch64 directory

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debian/patches/ubuntu/arm64/0133-target-arm-A64-Add-SIMD-three-different-ABDL-instruc.patch
 
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From 3526cb5986df2ccbe0cded717f4e27443fd9ef37 Mon Sep 17 00:00:00 2001
 
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From: Peter Maydell <peter.maydell@linaro.org>
 
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Date: Fri, 31 Jan 2014 14:47:36 +0000
 
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Subject: [PATCH 133/158] target-arm: A64: Add SIMD three-different ABDL
 
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 instructions
 
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Implement the absolute-difference instructions in the SIMD
 
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three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
 
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SABDL2, UABDL, UABDL2.
 
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 
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Reviewed-by: Richard Henderson <rth@twiddle.net>
 
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---
 
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 target-arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++--
 
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 1 file changed, 33 insertions(+), 2 deletions(-)
 
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
 
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index e8479a5..e098efd 100644
 
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--- a/target-arm/translate-a64.c
 
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+++ b/target-arm/translate-a64.c
 
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@@ -5602,6 +5602,21 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
 
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             }
 
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             switch (opcode) {
 
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+            case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
 
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+            case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
 
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+            {
 
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+                TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
 
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+                TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
 
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+
 
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+                tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
 
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+                tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
 
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+                tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
 
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+                                    tcg_passres,
 
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+                                    tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
 
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+                tcg_temp_free_i64(tcg_tmp1);
 
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+                tcg_temp_free_i64(tcg_tmp2);
 
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+                break;
 
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+            }
 
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             case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
 
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             case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
 
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             case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
 
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@@ -5640,6 +5655,22 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
 
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             }
 
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             switch (opcode) {
 
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+            case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
 
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+            case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
 
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+                if (size == 0) {
 
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+                    if (is_u) {
 
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+                        gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
 
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+                    } else {
 
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+                        gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
 
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+                    }
 
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+                } else {
 
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+                    if (is_u) {
 
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+                        gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
 
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+                    } else {
 
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+                        gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
 
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+                    }
 
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+                }
 
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+                break;
 
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             case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
 
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             case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
 
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             case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
 
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@@ -5739,10 +5770,10 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
 
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         /* fall through */
 
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     case 0:
 
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     case 2:
 
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-    case 5:
 
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-    case 7:
 
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         unsupported_encoding(s, insn);
 
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         break;
 
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+    case 5:
 
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+    case 7:
 
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     case 8:
 
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     case 10:
 
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     case 12:
 
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-- 
 
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1.9.rc1
 
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