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Viewing changes to debian/patches/ubuntu/arm64/0131-target-arm-Add-AArch32-SIMD-VCVTA-VCVTN-VCVTP-and-VC.patch

  • Committer: Package Import Robot
  • Author(s): dann frazier
  • Date: 2014-02-11 15:41:53 UTC
  • Revision ID: package-import@ubuntu.com-20140211154153-2d001tf0ium08u81
Tags: 1.7.0+dfsg-3ubuntu2
* Backport changes to enable qemu-user-static support for aarch64
* debian/control: add ppc64el to Architectures
* debian/rules: only install qemu-system-aarch64 on arm64.
  Fixes a FTBFS  when built twice in a row on non-arm64 due to a stale
  debian/qemu-system-aarch64 directory

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debian/patches/ubuntu/arm64/0131-target-arm-Add-AArch32-SIMD-VCVTA-VCVTN-VCVTP-and-VC.patch
 
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From cb20c043fcf2bb963f9d1bda012fadc9af3e787d Mon Sep 17 00:00:00 2001
 
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From: Will Newton <will.newton@linaro.org>
 
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Date: Fri, 31 Jan 2014 14:47:35 +0000
 
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Subject: [PATCH 131/158] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and
 
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 VCVTM
 
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Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
 
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and VCVTM instructions.
 
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Signed-off-by: Will Newton <will.newton@linaro.org>
 
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 
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---
 
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 target-arm/translate.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++-
 
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 1 file changed, 52 insertions(+), 1 deletion(-)
 
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diff --git a/target-arm/translate.c b/target-arm/translate.c
 
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index 327f453..091db1b 100644
 
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--- a/target-arm/translate.c
 
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+++ b/target-arm/translate.c
 
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@@ -4788,6 +4788,14 @@ static const uint8_t neon_3r_sizes[] = {
 
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 #define NEON_2RM_VRINTM 45
 
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 #define NEON_2RM_VCVT_F32_F16 46
 
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 #define NEON_2RM_VRINTP 47
 
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+#define NEON_2RM_VCVTAU 48
 
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+#define NEON_2RM_VCVTAS 49
 
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+#define NEON_2RM_VCVTNU 50
 
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+#define NEON_2RM_VCVTNS 51
 
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+#define NEON_2RM_VCVTPU 52
 
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+#define NEON_2RM_VCVTPS 53
 
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+#define NEON_2RM_VCVTMU 54
 
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+#define NEON_2RM_VCVTMS 55
 
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 #define NEON_2RM_VRECPE 56
 
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 #define NEON_2RM_VRSQRTE 57
 
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 #define NEON_2RM_VRECPE_F 58
 
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@@ -4802,7 +4810,8 @@ static int neon_2rm_is_float_op(int op)
 
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     /* Return true if this neon 2reg-misc op is float-to-float */
 
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     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
 
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             (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
 
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-            op == NEON_2RM_VRINTM || op == NEON_2RM_VRINTP ||
 
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+            op == NEON_2RM_VRINTM ||
 
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+            (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
 
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             op >= NEON_2RM_VRECPE_F);
 
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 }
 
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@@ -4853,6 +4862,14 @@ static const uint8_t neon_2rm_sizes[] = {
 
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     [NEON_2RM_VRINTM] = 0x4,
 
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     [NEON_2RM_VCVT_F32_F16] = 0x2,
 
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     [NEON_2RM_VRINTP] = 0x4,
 
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+    [NEON_2RM_VCVTAU] = 0x4,
 
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+    [NEON_2RM_VCVTAS] = 0x4,
 
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+    [NEON_2RM_VCVTNU] = 0x4,
 
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+    [NEON_2RM_VCVTNS] = 0x4,
 
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+    [NEON_2RM_VCVTPU] = 0x4,
 
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+    [NEON_2RM_VCVTPS] = 0x4,
 
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+    [NEON_2RM_VCVTMU] = 0x4,
 
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+    [NEON_2RM_VCVTMS] = 0x4,
 
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     [NEON_2RM_VRECPE] = 0x4,
 
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     [NEON_2RM_VRSQRTE] = 0x4,
 
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     [NEON_2RM_VRECPE_F] = 0x4,
 
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@@ -6574,6 +6591,40 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
 
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                             tcg_temp_free_ptr(fpstatus);
 
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                             break;
 
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                         }
 
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+                        case NEON_2RM_VCVTAU:
 
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+                        case NEON_2RM_VCVTAS:
 
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+                        case NEON_2RM_VCVTNU:
 
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+                        case NEON_2RM_VCVTNS:
 
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+                        case NEON_2RM_VCVTPU:
 
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+                        case NEON_2RM_VCVTPS:
 
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+                        case NEON_2RM_VCVTMU:
 
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+                        case NEON_2RM_VCVTMS:
 
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+                        {
 
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+                            bool is_signed = !extract32(insn, 7, 1);
 
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+                            TCGv_ptr fpst = get_fpstatus_ptr(1);
 
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+                            TCGv_i32 tcg_rmode, tcg_shift;
 
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+                            int rmode = fp_decode_rm[extract32(insn, 8, 2)];
 
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+
 
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+                            tcg_shift = tcg_const_i32(0);
 
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+                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
 
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+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
 
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+                                                      cpu_env);
 
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+
 
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+                            if (is_signed) {
 
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+                                gen_helper_vfp_tosls(cpu_F0s, cpu_F0s,
 
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+                                                     tcg_shift, fpst);
 
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+                            } else {
 
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+                                gen_helper_vfp_touls(cpu_F0s, cpu_F0s,
 
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+                                                     tcg_shift, fpst);
 
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+                            }
 
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+
 
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+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
 
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+                                                      cpu_env);
 
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+                            tcg_temp_free_i32(tcg_rmode);
 
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+                            tcg_temp_free_i32(tcg_shift);
 
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+                            tcg_temp_free_ptr(fpst);
 
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+                            break;
 
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+                        }
 
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                         case NEON_2RM_VRECPE:
 
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                             gen_helper_recpe_u32(tmp, tmp, cpu_env);
 
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                             break;
 
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-- 
 
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1.9.rc1
 
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