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From a451a7a6c7ea238490771d660b95dccc60dcd7ed Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Sat, 4 Jan 2014 22:15:44 +0000
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Subject: [PATCH 063/158] target-arm: Remove ARMCPU/CPUARMState from cpregs
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The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
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cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
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This is problematic for the A64 decoder, which doesn't pass the
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environment pointer around everywhere the way the 32 bit decoder
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does. Adjust the parameters these functions take so that we can
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copy only the relevant info from the CPUARMState into the
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DisasContext and then use that.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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target-arm/cpu.h | 6 +++---
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target-arm/helper.c | 12 ++++++------
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target-arm/translate-a64.c | 2 ++
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target-arm/translate.c | 7 ++++---
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target-arm/translate.h | 2 ++
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5 files changed, 17 insertions(+), 12 deletions(-)
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diff --git a/target-arm/cpu.h b/target-arm/cpu.h
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index a154429..9dade70 100644
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--- a/target-arm/cpu.h
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+++ b/target-arm/cpu.h
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@@ -857,7 +857,7 @@ static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
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define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
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-const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
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+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
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/* CPWriteFn that can be used to implement writes-ignored behaviour */
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int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
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@@ -870,10 +870,10 @@ int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
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void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
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-static inline bool cp_access_ok(CPUARMState *env,
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+static inline bool cp_access_ok(int current_pl,
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const ARMCPRegInfo *ri, int isread)
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- return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
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+ return (ri->access >> ((current_pl * 2) + isread)) & 1;
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diff --git a/target-arm/helper.c b/target-arm/helper.c
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index ef73df9..be641bc 100644
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--- a/target-arm/helper.c
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+++ b/target-arm/helper.c
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@@ -186,7 +186,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
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uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
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const ARMCPRegInfo *ri;
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- ri = get_arm_cp_reginfo(cpu, regidx);
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+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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@@ -214,7 +214,7 @@ bool write_list_to_cpustate(ARMCPU *cpu)
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const ARMCPRegInfo *ri;
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- ri = get_arm_cp_reginfo(cpu, regidx);
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+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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@@ -242,7 +242,7 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
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const ARMCPRegInfo *ri;
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regidx = *(uint32_t *)key;
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- ri = get_arm_cp_reginfo(cpu, regidx);
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+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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if (!(ri->type & ARM_CP_NO_MIGRATE)) {
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cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
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@@ -258,7 +258,7 @@ static void count_cpreg(gpointer key, gpointer opaque)
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const ARMCPRegInfo *ri;
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regidx = *(uint32_t *)key;
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- ri = get_arm_cp_reginfo(cpu, regidx);
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+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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if (!(ri->type & ARM_CP_NO_MIGRATE)) {
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cpu->cpreg_array_len++;
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@@ -2145,9 +2145,9 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
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-const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
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+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
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- return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
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+ return g_hash_table_lookup(cpregs, &encoded_cp);
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int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
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index 7d98337..e35d2f3 100644
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--- a/target-arm/translate-a64.c
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+++ b/target-arm/translate-a64.c
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@@ -3007,6 +3007,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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+ dc->cp_regs = cpu->cp_regs;
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+ dc->current_pl = arm_current_pl(env);
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init_tmp_a64_array(dc);
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index a0a1ab2..e00c650 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -6484,7 +6484,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
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const ARMCPRegInfo *ri;
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- ARMCPU *cpu = arm_env_get_cpu(env);
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cpnum = (insn >> 8) & 0xf;
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if (arm_feature(env, ARM_FEATURE_XSCALE)
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@@ -6527,11 +6526,11 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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isread = (insn >> 20) & 1;
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rt = (insn >> 12) & 0xf;
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- ri = get_arm_cp_reginfo(cpu,
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+ ri = get_arm_cp_reginfo(s->cp_regs,
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ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2));
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/* Check access permissions */
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- if (!cp_access_ok(env, ri, isread)) {
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+ if (!cp_access_ok(s->current_pl, ri, isread)) {
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@@ -10266,6 +10265,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
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dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
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dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
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+ dc->cp_regs = cpu->cp_regs;
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+ dc->current_pl = arm_current_pl(env);
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cpu_F0s = tcg_temp_new_i32();
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cpu_F1s = tcg_temp_new_i32();
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diff --git a/target-arm/translate.h b/target-arm/translate.h
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index a6f6b3e..67da699 100644
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--- a/target-arm/translate.h
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+++ b/target-arm/translate.h
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@@ -24,6 +24,8 @@ typedef struct DisasContext {
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+ GHashTable *cp_regs;
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#define TMP_A64_MAX 16
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TCGv_i64 tmp_a64[TMP_A64_MAX];