2
#include "exec/gdbstub.h"
4
#include "qemu/host-utils.h"
5
#include "sysemu/arch_init.h"
6
#include "sysemu/sysemu.h"
7
#include "qemu/bitops.h"
9
#ifndef CONFIG_USER_ONLY
10
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11
int access_type, int is_user,
12
hwaddr *phys_ptr, int *prot,
13
target_ulong *page_size);
16
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
20
/* VFP data registers are always little-endian. */
21
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
23
stfq_le_p(buf, env->vfp.regs[reg]);
26
if (arm_feature(env, ARM_FEATURE_NEON)) {
27
/* Aliases for Q regs. */
30
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
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stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
35
switch (reg - nregs) {
36
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
43
static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
47
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
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env->vfp.regs[reg] = ldfq_le_p(buf);
52
if (arm_feature(env, ARM_FEATURE_NEON)) {
55
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
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env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
60
switch (reg - nregs) {
61
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
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case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
68
static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
72
/* 128 bit FP register */
73
stfq_le_p(buf, env->vfp.regs[reg * 2]);
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stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
78
stl_p(buf, vfp_get_fpsr(env));
82
stl_p(buf, vfp_get_fpcr(env));
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static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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/* 128 bit FP register */
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env->vfp.regs[reg * 2] = ldfq_le_p(buf);
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env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
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vfp_set_fpsr(env, ldl_p(buf));
103
vfp_set_fpcr(env, ldl_p(buf));
110
static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
113
if (ri->type & ARM_CP_64BIT) {
114
*value = CPREG_FIELD64(env, ri);
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*value = CPREG_FIELD32(env, ri);
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static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
124
if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(env, ri) = value;
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CPREG_FIELD32(env, ri) = value;
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static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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/* Raw read of a coprocessor register (as needed for migration, etc)
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* return true on success, false if the read is impossible for some reason.
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if (ri->type & ARM_CP_CONST) {
140
} else if (ri->raw_readfn) {
141
return (ri->raw_readfn(env, ri, v) == 0);
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} else if (ri->readfn) {
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return (ri->readfn(env, ri, v) == 0);
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raw_read(env, ri, v);
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static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
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/* Raw write of a coprocessor register (as needed for migration, etc).
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* Return true on success, false if the write is impossible for some reason.
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* Note that constant registers are treated as write-ignored; the
156
* caller should check for success by whether a readback gives the
159
if (ri->type & ARM_CP_CONST) {
161
} else if (ri->raw_writefn) {
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return (ri->raw_writefn(env, ri, v) == 0);
163
} else if (ri->writefn) {
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return (ri->writefn(env, ri, v) == 0);
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raw_write(env, ri, v);
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bool write_cpustate_to_list(ARMCPU *cpu)
173
/* Write the coprocessor state from cpu->env to the (index,value) list. */
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for (i = 0; i < cpu->cpreg_array_len; i++) {
178
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
179
const ARMCPRegInfo *ri;
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ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
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if (ri->type & ARM_CP_NO_MIGRATE) {
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if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
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cpu->cpreg_values[i] = v;
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bool write_list_to_cpustate(ARMCPU *cpu)
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for (i = 0; i < cpu->cpreg_array_len; i++) {
204
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
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uint64_t v = cpu->cpreg_values[i];
207
const ARMCPRegInfo *ri;
209
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
214
if (ri->type & ARM_CP_NO_MIGRATE) {
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/* Write value and confirm it reads back as written
218
* (to catch read-only registers and partially read-only
219
* registers where the incoming migration value doesn't match)
221
if (!write_raw_cp_reg(&cpu->env, ri, v) ||
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!read_raw_cp_reg(&cpu->env, ri, &readback) ||
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static void add_cpreg_to_list(gpointer key, gpointer opaque)
232
ARMCPU *cpu = opaque;
234
const ARMCPRegInfo *ri;
236
regidx = *(uint32_t *)key;
237
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
239
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
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cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
241
/* The value array need not be initialized at this point */
242
cpu->cpreg_array_len++;
246
static void count_cpreg(gpointer key, gpointer opaque)
248
ARMCPU *cpu = opaque;
250
const ARMCPRegInfo *ri;
252
regidx = *(uint32_t *)key;
253
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
255
if (!(ri->type & ARM_CP_NO_MIGRATE)) {
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cpu->cpreg_array_len++;
260
static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
262
uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
263
uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
274
static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
276
GList **plist = udata;
278
*plist = g_list_prepend(*plist, key);
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void init_cpreg_list(ARMCPU *cpu)
283
/* Initialise the cpreg_tuples[] array based on the cp_regs hash.
284
* Note that we require cpreg_tuples[] to be sorted by key ID.
289
g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
291
keys = g_list_sort(keys, cpreg_key_compare);
293
cpu->cpreg_array_len = 0;
295
g_list_foreach(keys, count_cpreg, cpu);
297
arraylen = cpu->cpreg_array_len;
298
cpu->cpreg_indexes = g_new(uint64_t, arraylen);
299
cpu->cpreg_values = g_new(uint64_t, arraylen);
300
cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
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cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
302
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
303
cpu->cpreg_array_len = 0;
305
g_list_foreach(keys, add_cpreg_to_list, cpu);
307
assert(cpu->cpreg_array_len == arraylen);
312
static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
314
env->cp15.c3 = value;
315
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
319
static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
321
if (env->cp15.c13_fcse != value) {
322
/* Unlike real hardware the qemu TLB uses virtual addresses,
323
* not modified virtual addresses, so this causes a TLB flush.
326
env->cp15.c13_fcse = value;
330
static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
333
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
334
/* For VMSA (when not using the LPAE long descriptor page table
335
* format) this register includes the ASID, so do a TLB flush.
336
* For PMSA it is purely a process ID and no action is needed.
340
env->cp15.c13_context = value;
344
static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
347
/* Invalidate all (TLBIALL) */
352
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
355
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
356
tlb_flush_page(env, value & TARGET_PAGE_MASK);
360
static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
363
/* Invalidate by ASID (TLBIASID) */
364
tlb_flush(env, value == 0);
368
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
371
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
372
tlb_flush_page(env, value & TARGET_PAGE_MASK);
376
static const ARMCPRegInfo cp_reginfo[] = {
377
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
378
* version" bits will read as a reserved value, which should cause
379
* Linux to not try to use the debug hardware.
381
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* MMU Domain access control / MPU write buffer control */
384
{ .name = "DACR", .cp = 15,
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.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
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.resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
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{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
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{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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/* ??? This covers not just the impdef TLB lockdown registers but also
395
* some v7VMSA registers relating to TEX remap, so it is overly broad.
397
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
398
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
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/* MMU TLB control. Note that the wildcarding means we cover not just
400
* the unified TLB ops but also the dside/iside/inner-shareable variants.
402
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
403
.opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
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.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
406
.opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
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.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
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.opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
410
.type = ARM_CP_NO_MIGRATE },
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{ .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
412
.opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
413
.type = ARM_CP_NO_MIGRATE },
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/* Cache maintenance ops; some of this space may be overridden later. */
415
{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
416
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
417
.type = ARM_CP_NOP | ARM_CP_OVERRIDE },
421
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
422
/* Not all pre-v6 cores implemented this WFI, so this is slightly
425
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
426
.access = PL1_W, .type = ARM_CP_WFI },
430
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
431
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432
* is UNPREDICTABLE; we choose to NOP as most implementations do).
434
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
435
.access = PL1_W, .type = ARM_CP_WFI },
436
/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438
* OMAPCP will override this space.
440
{ .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
441
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
443
{ .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
444
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
446
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
447
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
448
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
453
static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
455
if (env->cp15.c1_coproc != value) {
456
env->cp15.c1_coproc = value;
457
/* ??? Is this safe when called from within a TB? */
463
static const ARMCPRegInfo v6_cp_reginfo[] = {
464
/* prefetch by MVA in v6, NOP in v7 */
465
{ .name = "MVA_prefetch",
466
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
467
.access = PL1_W, .type = ARM_CP_NOP },
468
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
469
.access = PL0_W, .type = ARM_CP_NOP },
470
{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
471
.access = PL0_W, .type = ARM_CP_NOP },
472
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
473
.access = PL0_W, .type = ARM_CP_NOP },
474
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
475
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
477
/* Watchpoint Fault Address Register : should actually only be present
478
* for 1136, 1176, 11MPCore.
480
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
481
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
482
{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
483
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
484
.resetvalue = 0, .writefn = cpacr_write },
489
static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
492
/* Generic performance monitor register read function for where
493
* user access may be allowed by PMUSERENR.
495
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
498
*value = CPREG_FIELD32(env, ri);
502
static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
505
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
508
/* only the DP, X, D and E bits are writable */
509
env->cp15.c9_pmcr &= ~0x39;
510
env->cp15.c9_pmcr |= (value & 0x39);
514
static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
517
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
521
env->cp15.c9_pmcnten |= value;
525
static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
528
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
532
env->cp15.c9_pmcnten &= ~value;
536
static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
539
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
542
env->cp15.c9_pmovsr &= ~value;
546
static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
549
if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
552
env->cp15.c9_pmxevtyper = value & 0xff;
556
static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
559
env->cp15.c9_pmuserenr = value & 1;
563
static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
566
/* We have no event counters so only the C bit can be changed */
568
env->cp15.c9_pminten |= value;
572
static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
576
env->cp15.c9_pminten &= ~value;
580
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
583
ARMCPU *cpu = arm_env_get_cpu(env);
584
*value = cpu->ccsidr[env->cp15.c0_cssel];
588
static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
591
env->cp15.c0_cssel = value & 0xf;
595
static const ARMCPRegInfo v7_cp_reginfo[] = {
596
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
599
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
600
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
601
{ .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
602
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
603
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
604
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
605
.access = PL1_W, .type = ARM_CP_NOP },
606
/* Performance monitors are implementation defined in v7,
607
* but with an ARM recommended set of registers, which we
608
* follow (although we don't actually implement any counters)
610
* Performance registers fall into three categories:
611
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
612
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
613
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
614
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
615
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
617
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
618
.access = PL0_RW, .resetvalue = 0,
619
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
620
.readfn = pmreg_read, .writefn = pmcntenset_write,
621
.raw_readfn = raw_read, .raw_writefn = raw_write },
622
{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
623
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
624
.readfn = pmreg_read, .writefn = pmcntenclr_write,
625
.type = ARM_CP_NO_MIGRATE },
626
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
627
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
628
.readfn = pmreg_read, .writefn = pmovsr_write,
629
.raw_readfn = raw_read, .raw_writefn = raw_write },
630
/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
633
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
634
.access = PL0_W, .type = ARM_CP_NOP },
635
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
636
* We choose to RAZ/WI. XXX should respect PMUSERENR.
638
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
639
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
640
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
641
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
642
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
643
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
645
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
646
.readfn = pmreg_read, .writefn = pmxevtyper_write,
647
.raw_readfn = raw_read, .raw_writefn = raw_write },
648
/* Unimplemented, RAZ/WI. XXX PMUSERENR */
649
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
650
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
651
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
652
.access = PL0_R | PL1_RW,
653
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
655
.writefn = pmuserenr_write, .raw_writefn = raw_write },
656
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
658
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
660
.writefn = pmintenset_write, .raw_writefn = raw_write },
661
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
662
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
663
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
664
.resetvalue = 0, .writefn = pmintenclr_write, },
665
{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
666
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
667
{ .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
668
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
669
.writefn = csselr_write, .resetvalue = 0 },
670
/* Auxiliary ID register: this actually has an IMPDEF value but for now
671
* just RAZ for all cores:
673
{ .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
674
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
678
static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
685
static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
688
/* This is a helper function because the user access rights
689
* depend on the value of the TEECR.
691
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
694
*value = env->teehbr;
698
static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
701
if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
708
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
709
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
710
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
712
.writefn = teecr_write },
713
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
714
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
715
.resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
716
.readfn = teehbr_read, .writefn = teehbr_write },
720
static const ARMCPRegInfo v6k_cp_reginfo[] = {
721
{ .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
722
.opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
724
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
725
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
727
.fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
728
.resetfn = arm_cp_reset_ignore },
729
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
730
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
731
.access = PL0_R|PL1_W,
732
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
733
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
734
.access = PL0_R|PL1_W,
735
.fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
736
.resetfn = arm_cp_reset_ignore },
737
{ .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
738
.opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
740
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
744
#ifndef CONFIG_USER_ONLY
746
static uint64_t gt_get_countervalue(CPUARMState *env)
748
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
751
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
753
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
756
/* Timer enabled: calculate and set current ISTATUS, irq, and
757
* reset timer to when ISTATUS next has to change
759
uint64_t count = gt_get_countervalue(&cpu->env);
760
/* Note that this must be unsigned 64 bit arithmetic: */
761
int istatus = count >= gt->cval;
764
gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
765
qemu_set_irq(cpu->gt_timer_outputs[timeridx],
766
(istatus && !(gt->ctl & 2)));
768
/* Next transition is when count rolls back over to zero */
769
nexttick = UINT64_MAX;
771
/* Next transition is when we hit cval */
774
/* Note that the desired next expiry time might be beyond the
775
* signed-64-bit range of a QEMUTimer -- in this case we just
776
* set the timer for as far in the future as possible. When the
777
* timer expires we will reset the timer for any remaining period.
779
if (nexttick > INT64_MAX / GTIMER_SCALE) {
780
nexttick = INT64_MAX / GTIMER_SCALE;
782
timer_mod(cpu->gt_timer[timeridx], nexttick);
784
/* Timer disabled: ISTATUS and timer output always clear */
786
qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
787
timer_del(cpu->gt_timer[timeridx]);
791
static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
794
/* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
795
if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
798
*value = env->cp15.c14_cntfrq;
802
static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
804
ARMCPU *cpu = arm_env_get_cpu(env);
805
int timeridx = ri->opc1 & 1;
807
timer_del(cpu->gt_timer[timeridx]);
810
static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
813
int timeridx = ri->opc1 & 1;
815
if (arm_current_pl(env) == 0 &&
816
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
819
*value = gt_get_countervalue(env);
823
static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
826
int timeridx = ri->opc1 & 1;
828
if (arm_current_pl(env) == 0 &&
829
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
832
*value = env->cp15.c14_timer[timeridx].cval;
836
static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
839
int timeridx = ri->opc1 & 1;
841
env->cp15.c14_timer[timeridx].cval = value;
842
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
845
static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
848
int timeridx = ri->crm & 1;
850
if (arm_current_pl(env) == 0 &&
851
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
854
*value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
855
gt_get_countervalue(env));
859
static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
862
int timeridx = ri->crm & 1;
864
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
865
+ sextract64(value, 0, 32);
866
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
870
static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
873
int timeridx = ri->crm & 1;
875
if (arm_current_pl(env) == 0 &&
876
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
879
*value = env->cp15.c14_timer[timeridx].ctl;
883
static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
886
ARMCPU *cpu = arm_env_get_cpu(env);
887
int timeridx = ri->crm & 1;
888
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
890
env->cp15.c14_timer[timeridx].ctl = value & 3;
891
if ((oldval ^ value) & 1) {
893
gt_recalc_timer(cpu, timeridx);
894
} else if ((oldval & value) & 2) {
895
/* IMASK toggled: don't need to recalculate,
896
* just set the interrupt line based on ISTATUS
898
qemu_set_irq(cpu->gt_timer_outputs[timeridx],
899
(oldval & 4) && (value & 2));
904
void arm_gt_ptimer_cb(void *opaque)
906
ARMCPU *cpu = opaque;
908
gt_recalc_timer(cpu, GTIMER_PHYS);
911
void arm_gt_vtimer_cb(void *opaque)
913
ARMCPU *cpu = opaque;
915
gt_recalc_timer(cpu, GTIMER_VIRT);
918
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
919
/* Note that CNTFRQ is purely reads-as-written for the benefit
920
* of software; writing it doesn't actually change the timer frequency.
921
* Our reset value matches the fixed frequency we implement the timer at.
923
{ .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
924
.access = PL1_RW | PL0_R,
925
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
926
.resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
927
.readfn = gt_cntfrq_read, .raw_readfn = raw_read,
929
/* overall control: mostly access permissions */
930
{ .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
932
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
935
/* per-timer control */
936
{ .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
937
.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
938
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
940
.readfn = gt_ctl_read, .writefn = gt_ctl_write,
941
.raw_readfn = raw_read, .raw_writefn = raw_write,
943
{ .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
944
.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
945
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
947
.readfn = gt_ctl_read, .writefn = gt_ctl_write,
948
.raw_readfn = raw_read, .raw_writefn = raw_write,
950
/* TimerValue views: a 32 bit downcounting view of the underlying state */
951
{ .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
952
.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
953
.readfn = gt_tval_read, .writefn = gt_tval_write,
955
{ .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
956
.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
957
.readfn = gt_tval_read, .writefn = gt_tval_write,
959
/* The counter itself */
960
{ .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
961
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
962
.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
964
{ .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
965
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
966
.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
968
/* Comparison value, indicating when the timer goes off */
969
{ .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
970
.access = PL1_RW | PL0_R,
971
.type = ARM_CP_64BIT | ARM_CP_IO,
972
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
974
.readfn = gt_cval_read, .writefn = gt_cval_write,
975
.raw_readfn = raw_read, .raw_writefn = raw_write,
977
{ .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
978
.access = PL1_RW | PL0_R,
979
.type = ARM_CP_64BIT | ARM_CP_IO,
980
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
982
.readfn = gt_cval_read, .writefn = gt_cval_write,
983
.raw_readfn = raw_read, .raw_writefn = raw_write,
989
/* In user-mode none of the generic timer registers are accessible,
990
* and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
991
* so instead just don't register any of them.
993
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
999
static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1001
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1002
env->cp15.c7_par = value;
1003
} else if (arm_feature(env, ARM_FEATURE_V7)) {
1004
env->cp15.c7_par = value & 0xfffff6ff;
1006
env->cp15.c7_par = value & 0xfffff1ff;
1011
#ifndef CONFIG_USER_ONLY
1012
/* get_phys_addr() isn't present for user-mode-only targets */
1014
/* Return true if extended addresses are enabled, ie this is an
1015
* LPAE implementation and we are using the long-descriptor translation
1016
* table format because the TTBCR EAE bit is set.
1018
static inline bool extended_addresses_enabled(CPUARMState *env)
1020
return arm_feature(env, ARM_FEATURE_LPAE)
1021
&& (env->cp15.c2_control & (1U << 31));
1024
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1027
target_ulong page_size;
1029
int ret, is_user = ri->opc2 & 2;
1030
int access_type = ri->opc2 & 1;
1033
/* Other states are only available with TrustZone */
1036
ret = get_phys_addr(env, value, access_type, is_user,
1037
&phys_addr, &prot, &page_size);
1038
if (extended_addresses_enabled(env)) {
1039
/* ret is a DFSR/IFSR value for the long descriptor
1040
* translation table format, but with WnR always clear.
1041
* Convert it to a 64-bit PAR.
1043
uint64_t par64 = (1 << 11); /* LPAE bit always set */
1045
par64 |= phys_addr & ~0xfffULL;
1046
/* We don't set the ATTR or SH fields in the PAR. */
1049
par64 |= (ret & 0x3f) << 1; /* FS */
1050
/* Note that S2WLK and FSTAGE are always zero, because we don't
1051
* implement virtualization and therefore there can't be a stage 2
1055
env->cp15.c7_par = par64;
1056
env->cp15.c7_par_hi = par64 >> 32;
1058
/* ret is a DFSR/IFSR value for the short descriptor
1059
* translation table format (with WnR always clear).
1060
* Convert it to a 32-bit PAR.
1063
/* We do not set any attribute bits in the PAR */
1064
if (page_size == (1 << 24)
1065
&& arm_feature(env, ARM_FEATURE_V7)) {
1066
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1068
env->cp15.c7_par = phys_addr & 0xfffff000;
1071
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1072
((ret & (12 << 1)) >> 6) |
1073
((ret & 0xf) << 1) | 1;
1075
env->cp15.c7_par_hi = 0;
1081
static const ARMCPRegInfo vapa_cp_reginfo[] = {
1082
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1083
.access = PL1_RW, .resetvalue = 0,
1084
.fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1085
.writefn = par_write },
1086
#ifndef CONFIG_USER_ONLY
1087
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1088
.access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1093
/* Return basic MPU access permission bits. */
1094
static uint32_t simple_mpu_ap_bits(uint32_t val)
1101
for (i = 0; i < 16; i += 2) {
1102
ret |= (val >> i) & mask;
1108
/* Pad basic MPU access permission bits to extended format. */
1109
static uint32_t extended_mpu_ap_bits(uint32_t val)
1116
for (i = 0; i < 16; i += 2) {
1117
ret |= (val & mask) << i;
1123
static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1126
env->cp15.c5_data = extended_mpu_ap_bits(value);
1130
static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1133
*value = simple_mpu_ap_bits(env->cp15.c5_data);
1137
static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1140
env->cp15.c5_insn = extended_mpu_ap_bits(value);
1144
static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1147
*value = simple_mpu_ap_bits(env->cp15.c5_insn);
1151
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1157
*value = env->cp15.c6_region[ri->crm];
1161
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1167
env->cp15.c6_region[ri->crm] = value;
1171
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1172
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1173
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1174
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1175
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1176
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1177
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1178
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1179
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1180
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1182
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1183
{ .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1185
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1186
{ .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1188
.fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1189
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1191
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1192
/* Protection region base and size registers */
1193
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1194
.opc2 = CP_ANY, .access = PL1_RW,
1195
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
1199
static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1202
int maskshift = extract32(value, 0, 3);
1204
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1205
value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1209
/* Note that we always calculate c2_mask and c2_base_mask, but
1210
* they are only used for short-descriptor tables (ie if EAE is 0);
1211
* for long-descriptor tables the TTBCR fields are used differently
1212
* and the c2_mask and c2_base_mask values are meaningless.
1214
env->cp15.c2_control = value;
1215
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1216
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1220
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1223
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1224
/* With LPAE the TTBCR could result in a change of ASID
1225
* via the TTBCR.A1 bit, so do a TLB flush.
1229
return vmsa_ttbcr_raw_write(env, ri, value);
1232
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1234
env->cp15.c2_base_mask = 0xffffc000u;
1235
env->cp15.c2_control = 0;
1236
env->cp15.c2_mask = 0;
1239
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1240
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1242
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1243
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1245
.fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1246
{ .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1248
.fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1249
{ .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1251
.fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
1252
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1253
.access = PL1_RW, .writefn = vmsa_ttbcr_write,
1254
.resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
1255
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1256
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1257
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1262
static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1265
env->cp15.c15_ticonfig = value & 0xe7;
1266
/* The OS_TYPE bit in this register changes the reported CPUID! */
1267
env->cp15.c0_cpuid = (value & (1 << 5)) ?
1268
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1272
static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1275
env->cp15.c15_threadid = value & 0xffff;
1279
static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1282
/* Wait-for-interrupt (deprecated) */
1283
cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1287
static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1290
/* On OMAP there are registers indicating the max/min index of dcache lines
1291
* containing a dirty line; cache flush operations have to reset these.
1293
env->cp15.c15_i_max = 0x000;
1294
env->cp15.c15_i_min = 0xff0;
1298
static const ARMCPRegInfo omap_cp_reginfo[] = {
1299
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1300
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1301
.fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1302
{ .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1303
.access = PL1_RW, .type = ARM_CP_NOP },
1304
{ .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1306
.fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1307
.writefn = omap_ticonfig_write },
1308
{ .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1310
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1311
{ .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1312
.access = PL1_RW, .resetvalue = 0xff0,
1313
.fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1314
{ .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1316
.fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1317
.writefn = omap_threadid_write },
1318
{ .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1319
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1320
.type = ARM_CP_NO_MIGRATE,
1321
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1322
/* TODO: Peripheral port remap register:
1323
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1324
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1327
{ .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1328
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1329
.type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1330
.writefn = omap_cachemaint_write },
1331
{ .name = "C9", .cp = 15, .crn = 9,
1332
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1333
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1337
static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1341
if (env->cp15.c15_cpar != value) {
1342
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
1344
env->cp15.c15_cpar = value;
1349
static const ARMCPRegInfo xscale_cp_reginfo[] = {
1350
{ .name = "XSCALE_CPAR",
1351
.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1352
.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1353
.writefn = xscale_cpar_write, },
1354
{ .name = "XSCALE_AUXCR",
1355
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1356
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1361
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1362
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
1363
* implementation of this implementation-defined space.
1364
* Ideally this should eventually disappear in favour of actually
1365
* implementing the correct behaviour for all cores.
1367
{ .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1368
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1369
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1374
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1375
/* Cache status: RAZ because we have no cache so it's always clean */
1376
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1377
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1382
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1383
/* We never have a a block transfer operation in progress */
1384
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1385
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1387
/* The cache ops themselves: these all NOP for QEMU */
1388
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1389
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1390
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1391
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1392
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1393
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1394
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1395
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1396
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1397
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1398
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1399
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1403
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1404
/* The cache test-and-clean instructions always return (1 << 30)
1405
* to indicate that there are no dirty cache lines.
1407
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1408
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1409
.resetvalue = (1 << 30) },
1410
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1411
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1412
.resetvalue = (1 << 30) },
1416
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1417
/* Ignore ReadBuffer accesses */
1418
{ .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1419
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1420
.access = PL1_RW, .resetvalue = 0,
1421
.type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1425
static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1428
CPUState *cs = CPU(arm_env_get_cpu(env));
1429
uint32_t mpidr = cs->cpu_index;
1430
/* We don't support setting cluster ID ([8..11])
1431
* so these bits always RAZ.
1433
if (arm_feature(env, ARM_FEATURE_V7MP)) {
1434
mpidr |= (1U << 31);
1435
/* Cores which are uniprocessor (non-coherent)
1436
* but still implement the MP extensions set
1437
* bit 30. (For instance, A9UP.) However we do
1438
* not currently model any of those cores.
1445
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1446
{ .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1447
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1451
static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1453
*value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1457
static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1459
env->cp15.c7_par_hi = value >> 32;
1460
env->cp15.c7_par = value;
1464
static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1466
env->cp15.c7_par_hi = 0;
1467
env->cp15.c7_par = 0;
1470
static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1473
*value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1477
static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1480
env->cp15.c2_base0_hi = value >> 32;
1481
env->cp15.c2_base0 = value;
1485
static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1488
/* Writes to the 64 bit format TTBRs may change the ASID */
1490
return ttbr064_raw_write(env, ri, value);
1493
static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1495
env->cp15.c2_base0_hi = 0;
1496
env->cp15.c2_base0 = 0;
1499
static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1502
*value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1506
static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1509
env->cp15.c2_base1_hi = value >> 32;
1510
env->cp15.c2_base1 = value;
1514
static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1516
env->cp15.c2_base1_hi = 0;
1517
env->cp15.c2_base1 = 0;
1520
static const ARMCPRegInfo lpae_cp_reginfo[] = {
1521
/* NOP AMAIR0/1: the override is because these clash with the rather
1522
* broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1524
{ .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1525
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1527
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1528
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1530
/* 64 bit access versions of the (dummy) debug registers */
1531
{ .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1532
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1533
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1534
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1535
{ .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1536
.access = PL1_RW, .type = ARM_CP_64BIT,
1537
.readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1538
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1539
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1540
.writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1541
.resetfn = ttbr064_reset },
1542
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1543
.access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1544
.writefn = ttbr164_write, .resetfn = ttbr164_reset },
1548
static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1550
CPREG_FIELD32(env, ri) = value & ~0x1f;
1554
static const ARMCPRegInfo trustzone_cp_reginfo[] = {
1555
/* Dummy implementations of registers; we don't enforce the
1556
* 'secure mode only' access checks. TODO: revisit as part of
1557
* proper fake-trustzone support.
1559
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
1560
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
1562
{ .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
1563
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sedbg),
1565
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
1566
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_nseac),
1568
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1569
.access = PL1_RW, .writefn = vbar_write,
1570
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
1572
{ .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
1573
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar),
1574
.writefn = vbar_write, .resetvalue = 0 },
1578
static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1581
*value = vfp_get_fpcr(env);
1585
static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1588
vfp_set_fpcr(env, value);
1592
static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1595
*value = vfp_get_fpsr(env);
1599
static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1602
vfp_set_fpsr(env, value);
1606
static const ARMCPRegInfo v8_cp_reginfo[] = {
1607
/* Minimal set of EL0-visible registers. This will need to be expanded
1608
* significantly for system emulation of AArch64 CPUs.
1610
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
1611
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1612
.access = PL0_RW, .type = ARM_CP_NZCV },
1613
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
1614
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1615
.access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1616
{ .name = "FPSR", .state = ARM_CP_STATE_AA64,
1617
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1618
.access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1619
/* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1620
* It will eventually need to have a CPU-specified reset value.
1622
{ .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1623
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1624
.access = PL0_R, .type = ARM_CP_CONST,
1625
.resetvalue = 0x80030003 },
1626
/* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1627
* For system mode the DZP bit here will need to be computed, not constant.
1629
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1630
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1631
.access = PL0_R, .type = ARM_CP_CONST,
1632
.resetvalue = 0x10 },
1636
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1638
env->cp15.c1_sys = value;
1639
/* ??? Lots of these bits are not implemented. */
1640
/* This may enable/disable the MMU, so do a TLB flush. */
1645
void register_cp_regs_for_features(ARMCPU *cpu)
1647
/* Register all the coprocessor registers based on feature bits */
1648
CPUARMState *env = &cpu->env;
1649
if (arm_feature(env, ARM_FEATURE_M)) {
1650
/* M profile has no coprocessor registers */
1654
define_arm_cp_regs(cpu, cp_reginfo);
1655
if (arm_feature(env, ARM_FEATURE_V6)) {
1656
/* The ID registers all have impdef reset values */
1657
ARMCPRegInfo v6_idregs[] = {
1658
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1659
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1660
.resetvalue = cpu->id_pfr0 },
1661
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1662
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1663
.resetvalue = cpu->id_pfr1 },
1664
{ .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1665
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1666
.resetvalue = cpu->id_dfr0 },
1667
{ .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1668
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1669
.resetvalue = cpu->id_afr0 },
1670
{ .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1671
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1672
.resetvalue = cpu->id_mmfr0 },
1673
{ .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1674
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1675
.resetvalue = cpu->id_mmfr1 },
1676
{ .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1677
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1678
.resetvalue = cpu->id_mmfr2 },
1679
{ .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1680
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1681
.resetvalue = cpu->id_mmfr3 },
1682
{ .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1683
.opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1684
.resetvalue = cpu->id_isar0 },
1685
{ .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1686
.opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1687
.resetvalue = cpu->id_isar1 },
1688
{ .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1689
.opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1690
.resetvalue = cpu->id_isar2 },
1691
{ .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1692
.opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1693
.resetvalue = cpu->id_isar3 },
1694
{ .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1695
.opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1696
.resetvalue = cpu->id_isar4 },
1697
{ .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1698
.opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1699
.resetvalue = cpu->id_isar5 },
1700
/* 6..7 are as yet unallocated and must RAZ */
1701
{ .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1702
.opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1704
{ .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1705
.opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1709
define_arm_cp_regs(cpu, v6_idregs);
1710
define_arm_cp_regs(cpu, v6_cp_reginfo);
1712
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1714
if (arm_feature(env, ARM_FEATURE_V6K)) {
1715
define_arm_cp_regs(cpu, v6k_cp_reginfo);
1717
if (arm_feature(env, ARM_FEATURE_V7)) {
1718
/* v7 performance monitor control register: same implementor
1719
* field as main ID register, and we implement no event counters.
1721
ARMCPRegInfo pmcr = {
1722
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1723
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1724
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1725
.readfn = pmreg_read, .writefn = pmcr_write,
1726
.raw_readfn = raw_read, .raw_writefn = raw_write,
1728
ARMCPRegInfo clidr = {
1729
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1730
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1732
define_one_arm_cp_reg(cpu, &pmcr);
1733
define_one_arm_cp_reg(cpu, &clidr);
1734
define_arm_cp_regs(cpu, v7_cp_reginfo);
1736
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1738
if (arm_feature(env, ARM_FEATURE_V8)) {
1739
define_arm_cp_regs(cpu, v8_cp_reginfo);
1741
if (arm_feature(env, ARM_FEATURE_MPU)) {
1742
/* These are the MPU registers prior to PMSAv6. Any new
1743
* PMSA core later than the ARM946 will require that we
1744
* implement the PMSAv6 or PMSAv7 registers, which are
1745
* completely different.
1747
assert(!arm_feature(env, ARM_FEATURE_V6));
1748
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1750
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1752
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1753
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1755
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1756
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1758
if (arm_feature(env, ARM_FEATURE_VAPA)) {
1759
define_arm_cp_regs(cpu, vapa_cp_reginfo);
1761
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1762
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1764
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1765
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1767
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1768
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1770
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1771
define_arm_cp_regs(cpu, omap_cp_reginfo);
1773
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1774
define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1776
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1777
define_arm_cp_regs(cpu, xscale_cp_reginfo);
1779
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1780
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1782
if (arm_feature(env, ARM_FEATURE_LPAE)) {
1783
define_arm_cp_regs(cpu, lpae_cp_reginfo);
1785
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
1786
define_arm_cp_regs(cpu, trustzone_cp_reginfo);
1788
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
1789
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
1790
* be read-only (ie write causes UNDEF exception).
1793
ARMCPRegInfo id_cp_reginfo[] = {
1794
/* Note that the MIDR isn't a simple constant register because
1795
* of the TI925 behaviour where writes to another register can
1796
* cause the MIDR value to change.
1798
* Unimplemented registers in the c15 0 0 0 space default to
1799
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1800
* and friends override accordingly.
1803
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1804
.access = PL1_R, .resetvalue = cpu->midr,
1805
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1806
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1807
.type = ARM_CP_OVERRIDE },
1809
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1810
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1812
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1813
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1815
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1816
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1817
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1819
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1820
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1822
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1823
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1825
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1826
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1828
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1829
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1831
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1832
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1835
ARMCPRegInfo crn0_wi_reginfo = {
1836
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1837
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1838
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
1840
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1841
arm_feature(env, ARM_FEATURE_STRONGARM)) {
1843
/* Register the blanket "writes ignored" value first to cover the
1844
* whole space. Then update the specific ID registers to allow write
1845
* access, so that they ignore writes rather than causing them to
1848
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1849
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1853
define_arm_cp_regs(cpu, id_cp_reginfo);
1856
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1857
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1860
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1861
ARMCPRegInfo auxcr = {
1862
.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1863
.access = PL1_RW, .type = ARM_CP_CONST,
1864
.resetvalue = cpu->reset_auxcr
1866
define_one_arm_cp_reg(cpu, &auxcr);
1869
/* Generic registers whose values depend on the implementation */
1871
ARMCPRegInfo sctlr = {
1872
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1873
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1874
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1875
.raw_writefn = raw_write,
1877
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1878
/* Normally we would always end the TB on an SCTLR write, but Linux
1879
* arch/arm/mach-pxa/sleep.S expects two instructions following
1880
* an MMU enable to execute from cache. Imitate this behaviour.
1882
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1884
define_one_arm_cp_reg(cpu, &sctlr);
1888
ARMCPU *cpu_arm_init(const char *cpu_model)
1893
oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1897
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1899
/* TODO this should be set centrally, once possible */
1900
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1905
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1907
CPUState *cs = CPU(cpu);
1908
CPUARMState *env = &cpu->env;
1910
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1911
gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1912
aarch64_fpu_gdb_set_reg,
1913
34, "aarch64-fpu.xml", 0);
1914
} else if (arm_feature(env, ARM_FEATURE_NEON)) {
1915
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1916
51, "arm-neon.xml", 0);
1917
} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1918
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1919
35, "arm-vfp3.xml", 0);
1920
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
1921
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1922
19, "arm-vfp.xml", 0);
1926
/* Sort alphabetically by type name, except for "any". */
1927
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1929
ObjectClass *class_a = (ObjectClass *)a;
1930
ObjectClass *class_b = (ObjectClass *)b;
1931
const char *name_a, *name_b;
1933
name_a = object_class_get_name(class_a);
1934
name_b = object_class_get_name(class_b);
1935
if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1937
} else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1940
return strcmp(name_a, name_b);
1944
static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1946
ObjectClass *oc = data;
1947
CPUListState *s = user_data;
1948
const char *typename;
1951
typename = object_class_get_name(oc);
1952
name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1953
(*s->cpu_fprintf)(s->file, " %s\n",
1958
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1962
.cpu_fprintf = cpu_fprintf,
1966
list = object_class_get_list(TYPE_ARM_CPU, false);
1967
list = g_slist_sort(list, arm_cpu_list_compare);
1968
(*cpu_fprintf)(f, "Available CPUs:\n");
1969
g_slist_foreach(list, arm_cpu_list_entry, &s);
1972
/* The 'host' CPU type is dynamically registered only if KVM is
1973
* enabled, so we have to special-case it here:
1975
(*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1979
static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1981
ObjectClass *oc = data;
1982
CpuDefinitionInfoList **cpu_list = user_data;
1983
CpuDefinitionInfoList *entry;
1984
CpuDefinitionInfo *info;
1985
const char *typename;
1987
typename = object_class_get_name(oc);
1988
info = g_malloc0(sizeof(*info));
1989
info->name = g_strndup(typename,
1990
strlen(typename) - strlen("-" TYPE_ARM_CPU));
1992
entry = g_malloc0(sizeof(*entry));
1993
entry->value = info;
1994
entry->next = *cpu_list;
1998
CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2000
CpuDefinitionInfoList *cpu_list = NULL;
2003
list = object_class_get_list(TYPE_ARM_CPU, false);
2004
g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2010
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2011
void *opaque, int state,
2012
int crm, int opc1, int opc2)
2014
/* Private utility function for define_one_arm_cp_reg_with_opaque():
2015
* add a single reginfo struct to the hash table.
2017
uint32_t *key = g_new(uint32_t, 1);
2018
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2019
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2020
if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2021
/* The AArch32 view of a shared register sees the lower 32 bits
2022
* of a 64 bit backing field. It is not migratable as the AArch64
2023
* view handles that. AArch64 also handles reset.
2024
* We assume it is a cp15 register.
2027
r2->type |= ARM_CP_NO_MIGRATE;
2028
r2->resetfn = arm_cp_reset_ignore;
2029
#ifdef HOST_WORDS_BIGENDIAN
2030
if (r2->fieldoffset) {
2031
r2->fieldoffset += sizeof(uint32_t);
2035
if (state == ARM_CP_STATE_AA64) {
2036
/* To allow abbreviation of ARMCPRegInfo
2037
* definitions, we treat cp == 0 as equivalent to
2038
* the value for "standard guest-visible sysreg".
2041
r2->cp = CP_REG_ARM64_SYSREG_CP;
2043
*key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2044
r2->opc0, opc1, opc2);
2046
*key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2049
r2->opaque = opaque;
2051
/* Make sure reginfo passed to helpers for wildcarded regs
2052
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2057
/* By convention, for wildcarded registers only the first
2058
* entry is used for migration; the others are marked as
2059
* NO_MIGRATE so we don't try to transfer the register
2060
* multiple times. Special registers (ie NOP/WFI) are
2063
if ((r->type & ARM_CP_SPECIAL) ||
2064
((r->crm == CP_ANY) && crm != 0) ||
2065
((r->opc1 == CP_ANY) && opc1 != 0) ||
2066
((r->opc2 == CP_ANY) && opc2 != 0)) {
2067
r2->type |= ARM_CP_NO_MIGRATE;
2070
/* Overriding of an existing definition must be explicitly
2073
if (!(r->type & ARM_CP_OVERRIDE)) {
2074
ARMCPRegInfo *oldreg;
2075
oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2076
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2077
fprintf(stderr, "Register redefined: cp=%d %d bit "
2078
"crn=%d crm=%d opc1=%d opc2=%d, "
2079
"was %s, now %s\n", r2->cp, 32 + 32 * is64,
2080
r2->crn, r2->crm, r2->opc1, r2->opc2,
2081
oldreg->name, r2->name);
2082
g_assert_not_reached();
2085
g_hash_table_insert(cpu->cp_regs, key, r2);
2089
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2090
const ARMCPRegInfo *r, void *opaque)
2092
/* Define implementations of coprocessor registers.
2093
* We store these in a hashtable because typically
2094
* there are less than 150 registers in a space which
2095
* is 16*16*16*8*8 = 262144 in size.
2096
* Wildcarding is supported for the crm, opc1 and opc2 fields.
2097
* If a register is defined twice then the second definition is
2098
* used, so this can be used to define some generic registers and
2099
* then override them with implementation specific variations.
2100
* At least one of the original and the second definition should
2101
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2102
* against accidental use.
2104
* The state field defines whether the register is to be
2105
* visible in the AArch32 or AArch64 execution state. If the
2106
* state is set to ARM_CP_STATE_BOTH then we synthesise a
2107
* reginfo structure for the AArch32 view, which sees the lower
2108
* 32 bits of the 64 bit register.
2110
* Only registers visible in AArch64 may set r->opc0; opc0 cannot
2111
* be wildcarded. AArch64 registers are always considered to be 64
2112
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2113
* the register, if any.
2115
int crm, opc1, opc2, state;
2116
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2117
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2118
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2119
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2120
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2121
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2122
/* 64 bit registers have only CRm and Opc1 fields */
2123
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2124
/* op0 only exists in the AArch64 encodings */
2125
assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2126
/* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2127
assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2128
/* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2129
* encodes a minimum access level for the register. We roll this
2130
* runtime check into our general permission check code, so check
2131
* here that the reginfo's specified permissions are strict enough
2132
* to encompass the generic architectural permission check.
2134
if (r->state != ARM_CP_STATE_AA32) {
2137
case 0: case 1: case 2:
2150
/* unallocated encoding, so not possible */
2158
/* min_EL EL1, secure mode only (we don't check the latter) */
2162
/* broken reginfo with out-of-range opc1 */
2166
/* assert our permissions are not too lax (stricter is fine) */
2167
assert((r->access & ~mask) == 0);
2170
/* Check that the register definition has enough info to handle
2171
* reads and writes if they are permitted.
2173
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2174
if (r->access & PL3_R) {
2175
assert(r->fieldoffset || r->readfn);
2177
if (r->access & PL3_W) {
2178
assert(r->fieldoffset || r->writefn);
2181
/* Bad type field probably means missing sentinel at end of reg list */
2182
assert(cptype_valid(r->type));
2183
for (crm = crmmin; crm <= crmmax; crm++) {
2184
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2185
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2186
for (state = ARM_CP_STATE_AA32;
2187
state <= ARM_CP_STATE_AA64; state++) {
2188
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2191
add_cpreg_to_hashtable(cpu, r, opaque, state,
2199
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2200
const ARMCPRegInfo *regs, void *opaque)
2202
/* Define a whole list of registers */
2203
const ARMCPRegInfo *r;
2204
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2205
define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2209
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2211
return g_hash_table_lookup(cpregs, &encoded_cp);
2214
int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2217
/* Helper coprocessor write function for write-ignore registers */
2221
int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2223
/* Helper coprocessor write function for read-as-zero registers */
2228
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2230
/* Helper coprocessor reset function for do-nothing-on-reset registers */
2233
static int bad_mode_switch(CPUARMState *env, int mode)
2235
/* Return true if it is not valid for us to switch to
2236
* this CPU mode (ie all the UNPREDICTABLE cases in
2237
* the ARM ARM CPSRWriteByInstr pseudocode).
2240
case ARM_CPU_MODE_USR:
2241
case ARM_CPU_MODE_SYS:
2242
case ARM_CPU_MODE_SVC:
2243
case ARM_CPU_MODE_ABT:
2244
case ARM_CPU_MODE_UND:
2245
case ARM_CPU_MODE_IRQ:
2246
case ARM_CPU_MODE_FIQ:
2253
uint32_t cpsr_read(CPUARMState *env)
2256
ZF = (env->ZF == 0);
2257
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2258
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2259
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2260
| ((env->condexec_bits & 0xfc) << 8)
2264
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2266
if (mask & CPSR_NZCV) {
2267
env->ZF = (~val) & CPSR_Z;
2269
env->CF = (val >> 29) & 1;
2270
env->VF = (val << 3) & 0x80000000;
2273
env->QF = ((val & CPSR_Q) != 0);
2275
env->thumb = ((val & CPSR_T) != 0);
2276
if (mask & CPSR_IT_0_1) {
2277
env->condexec_bits &= ~3;
2278
env->condexec_bits |= (val >> 25) & 3;
2280
if (mask & CPSR_IT_2_7) {
2281
env->condexec_bits &= 3;
2282
env->condexec_bits |= (val >> 8) & 0xfc;
2284
if (mask & CPSR_GE) {
2285
env->GE = (val >> 16) & 0xf;
2288
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2289
if (bad_mode_switch(env, val & CPSR_M)) {
2290
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2291
* We choose to ignore the attempt and leave the CPSR M field
2296
switch_mode(env, val & CPSR_M);
2299
mask &= ~CACHED_CPSR_BITS;
2300
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2303
/* Sign/zero extend */
2304
uint32_t HELPER(sxtb16)(uint32_t x)
2307
res = (uint16_t)(int8_t)x;
2308
res |= (uint32_t)(int8_t)(x >> 16) << 16;
2312
uint32_t HELPER(uxtb16)(uint32_t x)
2315
res = (uint16_t)(uint8_t)x;
2316
res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2320
uint32_t HELPER(clz)(uint32_t x)
2325
int32_t HELPER(sdiv)(int32_t num, int32_t den)
2329
if (num == INT_MIN && den == -1)
2334
uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2341
uint32_t HELPER(rbit)(uint32_t x)
2343
x = ((x & 0xff000000) >> 24)
2344
| ((x & 0x00ff0000) >> 8)
2345
| ((x & 0x0000ff00) << 8)
2346
| ((x & 0x000000ff) << 24);
2347
x = ((x & 0xf0f0f0f0) >> 4)
2348
| ((x & 0x0f0f0f0f) << 4);
2349
x = ((x & 0x88888888) >> 3)
2350
| ((x & 0x44444444) >> 1)
2351
| ((x & 0x22222222) << 1)
2352
| ((x & 0x11111111) << 3);
2356
#if defined(CONFIG_USER_ONLY)
2358
void arm_cpu_do_interrupt(CPUState *cs)
2360
ARMCPU *cpu = ARM_CPU(cs);
2361
CPUARMState *env = &cpu->env;
2363
env->exception_index = -1;
2366
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2370
env->exception_index = EXCP_PREFETCH_ABORT;
2371
env->cp15.c6_insn = address;
2373
env->exception_index = EXCP_DATA_ABORT;
2374
env->cp15.c6_data = address;
2379
/* These should probably raise undefined insn exceptions. */
2380
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2382
cpu_abort(env, "v7m_mrs %d\n", reg);
2385
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2387
cpu_abort(env, "v7m_mrs %d\n", reg);
2391
void switch_mode(CPUARMState *env, int mode)
2393
if (mode != ARM_CPU_MODE_USR)
2394
cpu_abort(env, "Tried to switch out of user mode\n");
2397
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2399
cpu_abort(env, "banked r13 write\n");
2402
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2404
cpu_abort(env, "banked r13 read\n");
2410
/* Map CPU modes onto saved register banks. */
2411
int bank_number(int mode)
2414
case ARM_CPU_MODE_USR:
2415
case ARM_CPU_MODE_SYS:
2417
case ARM_CPU_MODE_SVC:
2419
case ARM_CPU_MODE_ABT:
2421
case ARM_CPU_MODE_UND:
2423
case ARM_CPU_MODE_IRQ:
2425
case ARM_CPU_MODE_FIQ:
2427
case ARM_CPU_MODE_SMC:
2430
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2433
void switch_mode(CPUARMState *env, int mode)
2438
old_mode = env->uncached_cpsr & CPSR_M;
2439
if (mode == old_mode)
2442
if (old_mode == ARM_CPU_MODE_FIQ) {
2443
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2444
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2445
} else if (mode == ARM_CPU_MODE_FIQ) {
2446
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2447
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2450
i = bank_number(old_mode);
2451
env->banked_r13[i] = env->regs[13];
2452
env->banked_r14[i] = env->regs[14];
2453
env->banked_spsr[i] = env->spsr;
2455
i = bank_number(mode);
2456
env->regs[13] = env->banked_r13[i];
2457
env->regs[14] = env->banked_r14[i];
2458
env->spsr = env->banked_spsr[i];
2461
static void v7m_push(CPUARMState *env, uint32_t val)
2464
stl_phys(env->regs[13], val);
2467
static uint32_t v7m_pop(CPUARMState *env)
2470
val = ldl_phys(env->regs[13]);
2475
/* Switch to V7M main or process stack pointer. */
2476
static void switch_v7m_sp(CPUARMState *env, int process)
2479
if (env->v7m.current_sp != process) {
2480
tmp = env->v7m.other_sp;
2481
env->v7m.other_sp = env->regs[13];
2482
env->regs[13] = tmp;
2483
env->v7m.current_sp = process;
2487
static void do_v7m_exception_exit(CPUARMState *env)
2492
type = env->regs[15];
2493
if (env->v7m.exception != 0)
2494
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2496
/* Switch to the target stack. */
2497
switch_v7m_sp(env, (type & 4) != 0);
2498
/* Pop registers. */
2499
env->regs[0] = v7m_pop(env);
2500
env->regs[1] = v7m_pop(env);
2501
env->regs[2] = v7m_pop(env);
2502
env->regs[3] = v7m_pop(env);
2503
env->regs[12] = v7m_pop(env);
2504
env->regs[14] = v7m_pop(env);
2505
env->regs[15] = v7m_pop(env);
2506
xpsr = v7m_pop(env);
2507
xpsr_write(env, xpsr, 0xfffffdff);
2508
/* Undo stack alignment. */
2511
/* ??? The exception return type specifies Thread/Handler mode. However
2512
this is also implied by the xPSR value. Not sure what to do
2513
if there is a mismatch. */
2514
/* ??? Likewise for mismatches between the CONTROL register and the stack
2518
/* Exception names for debug logging; note that not all of these
2519
* precisely correspond to architectural exceptions.
2521
static const char * const excnames[] = {
2522
[EXCP_UDEF] = "Undefined Instruction",
2524
[EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2525
[EXCP_DATA_ABORT] = "Data Abort",
2528
[EXCP_BKPT] = "Breakpoint",
2529
[EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2530
[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2531
[EXCP_STREX] = "QEMU intercept of STREX",
2534
static inline void arm_log_exception(int idx)
2536
if (qemu_loglevel_mask(CPU_LOG_INT)) {
2537
const char *exc = NULL;
2539
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2540
exc = excnames[idx];
2545
qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2549
void arm_v7m_cpu_do_interrupt(CPUState *cs)
2551
ARMCPU *cpu = ARM_CPU(cs);
2552
CPUARMState *env = &cpu->env;
2553
uint32_t xpsr = xpsr_read(env);
2557
arm_log_exception(env->exception_index);
2560
if (env->v7m.current_sp)
2562
if (env->v7m.exception == 0)
2565
/* For exceptions we just mark as pending on the NVIC, and let that
2567
/* TODO: Need to escalate if the current priority is higher than the
2568
one we're raising. */
2569
switch (env->exception_index) {
2571
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2574
/* The PC already points to the next instruction. */
2575
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2577
case EXCP_PREFETCH_ABORT:
2578
case EXCP_DATA_ABORT:
2579
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2582
if (semihosting_enabled) {
2584
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2587
env->regs[0] = do_arm_semihosting(env);
2588
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2592
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2595
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2597
case EXCP_EXCEPTION_EXIT:
2598
do_v7m_exception_exit(env);
2601
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2602
return; /* Never happens. Keep compiler happy. */
2605
/* Align stack pointer. */
2606
/* ??? Should only do this if Configuration Control Register
2607
STACKALIGN bit is set. */
2608
if (env->regs[13] & 4) {
2612
/* Switch to the handler mode. */
2613
v7m_push(env, xpsr);
2614
v7m_push(env, env->regs[15]);
2615
v7m_push(env, env->regs[14]);
2616
v7m_push(env, env->regs[12]);
2617
v7m_push(env, env->regs[3]);
2618
v7m_push(env, env->regs[2]);
2619
v7m_push(env, env->regs[1]);
2620
v7m_push(env, env->regs[0]);
2621
switch_v7m_sp(env, 0);
2623
env->condexec_bits = 0;
2625
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2626
env->regs[15] = addr & 0xfffffffe;
2627
env->thumb = addr & 1;
2630
/* Handle a CPU exception. */
2631
void arm_cpu_do_interrupt(CPUState *cs)
2633
ARMCPU *cpu = ARM_CPU(cs);
2634
CPUARMState *env = &cpu->env;
2642
arm_log_exception(env->exception_index);
2644
/* TODO: Vectored interrupt controller. */
2645
switch (env->exception_index) {
2647
new_mode = ARM_CPU_MODE_UND;
2656
if (semihosting_enabled) {
2657
/* Check for semihosting interrupt. */
2659
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2662
mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2665
/* Only intercept calls from privileged modes, to provide some
2666
semblance of security. */
2667
if (((mask == 0x123456 && !env->thumb)
2668
|| (mask == 0xab && env->thumb))
2669
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2670
env->regs[0] = do_arm_semihosting(env);
2671
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2675
new_mode = ARM_CPU_MODE_SVC;
2678
/* The PC already points to the next instruction. */
2682
/* See if this is a semihosting syscall. */
2683
if (env->thumb && semihosting_enabled) {
2684
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2686
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2688
env->regs[0] = do_arm_semihosting(env);
2689
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2693
env->cp15.c5_insn = 2;
2694
/* Fall through to prefetch abort. */
2695
case EXCP_PREFETCH_ABORT:
2696
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2697
env->cp15.c5_insn, env->cp15.c6_insn);
2698
new_mode = ARM_CPU_MODE_ABT;
2700
mask = CPSR_A | CPSR_I;
2703
case EXCP_DATA_ABORT:
2704
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2705
env->cp15.c5_data, env->cp15.c6_data);
2706
new_mode = ARM_CPU_MODE_ABT;
2708
mask = CPSR_A | CPSR_I;
2712
new_mode = ARM_CPU_MODE_IRQ;
2714
/* Disable IRQ and imprecise data aborts. */
2715
mask = CPSR_A | CPSR_I;
2719
new_mode = ARM_CPU_MODE_FIQ;
2721
/* Disable FIQ, IRQ and imprecise data aborts. */
2722
mask = CPSR_A | CPSR_I | CPSR_F;
2726
if (semihosting_enabled) {
2727
cpu_abort(env, "SMC handling under semihosting not implemented\n");
2730
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2731
env->cp15.c1_scr &= ~1;
2733
offset = env->thumb ? 2 : 0;
2734
new_mode = ARM_CPU_MODE_SMC;
2736
mask = CPSR_A | CPSR_I | CPSR_F;
2739
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2740
return; /* Never happens. Keep compiler happy. */
2742
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
2743
if (new_mode == ARM_CPU_MODE_SMC ||
2744
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
2745
addr += env->cp15.c12_mvbar;
2747
if (env->cp15.c1_sys & (1 << 13)) {
2750
addr += env->cp15.c12_vbar;
2755
if (env->cp15.c1_sys & (1 << 13)) {
2759
switch_mode (env, new_mode);
2760
env->spsr = cpsr_read(env);
2761
/* Clear IT bits. */
2762
env->condexec_bits = 0;
2763
/* Switch to the new mode, and to the correct instruction set. */
2764
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2765
env->uncached_cpsr |= mask;
2766
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2767
* and we should just guard the thumb mode on V4 */
2768
if (arm_feature(env, ARM_FEATURE_V4T)) {
2769
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2771
env->regs[14] = env->regs[15] + offset;
2772
env->regs[15] = addr;
2773
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2776
/* Check section/page access permissions.
2777
Returns the page protection flags, or zero if the access is not
2779
static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2780
int access_type, int is_user)
2784
if (domain_prot == 3) {
2785
return PAGE_READ | PAGE_WRITE;
2788
if (access_type == 1)
2791
prot_ro = PAGE_READ;
2795
if (access_type == 1)
2797
switch ((env->cp15.c1_sys >> 8) & 3) {
2799
return is_user ? 0 : PAGE_READ;
2806
return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2811
return PAGE_READ | PAGE_WRITE;
2813
return PAGE_READ | PAGE_WRITE;
2814
case 4: /* Reserved. */
2817
return is_user ? 0 : prot_ro;
2821
if (!arm_feature (env, ARM_FEATURE_V6K))
2829
static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2833
if (address & env->cp15.c2_mask)
2834
table = env->cp15.c2_base1 & 0xffffc000;
2836
table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2838
table |= (address >> 18) & 0x3ffc;
2842
static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2843
int is_user, hwaddr *phys_ptr,
2844
int *prot, target_ulong *page_size)
2855
/* Pagetable walk. */
2856
/* Lookup l1 descriptor. */
2857
table = get_level1_table_address(env, address);
2858
desc = ldl_phys(table);
2860
domain = (desc >> 5) & 0x0f;
2861
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2863
/* Section translation fault. */
2867
if (domain_prot == 0 || domain_prot == 2) {
2869
code = 9; /* Section domain fault. */
2871
code = 11; /* Page domain fault. */
2876
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2877
ap = (desc >> 10) & 3;
2879
*page_size = 1024 * 1024;
2881
/* Lookup l2 entry. */
2883
/* Coarse pagetable. */
2884
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2886
/* Fine pagetable. */
2887
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2889
desc = ldl_phys(table);
2891
case 0: /* Page translation fault. */
2894
case 1: /* 64k page. */
2895
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2896
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2897
*page_size = 0x10000;
2899
case 2: /* 4k page. */
2900
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2901
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2902
*page_size = 0x1000;
2904
case 3: /* 1k page. */
2906
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2907
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2909
/* Page translation fault. */
2914
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2916
ap = (desc >> 4) & 3;
2920
/* Never happens, but compiler isn't smart enough to tell. */
2925
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
2927
/* Access permission fault. */
2931
*phys_ptr = phys_addr;
2934
return code | (domain << 4);
2937
static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2938
int is_user, hwaddr *phys_ptr,
2939
int *prot, target_ulong *page_size)
2952
/* Pagetable walk. */
2953
/* Lookup l1 descriptor. */
2954
table = get_level1_table_address(env, address);
2955
desc = ldl_phys(table);
2957
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2958
/* Section translation fault, or attempt to use the encoding
2959
* which is Reserved on implementations without PXN.
2964
if ((type == 1) || !(desc & (1 << 18))) {
2965
/* Page or Section. */
2966
domain = (desc >> 5) & 0x0f;
2968
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2969
if (domain_prot == 0 || domain_prot == 2) {
2971
code = 9; /* Section domain fault. */
2973
code = 11; /* Page domain fault. */
2978
if (desc & (1 << 18)) {
2980
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2981
*page_size = 0x1000000;
2984
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2985
*page_size = 0x100000;
2987
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2988
xn = desc & (1 << 4);
2992
if (arm_feature(env, ARM_FEATURE_PXN)) {
2993
pxn = (desc >> 2) & 1;
2995
/* Lookup l2 entry. */
2996
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2997
desc = ldl_phys(table);
2998
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3000
case 0: /* Page translation fault. */
3003
case 1: /* 64k page. */
3004
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3005
xn = desc & (1 << 15);
3006
*page_size = 0x10000;
3008
case 2: case 3: /* 4k page. */
3009
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3011
*page_size = 0x1000;
3014
/* Never happens, but compiler isn't smart enough to tell. */
3019
if (domain_prot == 3) {
3020
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3022
if (pxn && !is_user) {
3025
if (xn && access_type == 2)
3028
/* The simplified model uses AP[0] as an access control bit. */
3029
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
3030
/* Access flag fault. */
3031
code = (code == 15) ? 6 : 3;
3034
*prot = check_ap(env, ap, domain_prot, access_type, is_user);
3036
/* Access permission fault. */
3043
*phys_ptr = phys_addr;
3046
return code | (domain << 4);
3049
/* Fault type for long-descriptor MMU fault reporting; this corresponds
3050
* to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3053
translation_fault = 1,
3055
permission_fault = 3,
3058
static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3059
int access_type, int is_user,
3060
hwaddr *phys_ptr, int *prot,
3061
target_ulong *page_size_ptr)
3063
/* Read an LPAE long-descriptor translation table. */
3064
MMUFaultType fault_type = translation_fault;
3072
uint32_t tableattrs;
3073
target_ulong page_size;
3076
/* Determine whether this address is in the region controlled by
3077
* TTBR0 or TTBR1 (or if it is in neither region and should fault).
3078
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
3079
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3081
uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3082
uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3083
if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3084
/* there is a ttbr0 region and we are in it (high bits all zero) */
3086
} else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3087
/* there is a ttbr1 region and we are in it (high bits all one) */
3090
/* ttbr0 region is "everything not in the ttbr1 region" */
3093
/* ttbr1 region is "everything not in the ttbr0 region" */
3096
/* in the gap between the two regions, this is a Translation fault */
3097
fault_type = translation_fault;
3101
/* Note that QEMU ignores shareability and cacheability attributes,
3102
* so we don't need to do anything with the SH, ORGN, IRGN fields
3103
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3104
* ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3105
* implement any ASID-like capability so we can ignore it (instead
3106
* we will always flush the TLB any time the ASID is changed).
3108
if (ttbr_select == 0) {
3109
ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
3110
epd = extract32(env->cp15.c2_control, 7, 1);
3113
ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
3114
epd = extract32(env->cp15.c2_control, 23, 1);
3119
/* Translation table walk disabled => Translation fault on TLB miss */
3123
/* If the region is small enough we will skip straight to a 2nd level
3124
* lookup. This affects the number of bits of the address used in
3125
* combination with the TTBR to find the first descriptor. ('n' here
3126
* matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3127
* from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3136
/* Clear the vaddr bits which aren't part of the within-region address,
3137
* so that we don't have to special case things when calculating the
3138
* first descriptor address.
3140
address &= (0xffffffffU >> tsz);
3142
/* Now we can extract the actual base address from the TTBR */
3143
descaddr = extract64(ttbr, 0, 40);
3144
descaddr &= ~((1ULL << n) - 1);
3148
uint64_t descriptor;
3150
descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3151
descriptor = ldq_phys(descaddr);
3152
if (!(descriptor & 1) ||
3153
(!(descriptor & 2) && (level == 3))) {
3154
/* Invalid, or the Reserved level 3 encoding */
3157
descaddr = descriptor & 0xfffffff000ULL;
3159
if ((descriptor & 2) && (level < 3)) {
3160
/* Table entry. The top five bits are attributes which may
3161
* propagate down through lower levels of the table (and
3162
* which are all arranged so that 0 means "no effect", so
3163
* we can gather them up by ORing in the bits at each level).
3165
tableattrs |= extract64(descriptor, 59, 5);
3169
/* Block entry at level 1 or 2, or page entry at level 3.
3170
* These are basically the same thing, although the number
3171
* of bits we pull in from the vaddr varies.
3173
page_size = (1 << (39 - (9 * level)));
3174
descaddr |= (address & (page_size - 1));
3175
/* Extract attributes from the descriptor and merge with table attrs */
3176
attrs = extract64(descriptor, 2, 10)
3177
| (extract64(descriptor, 52, 12) << 10);
3178
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3179
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3180
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3181
* means "force PL1 access only", which means forcing AP[1] to 0.
3183
if (extract32(tableattrs, 2, 1)) {
3186
/* Since we're always in the Non-secure state, NSTable is ignored. */
3189
/* Here descaddr is the final physical address, and attributes
3192
fault_type = access_fault;
3193
if ((attrs & (1 << 8)) == 0) {
3197
fault_type = permission_fault;
3198
if (is_user && !(attrs & (1 << 4))) {
3199
/* Unprivileged access not enabled */
3202
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3203
if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3205
if (access_type == 2) {
3208
*prot &= ~PAGE_EXEC;
3210
if (attrs & (1 << 5)) {
3211
/* Write access forbidden */
3212
if (access_type == 1) {
3215
*prot &= ~PAGE_WRITE;
3218
*phys_ptr = descaddr;
3219
*page_size_ptr = page_size;
3223
/* Long-descriptor format IFSR/DFSR value */
3224
return (1 << 9) | (fault_type << 2) | level;
3227
static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3228
int access_type, int is_user,
3229
hwaddr *phys_ptr, int *prot)
3235
*phys_ptr = address;
3236
for (n = 7; n >= 0; n--) {
3237
base = env->cp15.c6_region[n];
3238
if ((base & 1) == 0)
3240
mask = 1 << ((base >> 1) & 0x1f);
3241
/* Keep this shift separate from the above to avoid an
3242
(undefined) << 32. */
3243
mask = (mask << 1) - 1;
3244
if (((base ^ address) & ~mask) == 0)
3250
if (access_type == 2) {
3251
mask = env->cp15.c5_insn;
3253
mask = env->cp15.c5_data;
3255
mask = (mask >> (n * 4)) & 0xf;
3262
*prot = PAGE_READ | PAGE_WRITE;
3267
*prot |= PAGE_WRITE;
3270
*prot = PAGE_READ | PAGE_WRITE;
3281
/* Bad permission. */
3288
/* get_phys_addr - get the physical address for this virtual address
3290
* Find the physical address corresponding to the given virtual address,
3291
* by doing a translation table walk on MMU based systems or using the
3292
* MPU state on MPU based systems.
3294
* Returns 0 if the translation was successful. Otherwise, phys_ptr,
3295
* prot and page_size are not filled in, and the return value provides
3296
* information on why the translation aborted, in the format of a
3297
* DFSR/IFSR fault register, with the following caveats:
3298
* * we honour the short vs long DFSR format differences.
3299
* * the WnR bit is never set (the caller must do this).
3300
* * for MPU based systems we don't bother to return a full FSR format
3304
* @address: virtual address to get physical address for
3305
* @access_type: 0 for read, 1 for write, 2 for execute
3306
* @is_user: 0 for privileged access, 1 for user
3307
* @phys_ptr: set to the physical address corresponding to the virtual address
3308
* @prot: set to the permissions for the page containing phys_ptr
3309
* @page_size: set to the size of the page containing phys_ptr
3311
static inline int get_phys_addr(CPUARMState *env, uint32_t address,
3312
int access_type, int is_user,
3313
hwaddr *phys_ptr, int *prot,
3314
target_ulong *page_size)
3316
/* Fast Context Switch Extension. */
3317
if (address < 0x02000000)
3318
address += env->cp15.c13_fcse;
3320
if ((env->cp15.c1_sys & 1) == 0) {
3321
/* MMU/MPU disabled. */
3322
*phys_ptr = address;
3323
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3324
*page_size = TARGET_PAGE_SIZE;
3326
} else if (arm_feature(env, ARM_FEATURE_MPU)) {
3327
*page_size = TARGET_PAGE_SIZE;
3328
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3330
} else if (extended_addresses_enabled(env)) {
3331
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3333
} else if (env->cp15.c1_sys & (1 << 23)) {
3334
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3337
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3342
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
3343
int access_type, int mmu_idx)
3346
target_ulong page_size;
3350
is_user = mmu_idx == MMU_USER_IDX;
3351
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3354
/* Map a single [sub]page. */
3355
phys_addr &= ~(hwaddr)0x3ff;
3356
address &= ~(uint32_t)0x3ff;
3357
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
3361
if (access_type == 2) {
3362
env->cp15.c5_insn = ret;
3363
env->cp15.c6_insn = address;
3364
env->exception_index = EXCP_PREFETCH_ABORT;
3366
env->cp15.c5_data = ret;
3367
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3368
env->cp15.c5_data |= (1 << 11);
3369
env->cp15.c6_data = address;
3370
env->exception_index = EXCP_DATA_ABORT;
3375
hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3377
ARMCPU *cpu = ARM_CPU(cs);
3379
target_ulong page_size;
3383
ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3392
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3394
if ((env->uncached_cpsr & CPSR_M) == mode) {
3395
env->regs[13] = val;
3397
env->banked_r13[bank_number(mode)] = val;
3401
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3403
if ((env->uncached_cpsr & CPSR_M) == mode) {
3404
return env->regs[13];
3406
return env->banked_r13[bank_number(mode)];
3410
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3414
return xpsr_read(env) & 0xf8000000;
3416
return xpsr_read(env) & 0xf80001ff;
3418
return xpsr_read(env) & 0xff00fc00;
3420
return xpsr_read(env) & 0xff00fdff;
3422
return xpsr_read(env) & 0x000001ff;
3424
return xpsr_read(env) & 0x0700fc00;
3426
return xpsr_read(env) & 0x0700edff;
3428
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3430
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3431
case 16: /* PRIMASK */
3432
return (env->uncached_cpsr & CPSR_I) != 0;
3433
case 17: /* BASEPRI */
3434
case 18: /* BASEPRI_MAX */
3435
return env->v7m.basepri;
3436
case 19: /* FAULTMASK */
3437
return (env->uncached_cpsr & CPSR_F) != 0;
3438
case 20: /* CONTROL */
3439
return env->v7m.control;
3441
/* ??? For debugging only. */
3442
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3447
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3451
xpsr_write(env, val, 0xf8000000);
3454
xpsr_write(env, val, 0xf8000000);
3457
xpsr_write(env, val, 0xfe00fc00);
3460
xpsr_write(env, val, 0xfe00fc00);
3463
/* IPSR bits are readonly. */
3466
xpsr_write(env, val, 0x0600fc00);
3469
xpsr_write(env, val, 0x0600fc00);
3472
if (env->v7m.current_sp)
3473
env->v7m.other_sp = val;
3475
env->regs[13] = val;
3478
if (env->v7m.current_sp)
3479
env->regs[13] = val;
3481
env->v7m.other_sp = val;
3483
case 16: /* PRIMASK */
3485
env->uncached_cpsr |= CPSR_I;
3487
env->uncached_cpsr &= ~CPSR_I;
3489
case 17: /* BASEPRI */
3490
env->v7m.basepri = val & 0xff;
3492
case 18: /* BASEPRI_MAX */
3494
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3495
env->v7m.basepri = val;
3497
case 19: /* FAULTMASK */
3499
env->uncached_cpsr |= CPSR_F;
3501
env->uncached_cpsr &= ~CPSR_F;
3503
case 20: /* CONTROL */
3504
env->v7m.control = val & 3;
3505
switch_v7m_sp(env, (val & 2) != 0);
3508
/* ??? For debugging only. */
3509
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3516
/* Note that signed overflow is undefined in C. The following routines are
3517
careful to use unsigned types where modulo arithmetic is required.
3518
Failure to do so _will_ break on newer gcc. */
3520
/* Signed saturating arithmetic. */
3522
/* Perform 16-bit signed saturating addition. */
3523
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3528
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3537
/* Perform 8-bit signed saturating addition. */
3538
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3543
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3552
/* Perform 16-bit signed saturating subtraction. */
3553
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3558
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3567
/* Perform 8-bit signed saturating subtraction. */
3568
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3573
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3582
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3583
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3584
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3585
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3588
#include "op_addsub.h"
3590
/* Unsigned saturating arithmetic. */
3591
static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3600
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3608
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3617
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3625
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3626
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3627
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3628
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3631
#include "op_addsub.h"
3633
/* Signed modulo arithmetic. */
3634
#define SARITH16(a, b, n, op) do { \
3636
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3637
RESULT(sum, n, 16); \
3639
ge |= 3 << (n * 2); \
3642
#define SARITH8(a, b, n, op) do { \
3644
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3645
RESULT(sum, n, 8); \
3651
#define ADD16(a, b, n) SARITH16(a, b, n, +)
3652
#define SUB16(a, b, n) SARITH16(a, b, n, -)
3653
#define ADD8(a, b, n) SARITH8(a, b, n, +)
3654
#define SUB8(a, b, n) SARITH8(a, b, n, -)
3658
#include "op_addsub.h"
3660
/* Unsigned modulo arithmetic. */
3661
#define ADD16(a, b, n) do { \
3663
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3664
RESULT(sum, n, 16); \
3665
if ((sum >> 16) == 1) \
3666
ge |= 3 << (n * 2); \
3669
#define ADD8(a, b, n) do { \
3671
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3672
RESULT(sum, n, 8); \
3673
if ((sum >> 8) == 1) \
3677
#define SUB16(a, b, n) do { \
3679
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3680
RESULT(sum, n, 16); \
3681
if ((sum >> 16) == 0) \
3682
ge |= 3 << (n * 2); \
3685
#define SUB8(a, b, n) do { \
3687
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3688
RESULT(sum, n, 8); \
3689
if ((sum >> 8) == 0) \
3696
#include "op_addsub.h"
3698
/* Halved signed arithmetic. */
3699
#define ADD16(a, b, n) \
3700
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3701
#define SUB16(a, b, n) \
3702
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3703
#define ADD8(a, b, n) \
3704
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3705
#define SUB8(a, b, n) \
3706
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3709
#include "op_addsub.h"
3711
/* Halved unsigned arithmetic. */
3712
#define ADD16(a, b, n) \
3713
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3714
#define SUB16(a, b, n) \
3715
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3716
#define ADD8(a, b, n) \
3717
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3718
#define SUB8(a, b, n) \
3719
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3722
#include "op_addsub.h"
3724
static inline uint8_t do_usad(uint8_t a, uint8_t b)
3732
/* Unsigned sum of absolute byte differences. */
3733
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3736
sum = do_usad(a, b);
3737
sum += do_usad(a >> 8, b >> 8);
3738
sum += do_usad(a >> 16, b >>16);
3739
sum += do_usad(a >> 24, b >> 24);
3743
/* For ARMv6 SEL instruction. */
3744
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3757
return (a & mask) | (b & ~mask);
3760
/* VFP support. We follow the convention used for VFP instructions:
3761
Single precision routines have a "s" suffix, double precision a
3764
/* Convert host exception flags to vfp form. */
3765
static inline int vfp_exceptbits_from_host(int host_bits)
3767
int target_bits = 0;
3769
if (host_bits & float_flag_invalid)
3771
if (host_bits & float_flag_divbyzero)
3773
if (host_bits & float_flag_overflow)
3775
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3777
if (host_bits & float_flag_inexact)
3778
target_bits |= 0x10;
3779
if (host_bits & float_flag_input_denormal)
3780
target_bits |= 0x80;
3784
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
3789
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3790
| (env->vfp.vec_len << 16)
3791
| (env->vfp.vec_stride << 20);
3792
i = get_float_exception_flags(&env->vfp.fp_status);
3793
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
3794
fpscr |= vfp_exceptbits_from_host(i);
3798
uint32_t vfp_get_fpscr(CPUARMState *env)
3800
return HELPER(vfp_get_fpscr)(env);
3803
/* Convert vfp exception flags to target form. */
3804
static inline int vfp_exceptbits_to_host(int target_bits)
3808
if (target_bits & 1)
3809
host_bits |= float_flag_invalid;
3810
if (target_bits & 2)
3811
host_bits |= float_flag_divbyzero;
3812
if (target_bits & 4)
3813
host_bits |= float_flag_overflow;
3814
if (target_bits & 8)
3815
host_bits |= float_flag_underflow;
3816
if (target_bits & 0x10)
3817
host_bits |= float_flag_inexact;
3818
if (target_bits & 0x80)
3819
host_bits |= float_flag_input_denormal;
3823
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
3828
changed = env->vfp.xregs[ARM_VFP_FPSCR];
3829
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3830
env->vfp.vec_len = (val >> 16) & 7;
3831
env->vfp.vec_stride = (val >> 20) & 3;
3834
if (changed & (3 << 22)) {
3835
i = (val >> 22) & 3;
3837
case FPROUNDING_TIEEVEN:
3838
i = float_round_nearest_even;
3840
case FPROUNDING_POSINF:
3843
case FPROUNDING_NEGINF:
3844
i = float_round_down;
3846
case FPROUNDING_ZERO:
3847
i = float_round_to_zero;
3850
set_float_rounding_mode(i, &env->vfp.fp_status);
3852
if (changed & (1 << 24)) {
3853
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3854
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3856
if (changed & (1 << 25))
3857
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
3859
i = vfp_exceptbits_to_host(val);
3860
set_float_exception_flags(i, &env->vfp.fp_status);
3861
set_float_exception_flags(0, &env->vfp.standard_fp_status);
3864
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3866
HELPER(vfp_set_fpscr)(env, val);
3869
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3871
#define VFP_BINOP(name) \
3872
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3874
float_status *fpst = fpstp; \
3875
return float32_ ## name(a, b, fpst); \
3877
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3879
float_status *fpst = fpstp; \
3880
return float64_ ## name(a, b, fpst); \
3892
float32 VFP_HELPER(neg, s)(float32 a)
3894
return float32_chs(a);
3897
float64 VFP_HELPER(neg, d)(float64 a)
3899
return float64_chs(a);
3902
float32 VFP_HELPER(abs, s)(float32 a)
3904
return float32_abs(a);
3907
float64 VFP_HELPER(abs, d)(float64 a)
3909
return float64_abs(a);
3912
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3914
return float32_sqrt(a, &env->vfp.fp_status);
3917
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3919
return float64_sqrt(a, &env->vfp.fp_status);
3922
/* XXX: check quiet/signaling case */
3923
#define DO_VFP_cmp(p, type) \
3924
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3927
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3928
case 0: flags = 0x6; break; \
3929
case -1: flags = 0x8; break; \
3930
case 1: flags = 0x2; break; \
3931
default: case 2: flags = 0x3; break; \
3933
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3934
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3936
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3939
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3940
case 0: flags = 0x6; break; \
3941
case -1: flags = 0x8; break; \
3942
case 1: flags = 0x2; break; \
3943
default: case 2: flags = 0x3; break; \
3945
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3946
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3948
DO_VFP_cmp(s, float32)
3949
DO_VFP_cmp(d, float64)
3952
/* Integer to float and float to integer conversions */
3954
#define CONV_ITOF(name, fsz, sign) \
3955
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3957
float_status *fpst = fpstp; \
3958
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3961
#define CONV_FTOI(name, fsz, sign, round) \
3962
uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3964
float_status *fpst = fpstp; \
3965
if (float##fsz##_is_any_nan(x)) { \
3966
float_raise(float_flag_invalid, fpst); \
3969
return float##fsz##_to_##sign##int32##round(x, fpst); \
3972
#define FLOAT_CONVS(name, p, fsz, sign) \
3973
CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3974
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3975
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3977
FLOAT_CONVS(si, s, 32, )
3978
FLOAT_CONVS(si, d, 64, )
3979
FLOAT_CONVS(ui, s, 32, u)
3980
FLOAT_CONVS(ui, d, 64, u)
3986
/* floating point conversion */
3987
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3989
float64 r = float32_to_float64(x, &env->vfp.fp_status);
3990
/* ARM requires that S<->D conversion of any kind of NaN generates
3991
* a quiet NaN by forcing the most significant frac bit to 1.
3993
return float64_maybe_silence_nan(r);
3996
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
3998
float32 r = float64_to_float32(x, &env->vfp.fp_status);
3999
/* ARM requires that S<->D conversion of any kind of NaN generates
4000
* a quiet NaN by forcing the most significant frac bit to 1.
4002
return float32_maybe_silence_nan(r);
4005
/* VFP3 fixed point conversion. */
4006
#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4007
float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4010
float_status *fpst = fpstp; \
4012
tmp = itype##_to_##float##fsz(x, fpst); \
4013
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4016
/* Notice that we want only input-denormal exception flags from the
4017
* scalbn operation: the other possible flags (overflow+inexact if
4018
* we overflow to infinity, output-denormal) aren't correct for the
4019
* complete scale-and-convert operation.
4021
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4022
uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4026
float_status *fpst = fpstp; \
4027
int old_exc_flags = get_float_exception_flags(fpst); \
4029
if (float##fsz##_is_any_nan(x)) { \
4030
float_raise(float_flag_invalid, fpst); \
4033
tmp = float##fsz##_scalbn(x, shift, fpst); \
4034
old_exc_flags |= get_float_exception_flags(fpst) \
4035
& float_flag_input_denormal; \
4036
set_float_exception_flags(old_exc_flags, fpst); \
4037
return float##fsz##_to_##itype##round(tmp, fpst); \
4040
#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4041
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4042
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4043
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4045
#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4046
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4047
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4049
VFP_CONV_FIX(sh, d, 64, 64, int16)
4050
VFP_CONV_FIX(sl, d, 64, 64, int32)
4051
VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4052
VFP_CONV_FIX(uh, d, 64, 64, uint16)
4053
VFP_CONV_FIX(ul, d, 64, 64, uint32)
4054
VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4055
VFP_CONV_FIX(sh, s, 32, 32, int16)
4056
VFP_CONV_FIX(sl, s, 32, 32, int32)
4057
VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4058
VFP_CONV_FIX(uh, s, 32, 32, uint16)
4059
VFP_CONV_FIX(ul, s, 32, 32, uint32)
4060
VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4062
#undef VFP_CONV_FIX_FLOAT
4063
#undef VFP_CONV_FLOAT_FIX_ROUND
4065
/* Set the current fp rounding mode and return the old one.
4066
* The argument is a softfloat float_round_ value.
4068
uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4070
float_status *fp_status = &env->vfp.fp_status;
4072
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4073
set_float_rounding_mode(rmode, fp_status);
4078
/* Half precision conversions. */
4079
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4081
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4082
float32 r = float16_to_float32(make_float16(a), ieee, s);
4084
return float32_maybe_silence_nan(r);
4089
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4091
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4092
float16 r = float32_to_float16(a, ieee, s);
4094
r = float16_maybe_silence_nan(r);
4096
return float16_val(r);
4099
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4101
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4104
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4106
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4109
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4111
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4114
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4116
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4119
float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4121
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4122
float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4124
return float64_maybe_silence_nan(r);
4129
uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4131
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4132
float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4134
r = float16_maybe_silence_nan(r);
4136
return float16_val(r);
4139
#define float32_two make_float32(0x40000000)
4140
#define float32_three make_float32(0x40400000)
4141
#define float32_one_point_five make_float32(0x3fc00000)
4143
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4145
float_status *s = &env->vfp.standard_fp_status;
4146
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4147
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4148
if (!(float32_is_zero(a) || float32_is_zero(b))) {
4149
float_raise(float_flag_input_denormal, s);
4153
return float32_sub(float32_two, float32_mul(a, b, s), s);
4156
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4158
float_status *s = &env->vfp.standard_fp_status;
4160
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4161
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4162
if (!(float32_is_zero(a) || float32_is_zero(b))) {
4163
float_raise(float_flag_input_denormal, s);
4165
return float32_one_point_five;
4167
product = float32_mul(a, b, s);
4168
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4173
/* Constants 256 and 512 are used in some helpers; we avoid relying on
4174
* int->float conversions at run-time. */
4175
#define float64_256 make_float64(0x4070000000000000LL)
4176
#define float64_512 make_float64(0x4080000000000000LL)
4178
/* The algorithm that must be used to calculate the estimate
4179
* is specified by the ARM ARM.
4181
static float64 recip_estimate(float64 a, CPUARMState *env)
4183
/* These calculations mustn't set any fp exception flags,
4184
* so we use a local copy of the fp_status.
4186
float_status dummy_status = env->vfp.standard_fp_status;
4187
float_status *s = &dummy_status;
4188
/* q = (int)(a * 512.0) */
4189
float64 q = float64_mul(float64_512, a, s);
4190
int64_t q_int = float64_to_int64_round_to_zero(q, s);
4192
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
4193
q = int64_to_float64(q_int, s);
4194
q = float64_add(q, float64_half, s);
4195
q = float64_div(q, float64_512, s);
4196
q = float64_div(float64_one, q, s);
4198
/* s = (int)(256.0 * r + 0.5) */
4199
q = float64_mul(q, float64_256, s);
4200
q = float64_add(q, float64_half, s);
4201
q_int = float64_to_int64_round_to_zero(q, s);
4203
/* return (double)s / 256.0 */
4204
return float64_div(int64_to_float64(q_int, s), float64_256, s);
4207
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4209
float_status *s = &env->vfp.standard_fp_status;
4211
uint32_t val32 = float32_val(a);
4214
int a_exp = (val32 & 0x7f800000) >> 23;
4215
int sign = val32 & 0x80000000;
4217
if (float32_is_any_nan(a)) {
4218
if (float32_is_signaling_nan(a)) {
4219
float_raise(float_flag_invalid, s);
4221
return float32_default_nan;
4222
} else if (float32_is_infinity(a)) {
4223
return float32_set_sign(float32_zero, float32_is_neg(a));
4224
} else if (float32_is_zero_or_denormal(a)) {
4225
if (!float32_is_zero(a)) {
4226
float_raise(float_flag_input_denormal, s);
4228
float_raise(float_flag_divbyzero, s);
4229
return float32_set_sign(float32_infinity, float32_is_neg(a));
4230
} else if (a_exp >= 253) {
4231
float_raise(float_flag_underflow, s);
4232
return float32_set_sign(float32_zero, float32_is_neg(a));
4235
f64 = make_float64((0x3feULL << 52)
4236
| ((int64_t)(val32 & 0x7fffff) << 29));
4238
result_exp = 253 - a_exp;
4240
f64 = recip_estimate(f64, env);
4243
| ((result_exp & 0xff) << 23)
4244
| ((float64_val(f64) >> 29) & 0x7fffff);
4245
return make_float32(val32);
4248
/* The algorithm that must be used to calculate the estimate
4249
* is specified by the ARM ARM.
4251
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
4253
/* These calculations mustn't set any fp exception flags,
4254
* so we use a local copy of the fp_status.
4256
float_status dummy_status = env->vfp.standard_fp_status;
4257
float_status *s = &dummy_status;
4261
if (float64_lt(a, float64_half, s)) {
4262
/* range 0.25 <= a < 0.5 */
4264
/* a in units of 1/512 rounded down */
4265
/* q0 = (int)(a * 512.0); */
4266
q = float64_mul(float64_512, a, s);
4267
q_int = float64_to_int64_round_to_zero(q, s);
4269
/* reciprocal root r */
4270
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4271
q = int64_to_float64(q_int, s);
4272
q = float64_add(q, float64_half, s);
4273
q = float64_div(q, float64_512, s);
4274
q = float64_sqrt(q, s);
4275
q = float64_div(float64_one, q, s);
4277
/* range 0.5 <= a < 1.0 */
4279
/* a in units of 1/256 rounded down */
4280
/* q1 = (int)(a * 256.0); */
4281
q = float64_mul(float64_256, a, s);
4282
int64_t q_int = float64_to_int64_round_to_zero(q, s);
4284
/* reciprocal root r */
4285
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4286
q = int64_to_float64(q_int, s);
4287
q = float64_add(q, float64_half, s);
4288
q = float64_div(q, float64_256, s);
4289
q = float64_sqrt(q, s);
4290
q = float64_div(float64_one, q, s);
4292
/* r in units of 1/256 rounded to nearest */
4293
/* s = (int)(256.0 * r + 0.5); */
4295
q = float64_mul(q, float64_256,s );
4296
q = float64_add(q, float64_half, s);
4297
q_int = float64_to_int64_round_to_zero(q, s);
4299
/* return (double)s / 256.0;*/
4300
return float64_div(int64_to_float64(q_int, s), float64_256, s);
4303
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4305
float_status *s = &env->vfp.standard_fp_status;
4311
val = float32_val(a);
4313
if (float32_is_any_nan(a)) {
4314
if (float32_is_signaling_nan(a)) {
4315
float_raise(float_flag_invalid, s);
4317
return float32_default_nan;
4318
} else if (float32_is_zero_or_denormal(a)) {
4319
if (!float32_is_zero(a)) {
4320
float_raise(float_flag_input_denormal, s);
4322
float_raise(float_flag_divbyzero, s);
4323
return float32_set_sign(float32_infinity, float32_is_neg(a));
4324
} else if (float32_is_neg(a)) {
4325
float_raise(float_flag_invalid, s);
4326
return float32_default_nan;
4327
} else if (float32_is_infinity(a)) {
4328
return float32_zero;
4331
/* Normalize to a double-precision value between 0.25 and 1.0,
4332
* preserving the parity of the exponent. */
4333
if ((val & 0x800000) == 0) {
4334
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4336
| ((uint64_t)(val & 0x7fffff) << 29));
4338
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4340
| ((uint64_t)(val & 0x7fffff) << 29));
4343
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4345
f64 = recip_sqrt_estimate(f64, env);
4347
val64 = float64_val(f64);
4349
val = ((result_exp & 0xff) << 23)
4350
| ((val64 >> 29) & 0x7fffff);
4351
return make_float32(val);
4354
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4358
if ((a & 0x80000000) == 0) {
4362
f64 = make_float64((0x3feULL << 52)
4363
| ((int64_t)(a & 0x7fffffff) << 21));
4365
f64 = recip_estimate (f64, env);
4367
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4370
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4374
if ((a & 0xc0000000) == 0) {
4378
if (a & 0x80000000) {
4379
f64 = make_float64((0x3feULL << 52)
4380
| ((uint64_t)(a & 0x7fffffff) << 21));
4381
} else { /* bits 31-30 == '01' */
4382
f64 = make_float64((0x3fdULL << 52)
4383
| ((uint64_t)(a & 0x3fffffff) << 22));
4386
f64 = recip_sqrt_estimate(f64, env);
4388
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4391
/* VFPv4 fused multiply-accumulate */
4392
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4394
float_status *fpst = fpstp;
4395
return float32_muladd(a, b, c, 0, fpst);
4398
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4400
float_status *fpst = fpstp;
4401
return float64_muladd(a, b, c, 0, fpst);
4404
/* ARMv8 round to integral */
4405
float32 HELPER(rints_exact)(float32 x, void *fp_status)
4407
return float32_round_to_int(x, fp_status);
4410
float64 HELPER(rintd_exact)(float64 x, void *fp_status)
4412
return float64_round_to_int(x, fp_status);
4415
float32 HELPER(rints)(float32 x, void *fp_status)
4417
int old_flags = get_float_exception_flags(fp_status), new_flags;
4420
ret = float32_round_to_int(x, fp_status);
4422
/* Suppress any inexact exceptions the conversion produced */
4423
if (!(old_flags & float_flag_inexact)) {
4424
new_flags = get_float_exception_flags(fp_status);
4425
set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4431
float64 HELPER(rintd)(float64 x, void *fp_status)
4433
int old_flags = get_float_exception_flags(fp_status), new_flags;
4436
ret = float64_round_to_int(x, fp_status);
4438
new_flags = get_float_exception_flags(fp_status);
4440
/* Suppress any inexact exceptions the conversion produced */
4441
if (!(old_flags & float_flag_inexact)) {
4442
new_flags = get_float_exception_flags(fp_status);
4443
set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4449
/* Convert ARM rounding mode to softfloat */
4450
int arm_rmode_to_sf(int rmode)
4453
case FPROUNDING_TIEAWAY:
4454
rmode = float_round_ties_away;
4456
case FPROUNDING_ODD:
4457
/* FIXME: add support for TIEAWAY and ODD */
4458
qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
4460
case FPROUNDING_TIEEVEN:
4462
rmode = float_round_nearest_even;
4464
case FPROUNDING_POSINF:
4465
rmode = float_round_up;
4467
case FPROUNDING_NEGINF:
4468
rmode = float_round_down;
4470
case FPROUNDING_ZERO:
4471
rmode = float_round_to_zero;
added
removed
.pc/ubuntu/arm64/0128-target-arm-Add-set_neon_rmode-helper.patch/target-arm/helper.c
