69
69
static void usage(void);
71
71
static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72
const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
74
# define UNAME_RELEASE "3.7.0"
76
# define UNAME_RELEASE CONFIG_UNAME_RELEASE
79
const char *qemu_uname_release = UNAME_RELEASE;
74
81
/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75
82
we allocate a bigger stack. Need a better solution, for example
596
/* Store exclusive handling for AArch32 */
590
597
static int do_strex(CPUARMState *env)
597
604
start_exclusive();
598
addr = env->exclusive_addr;
599
if (addr != env->exclusive_test) {
605
if (env->exclusive_addr != env->exclusive_test) {
608
/* We know we're always AArch32 so the address is in uint32_t range
609
* unless it was the -1 exclusive-monitor-lost value (which won't
610
* match exclusive_test above).
612
assert(extract64(env->exclusive_addr, 32, 32) == 0);
613
addr = env->exclusive_addr;
602
614
size = env->exclusive_info & 0xf;
618
630
env->cp15.c6_data = addr;
621
if (val != env->exclusive_val) {
625
segv = get_user_u32(val, addr + 4);
635
segv = get_user_u32(valhi, addr + 4);
627
637
env->cp15.c6_data = addr + 4;
630
if (val != env->exclusive_high) {
640
val = deposit64(val, 32, 32, valhi);
642
if (val != env->exclusive_val) {
634
646
val = env->regs[(env->exclusive_info >> 8) & 0xf];
895
* Handle AArch64 store-release exclusive
897
* rs = gets the status result of store exclusive
898
* rt = is the register that is stored
899
* rt2 = is the second register store (in STP)
902
static int do_strex_a64(CPUARMState *env)
913
/* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
914
size = extract32(env->exclusive_info, 0, 2);
915
is_pair = extract32(env->exclusive_info, 2, 1);
916
rs = extract32(env->exclusive_info, 4, 5);
917
rt = extract32(env->exclusive_info, 9, 5);
918
rt2 = extract32(env->exclusive_info, 14, 5);
920
addr = env->exclusive_addr;
922
if (addr != env->exclusive_test) {
928
segv = get_user_u8(val, addr);
931
segv = get_user_u16(val, addr);
934
segv = get_user_u32(val, addr);
937
segv = get_user_u64(val, addr);
943
env->cp15.c6_data = addr;
946
if (val != env->exclusive_val) {
951
segv = get_user_u32(val, addr + 4);
953
segv = get_user_u64(val, addr + 8);
956
env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
959
if (val != env->exclusive_high) {
963
val = env->xregs[rt];
966
segv = put_user_u8(val, addr);
969
segv = put_user_u16(val, addr);
972
segv = put_user_u32(val, addr);
975
segv = put_user_u64(val, addr);
982
val = env->xregs[rt2];
984
segv = put_user_u32(val, addr + 4);
986
segv = put_user_u64(val, addr + 8);
989
env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
996
/* rs == 31 encodes a write to the ZR, thus throwing away
997
* the status return. This is rather silly but valid.
1000
env->xregs[rs] = rc;
1003
/* instruction faulted, PC does not advance */
1004
/* either way a strex releases any exclusive lock we have */
1005
env->exclusive_addr = -1;
883
1010
/* AArch64 main loop */
884
1011
void cpu_loop(CPUARMState *env)
953
1080
process_pending_signals(env);
1081
/* Exception return on AArch64 always clears the exclusive monitor,
1082
* so any return to running guest code implies this.
1083
* A strex (successful or otherwise) also clears the monitor, so
1084
* we don't need to specialcase EXCP_STREX.
1086
env->exclusive_addr = -1;
956
1089
#endif /* ndef TARGET_ABI32 */