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From a3ca5aff47390abcb5c665cdea6248feb0246c72 Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Tue, 7 Jan 2014 17:19:14 +0000
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Subject: [PATCH 108/158] target-arm: A64: Add 1-source 32-to-32 and 64-to-64
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This patch adds support for those instructions in the "Floating-point
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data-processing (1 source)" group which are simple 32-bit-to-32-bit
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or 64-bit-to-64-bit operations (ie everything except FCVT between
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single/double/half precision).
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We put the new round-to-int helpers in helper.c because they will
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also be used by the new ARMv8 A32/T32 rounding instructions.
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Signed-off-by: Alexander Graf <agraf@suse.de>
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[WN: Commit message tweak, merged single and double precision patches,
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updated to new infrastructure.]
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Signed-off-by: Will Newton <will.newton@linaro.org>
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[PMM: reworked decode, split FCVT out into their own patch]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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target-arm/helper.c | 45 ++++++++++++++
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target-arm/helper.h | 5 ++
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target-arm/translate-a64.c | 142 ++++++++++++++++++++++++++++++++++++++++++++-
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3 files changed, 191 insertions(+), 1 deletion(-)
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diff --git a/target-arm/helper.c b/target-arm/helper.c
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index 6206af7..b84b8a1 100644
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--- a/target-arm/helper.c
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+++ b/target-arm/helper.c
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@@ -4388,3 +4388,48 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
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float_status *fpst = fpstp;
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return float64_muladd(a, b, c, 0, fpst);
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+/* ARMv8 round to integral */
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+float32 HELPER(rints_exact)(float32 x, void *fp_status)
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+ return float32_round_to_int(x, fp_status);
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+float64 HELPER(rintd_exact)(float64 x, void *fp_status)
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+ return float64_round_to_int(x, fp_status);
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+float32 HELPER(rints)(float32 x, void *fp_status)
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+ int old_flags = get_float_exception_flags(fp_status), new_flags;
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+ ret = float32_round_to_int(x, fp_status);
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+ /* Suppress any inexact exceptions the conversion produced */
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+ if (!(old_flags & float_flag_inexact)) {
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+ new_flags = get_float_exception_flags(fp_status);
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+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
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+float64 HELPER(rintd)(float64 x, void *fp_status)
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+ int old_flags = get_float_exception_flags(fp_status), new_flags;
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+ ret = float64_round_to_int(x, fp_status);
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+ new_flags = get_float_exception_flags(fp_status);
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+ /* Suppress any inexact exceptions the conversion produced */
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+ if (!(old_flags & float_flag_inexact)) {
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+ new_flags = get_float_exception_flags(fp_status);
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+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
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diff --git a/target-arm/helper.h b/target-arm/helper.h
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index 6dccf90..329b97f 100644
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--- a/target-arm/helper.h
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+++ b/target-arm/helper.h
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@@ -171,6 +171,11 @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32)
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DEF_HELPER_3(sar_cc, i32, env, i32, i32)
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DEF_HELPER_3(ror_cc, i32, env, i32, i32)
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+DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr)
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+DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
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+DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
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+DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
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DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qadd_s8, i32, env, i32, i32)
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
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index 9b23d37..345a47b 100644
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--- a/target-arm/translate-a64.c
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+++ b/target-arm/translate-a64.c
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@@ -3386,6 +3386,118 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
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+/* C3.6.25 Floating-point data-processing (1 source) - single precision */
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+static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
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+ fpst = get_fpstatus_ptr();
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+ tcg_op = read_fp_sreg(s, rn);
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+ tcg_res = tcg_temp_new_i32();
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+ case 0x0: /* FMOV */
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+ tcg_gen_mov_i32(tcg_res, tcg_op);
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+ case 0x1: /* FABS */
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+ gen_helper_vfp_abss(tcg_res, tcg_op);
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+ case 0x2: /* FNEG */
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+ gen_helper_vfp_negs(tcg_res, tcg_op);
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+ case 0x3: /* FSQRT */
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+ gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
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+ case 0x8: /* FRINTN */
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+ case 0x9: /* FRINTP */
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+ case 0xa: /* FRINTM */
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+ case 0xb: /* FRINTZ */
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+ case 0xc: /* FRINTA */
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+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
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+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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+ gen_helper_rints(tcg_res, tcg_op, fpst);
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+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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+ tcg_temp_free_i32(tcg_rmode);
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+ case 0xe: /* FRINTX */
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+ gen_helper_rints_exact(tcg_res, tcg_op, fpst);
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+ case 0xf: /* FRINTI */
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+ gen_helper_rints(tcg_res, tcg_op, fpst);
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+ write_fp_sreg(s, rd, tcg_res);
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+ tcg_temp_free_ptr(fpst);
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+ tcg_temp_free_i32(tcg_op);
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+ tcg_temp_free_i32(tcg_res);
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+/* C3.6.25 Floating-point data-processing (1 source) - double precision */
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+static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
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+ fpst = get_fpstatus_ptr();
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+ tcg_op = read_fp_dreg(s, rn);
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+ tcg_res = tcg_temp_new_i64();
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+ case 0x0: /* FMOV */
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+ tcg_gen_mov_i64(tcg_res, tcg_op);
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+ case 0x1: /* FABS */
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+ gen_helper_vfp_absd(tcg_res, tcg_op);
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+ case 0x2: /* FNEG */
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+ gen_helper_vfp_negd(tcg_res, tcg_op);
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+ case 0x3: /* FSQRT */
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+ gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
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+ case 0x8: /* FRINTN */
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+ case 0x9: /* FRINTP */
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+ case 0xa: /* FRINTM */
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+ case 0xb: /* FRINTZ */
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+ case 0xc: /* FRINTA */
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+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
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+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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+ gen_helper_rintd(tcg_res, tcg_op, fpst);
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+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
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+ tcg_temp_free_i32(tcg_rmode);
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+ case 0xe: /* FRINTX */
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+ gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
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+ case 0xf: /* FRINTI */
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+ gen_helper_rintd(tcg_res, tcg_op, fpst);
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+ write_fp_dreg(s, rd, tcg_res);
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+ tcg_temp_free_ptr(fpst);
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+ tcg_temp_free_i64(tcg_op);
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+ tcg_temp_free_i64(tcg_res);
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/* C3.6.25 Floating point data-processing (1 source)
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* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
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* +---+---+---+-----------+------+---+--------+-----------+------+------+
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@@ -3394,7 +3506,35 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
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static void disas_fp_1src(DisasContext *s, uint32_t insn)
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- unsupported_encoding(s, insn);
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+ int type = extract32(insn, 22, 2);
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+ int opcode = extract32(insn, 15, 6);
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+ int rn = extract32(insn, 5, 5);
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+ int rd = extract32(insn, 0, 5);
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+ case 0x4: case 0x5: case 0x7:
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+ /* FCVT between half, single and double precision */
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+ unsupported_encoding(s, insn);
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+ /* 32-to-32 and 64-to-64 ops */
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+ handle_fp_1src_single(s, opcode, rd, rn);
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+ handle_fp_1src_double(s, opcode, rd, rn);
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+ unallocated_encoding(s);
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+ unallocated_encoding(s);
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/* C3.6.26 Floating-point data-processing (2 source) - single precision */