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From afb761a664ef46fac23a1631c6ffd236ea860aae Mon Sep 17 00:00:00 2001
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From: Claudio Fontana <claudio.fontana@linaro.org>
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Date: Sat, 4 Jan 2014 22:15:46 +0000
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Subject: [PATCH 068/158] target-arm: A64: add support for conditional compare
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this patch adds support for C3.5.4 - C3.5.5
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Conditional compare (both immediate and register)
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Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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target-arm/translate-a64.c | 73 +++++++++++++++++++++++++++++++++++++---------
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1 file changed, 60 insertions(+), 13 deletions(-)
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diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
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index 9f508b9..538d69e 100644
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--- a/target-arm/translate-a64.c
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+++ b/target-arm/translate-a64.c
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@@ -2483,16 +2483,67 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
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-/* Conditional compare (immediate) */
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-static void disas_cc_imm(DisasContext *s, uint32_t insn)
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+/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
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+ * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
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+ * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
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+ * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
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+ * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
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+static void disas_cc(DisasContext *s, uint32_t insn)
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- unsupported_encoding(s, insn);
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+ unsigned int sf, op, y, cond, rn, nzcv, is_imm;
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+ int label_continue = -1;
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+ TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
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-/* Conditional compare (register) */
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-static void disas_cc_reg(DisasContext *s, uint32_t insn)
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- unsupported_encoding(s, insn);
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+ if (!extract32(insn, 29, 1)) {
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+ unallocated_encoding(s);
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+ if (insn & (1 << 10 | 1 << 4)) {
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+ unallocated_encoding(s);
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+ sf = extract32(insn, 31, 1);
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+ op = extract32(insn, 30, 1);
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+ is_imm = extract32(insn, 11, 1);
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+ y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
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+ cond = extract32(insn, 12, 4);
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+ rn = extract32(insn, 5, 5);
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+ nzcv = extract32(insn, 0, 4);
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+ if (cond < 0x0e) { /* not always */
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+ int label_match = gen_new_label();
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+ label_continue = gen_new_label();
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+ arm_gen_test_cc(cond, label_match);
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+ tcg_tmp = tcg_temp_new_i64();
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+ tcg_gen_movi_i64(tcg_tmp, nzcv << 28);
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+ gen_set_nzcv(tcg_tmp);
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+ tcg_temp_free_i64(tcg_tmp);
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+ tcg_gen_br(label_continue);
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+ gen_set_label(label_match);
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+ /* match, or condition is always */
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+ tcg_y = new_tmp_a64(s);
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+ tcg_gen_movi_i64(tcg_y, y);
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+ tcg_y = cpu_reg(s, y);
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+ tcg_rn = cpu_reg(s, rn);
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+ tcg_tmp = tcg_temp_new_i64();
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+ gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
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+ gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
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+ tcg_temp_free_i64(tcg_tmp);
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+ if (cond < 0x0e) { /* continue */
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+ gen_set_label(label_continue);
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/* C3.5.6 Conditional select
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@@ -2846,11 +2897,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
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disas_adc_sbc(s, insn);
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case 0x2: /* Conditional compare */
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- if (insn & (1 << 11)) { /* (immediate) */
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- disas_cc_imm(s, insn);
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- } else { /* (register) */
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- disas_cc_reg(s, insn);
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+ disas_cc(s, insn); /* both imm and reg forms */
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case 0x4: /* Conditional select */
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disas_cond_select(s, insn);