644
644
#define lduw_code(p) lduw_raw(p)
645
645
#define ldsw_code(p) ldsw_raw(p)
646
646
#define ldl_code(p) ldl_raw(p)
647
#define ldq_code(p) ldq_raw(p)
648
649
#define ldub_kernel(p) ldub_raw(p)
649
650
#define ldsb_kernel(p) ldsb_raw(p)
650
651
#define lduw_kernel(p) lduw_raw(p)
651
652
#define ldsw_kernel(p) ldsw_raw(p)
652
653
#define ldl_kernel(p) ldl_raw(p)
654
#define ldq_kernel(p) ldq_raw(p)
653
655
#define ldfl_kernel(p) ldfl_raw(p)
654
656
#define ldfq_kernel(p) ldfq_raw(p)
655
657
#define stb_kernel(p, v) stb_raw(p, v)
690
692
void page_set_flags(target_ulong start, target_ulong end, int flags);
691
693
void page_unprotect_range(target_ulong data, target_ulong data_size);
693
#define SINGLE_CPU_DEFINES
694
#ifdef SINGLE_CPU_DEFINES
696
#if defined(TARGET_I386)
698
#define CPUState CPUX86State
699
#define cpu_init cpu_x86_init
700
#define cpu_exec cpu_x86_exec
701
#define cpu_gen_code cpu_x86_gen_code
702
#define cpu_signal_handler cpu_x86_signal_handler
704
#elif defined(TARGET_ARM)
706
#define CPUState CPUARMState
707
#define cpu_init cpu_arm_init
708
#define cpu_exec cpu_arm_exec
709
#define cpu_gen_code cpu_arm_gen_code
710
#define cpu_signal_handler cpu_arm_signal_handler
712
#elif defined(TARGET_SPARC)
714
#define CPUState CPUSPARCState
715
#define cpu_init cpu_sparc_init
716
#define cpu_exec cpu_sparc_exec
717
#define cpu_gen_code cpu_sparc_gen_code
718
#define cpu_signal_handler cpu_sparc_signal_handler
720
#elif defined(TARGET_PPC)
722
#define CPUState CPUPPCState
723
#define cpu_init cpu_ppc_init
724
#define cpu_exec cpu_ppc_exec
725
#define cpu_gen_code cpu_ppc_gen_code
726
#define cpu_signal_handler cpu_ppc_signal_handler
728
#elif defined(TARGET_M68K)
729
#define CPUState CPUM68KState
730
#define cpu_init cpu_m68k_init
731
#define cpu_exec cpu_m68k_exec
732
#define cpu_gen_code cpu_m68k_gen_code
733
#define cpu_signal_handler cpu_m68k_signal_handler
735
#elif defined(TARGET_MIPS)
736
#define CPUState CPUMIPSState
737
#define cpu_init cpu_mips_init
738
#define cpu_exec cpu_mips_exec
739
#define cpu_gen_code cpu_mips_gen_code
740
#define cpu_signal_handler cpu_mips_signal_handler
742
#elif defined(TARGET_SH4)
743
#define CPUState CPUSH4State
744
#define cpu_init cpu_sh4_init
745
#define cpu_exec cpu_sh4_exec
746
#define cpu_gen_code cpu_sh4_gen_code
747
#define cpu_signal_handler cpu_sh4_signal_handler
751
#error unsupported target CPU
755
#endif /* SINGLE_CPU_DEFINES */
695
CPUState *cpu_copy(CPUState *env);
757
697
void cpu_dump_state(CPUState *env, FILE *f,
758
698
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
700
void cpu_dump_statistics (CPUState *env, FILE *f,
701
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
761
void cpu_abort(CPUState *env, const char *fmt, ...);
704
void cpu_abort(CPUState *env, const char *fmt, ...)
705
__attribute__ ((__format__ (__printf__, 2, 3)))
706
__attribute__ ((__noreturn__));
762
707
extern CPUState *first_cpu;
763
708
extern CPUState *cpu_single_env;
764
709
extern int code_copy_enabled;
770
715
#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
771
716
#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
772
717
#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
718
#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
774
720
void cpu_interrupt(CPUState *s, int mask);
775
721
void cpu_reset_interrupt(CPUState *env, int mask);
723
int cpu_watchpoint_insert(CPUState *env, target_ulong addr);
724
int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
777
725
int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
778
726
int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
779
727
void cpu_single_step(CPUState *env, int enabled);
1001
953
return rval.i64;
957
#elif defined(__mips__)
959
static inline int64_t cpu_get_real_ticks(void)
961
#if __mips_isa_rev >= 2
963
static uint32_t cyc_per_count = 0;
966
__asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
968
__asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
969
return (int64_t)(count * cyc_per_count);
972
static int64_t ticks = 0;
1005
978
/* The host CPU doesn't have an easily accessible cycle counter.
1006
Just return a monotonically increasing vlue. This will be totally wrong,
1007
but hopefully better than nothing. */
979
Just return a monotonically increasing value. This will be
980
totally wrong, but hopefully better than nothing. */
1008
981
static inline int64_t cpu_get_real_ticks (void)
1010
983
static int64_t ticks = 0;