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- Committer: Bazaar Package Importer
- Author(s): Soren Hansen
- Date: 2007-10-22 17:07:29 UTC
- mto: (1.5.1) (10.1.1 squeeze) (11.1.1 experimental) (12.1.1 sid) (6.1.1 sid)
- mto: This revision was merged to the branch mainline in revision 3.
- Revision ID: james.westby@ubuntu.com-20071022170729-4ihaxntpl01xg29n
Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816
- files added:
- block-parallels.c
- linux-user/alpha
- linux-user/ppc64
- linux-user/x86_64
- target-alpha
- files removed:
- linux-user/m68k-semi.c
- files modified:
- Changelog
added
removed
hw/ide.c
2
2
* QEMU IDE disk and CD-ROM Emulator
3
3
*
4
4
* Copyright (c) 2003 Fabrice Bellard
5
* Copyright (c) 2006 Openedhand Ltd.
5
6
*
6
7
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
8
* of this software and associated documentation files (the "Software"), to deal
131
132
#define WIN_SPECIFY 0x91 /* set drive geometry translation */
132
133
#define WIN_DOWNLOAD_MICROCODE 0x92
133
134
#define WIN_STANDBYNOW2 0x94
135
#define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */
134
136
#define WIN_STANDBY2 0x96
135
137
#define WIN_SETIDLE2 0x97
136
138
#define WIN_CHECKPOWERMODE2 0x98
142
144
#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
143
145
#define WIN_QUEUED_SERVICE 0xA2
144
146
#define WIN_SMART 0xB0 /* self-monitoring and reporting */
145
#define CFA_ERASE_SECTORS 0xC0
147
#define CFA_ACCESS_METADATA_STORAGE 0xB8
148
#define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
146
149
#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
147
150
#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
148
151
#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
176
179
#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
177
180
#define WIN_SETFEATURES 0xEF /* set special drive features */
178
181
#define EXABYTE_ENABLE_NEST 0xF0
182
#define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */
179
183
#define WIN_SECURITY_SET_PASS 0xF1
180
184
#define WIN_SECURITY_UNLOCK 0xF2
181
185
#define WIN_SECURITY_ERASE_PREPARE 0xF3
182
186
#define WIN_SECURITY_ERASE_UNIT 0xF4
183
187
#define WIN_SECURITY_FREEZE_LOCK 0xF5
188
#define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */
184
189
#define WIN_SECURITY_DISABLE 0xF6
185
190
#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
186
191
#define WIN_SET_MAX 0xF9
282
287
#define ASC_MEDIUM_NOT_PRESENT 0x3a
283
288
#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
284
289
290
#define CFA_NO_ERROR 0x00
291
#define CFA_MISC_ERROR 0x09
292
#define CFA_INVALID_COMMAND 0x20
293
#define CFA_INVALID_ADDRESS 0x21
294
#define CFA_ADDRESS_OVERFLOW 0x2f
295
285
296
#define SENSE_NONE 0
286
297
#define SENSE_NOT_READY 2
287
298
#define SENSE_ILLEGAL_REQUEST 5
295
306
typedef struct IDEState {
296
307
/* ide config */
297
308
int is_cdrom;
309
int is_cf;
298
310
int cylinders, heads, sectors;
299
311
int64_t nb_sectors;
300
312
int mult_sectors;
301
313
int identify_set;
302
314
uint16_t identify_data[256];
303
SetIRQFunc *set_irq;
304
void *irq_opaque;
305
int irq;
315
qemu_irq irq;
306
316
PCIDevice *pci_dev;
307
317
struct BMDMAState *bmdma;
308
318
int drive_serial;
349
359
uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
350
360
QEMUTimer *sector_write_timer; /* only used for win2k instal hack */
351
361
uint32_t irq_count; /* counts IRQs when using win2k install hack */
362
/* CF-ATA extended error */
363
uint8_t ext_error;
364
/* CF-ATA metadata storage */
365
uint32_t mdata_size;
366
uint8_t *mdata_storage;
367
int media_changed;
352
368
} IDEState;
353
369
354
370
#define BM_STATUS_DMAING 0x01
360
376
361
377
#define IDE_TYPE_PIIX3 0
362
378
#define IDE_TYPE_CMD646 1
379
#define IDE_TYPE_PIIX4 2
363
380
364
381
/* CMD646 specific */
365
382
#define MRDMODE 0x71
544
561
s->identify_set = 1;
545
562
}
546
563
564
static void ide_cfata_identify(IDEState *s)
565
{
566
uint16_t *p;
567
uint32_t cur_sec;
568
char buf[20];
569
570
p = (uint16_t *) s->identify_data;
571
if (s->identify_set)
572
goto fill_buffer;
573
574
memset(p, 0, sizeof(s->identify_data));
575
576
cur_sec = s->cylinders * s->heads * s->sectors;
577
578
put_le16(p + 0, 0x848a); /* CF Storage Card signature */
579
put_le16(p + 1, s->cylinders); /* Default cylinders */
580
put_le16(p + 3, s->heads); /* Default heads */
581
put_le16(p + 6, s->sectors); /* Default sectors per track */
582
put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
583
put_le16(p + 8, s->nb_sectors); /* Sectors per card */
584
snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
585
padstr((uint8_t *)(p + 10), buf, 20); /* Serial number in ASCII */
586
put_le16(p + 22, 0x0004); /* ECC bytes */
587
padstr((uint8_t *) (p + 23), QEMU_VERSION, 8); /* Firmware Revision */
588
padstr((uint8_t *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
589
#if MAX_MULT_SECTORS > 1
590
put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
591
#else
592
put_le16(p + 47, 0x0000);
593
#endif
594
put_le16(p + 49, 0x0f00); /* Capabilities */
595
put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
596
put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
597
put_le16(p + 53, 0x0003); /* Translation params valid */
598
put_le16(p + 54, s->cylinders); /* Current cylinders */
599
put_le16(p + 55, s->heads); /* Current heads */
600
put_le16(p + 56, s->sectors); /* Current sectors */
601
put_le16(p + 57, cur_sec); /* Current capacity */
602
put_le16(p + 58, cur_sec >> 16); /* Current capacity */
603
if (s->mult_sectors) /* Multiple sector setting */
604
put_le16(p + 59, 0x100 | s->mult_sectors);
605
put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
606
put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
607
put_le16(p + 63, 0x0203); /* Multiword DMA capability */
608
put_le16(p + 64, 0x0001); /* Flow Control PIO support */
609
put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
610
put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
611
put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
612
put_le16(p + 82, 0x400c); /* Command Set supported */
613
put_le16(p + 83, 0x7068); /* Command Set supported */
614
put_le16(p + 84, 0x4000); /* Features supported */
615
put_le16(p + 85, 0x000c); /* Command Set enabled */
616
put_le16(p + 86, 0x7044); /* Command Set enabled */
617
put_le16(p + 87, 0x4000); /* Features enabled */
618
put_le16(p + 91, 0x4060); /* Current APM level */
619
put_le16(p + 129, 0x0002); /* Current features option */
620
put_le16(p + 130, 0x0005); /* Reassigned sectors */
621
put_le16(p + 131, 0x0001); /* Initial power mode */
622
put_le16(p + 132, 0x0000); /* User signature */
623
put_le16(p + 160, 0x8100); /* Power requirement */
624
put_le16(p + 161, 0x8001); /* CF command set */
625
626
s->identify_set = 1;
627
628
fill_buffer:
629
memcpy(s->io_buffer, p, sizeof(s->identify_data));
630
}
631
547
632
static void ide_set_signature(IDEState *s)
548
633
{
549
634
s->select &= 0xf0; /* clear head */
575
660
if (bm) {
576
661
bm->status |= BM_STATUS_INT;
577
662
}
578
s->set_irq(s->irq_opaque, s->irq, 1);
663
qemu_irq_raise(s->irq);
579
664
}
580
665
}
581
666
794
879
ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
795
880
s->nsector -= n;
796
881
if (s->nsector == 0) {
797
/* no more sector to write */
882
/* no more sectors to write */
798
883
ide_transfer_stop(s);
799
884
} else {
800
885
n1 = s->nsector;
1482
1567
buf[1] = 0x80; /* removable */
1483
1568
buf[2] = 0x00; /* ISO */
1484
1569
buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1485
buf[4] = 31; /* additionnal length */
1570
buf[4] = 31; /* additional length */
1486
1571
buf[5] = 0; /* reserved */
1487
1572
buf[6] = 0; /* reserved */
1488
1573
buf[7] = 0; /* reserved */
1498
1583
}
1499
1584
}
1500
1585
1586
static void ide_cfata_metadata_inquiry(IDEState *s)
1587
{
1588
uint16_t *p;
1589
uint32_t spd;
1590
1591
p = (uint16_t *) s->io_buffer;
1592
memset(p, 0, 0x200);
1593
spd = ((s->mdata_size - 1) >> 9) + 1;
1594
1595
put_le16(p + 0, 0x0001); /* Data format revision */
1596
put_le16(p + 1, 0x0000); /* Media property: silicon */
1597
put_le16(p + 2, s->media_changed); /* Media status */
1598
put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1599
put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1600
put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1601
put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1602
}
1603
1604
static void ide_cfata_metadata_read(IDEState *s)
1605
{
1606
uint16_t *p;
1607
1608
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1609
s->status = ERR_STAT;
1610
s->error = ABRT_ERR;
1611
return;
1612
}
1613
1614
p = (uint16_t *) s->io_buffer;
1615
memset(p, 0, 0x200);
1616
1617
put_le16(p + 0, s->media_changed); /* Media status */
1618
memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1619
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1620
s->nsector << 9), 0x200 - 2));
1621
}
1622
1623
static void ide_cfata_metadata_write(IDEState *s)
1624
{
1625
if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1626
s->status = ERR_STAT;
1627
s->error = ABRT_ERR;
1628
return;
1629
}
1630
1631
s->media_changed = 0;
1632
1633
memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1634
s->io_buffer + 2,
1635
MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1636
s->nsector << 9), 0x200 - 2));
1637
}
1638
1501
1639
/* called when the inserted state of the media has changed */
1502
1640
static void cdrom_change_cb(void *opaque)
1503
1641
{
1613
1751
switch(val) {
1614
1752
case WIN_IDENTIFY:
1615
1753
if (s->bs && !s->is_cdrom) {
1616
ide_identify(s);
1754
if (!s->is_cf)
1755
ide_identify(s);
1756
else
1757
ide_cfata_identify(s);
1617
1758
s->status = READY_STAT | SEEK_STAT;
1618
1759
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1619
1760
} else {
1631
1772
ide_set_irq(s);
1632
1773
break;
1633
1774
case WIN_SETMULT:
1634
if (s->nsector > MAX_MULT_SECTORS ||
1635
s->nsector == 0 ||
1636
(s->nsector & (s->nsector - 1)) != 0) {
1775
if (s->is_cf && s->nsector == 0) {
1776
/* Disable Read and Write Multiple */
1777
s->mult_sectors = 0;
1778
s->status = READY_STAT;
1779
} else if ((s->nsector & 0xff) != 0 &&
1780
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1781
(s->nsector & (s->nsector - 1)) != 0)) {
1637
1782
ide_abort_command(s);
1638
1783
} else {
1639
s->mult_sectors = s->nsector;
1784
s->mult_sectors = s->nsector & 0xff;
1640
1785
s->status = READY_STAT;
1641
1786
}
1642
1787
ide_set_irq(s);
1664
1809
lba48 = 1;
1665
1810
case WIN_WRITE:
1666
1811
case WIN_WRITE_ONCE:
1812
case CFA_WRITE_SECT_WO_ERASE:
1813
case WIN_WRITE_VERIFY:
1667
1814
ide_cmd_lba48_transform(s, lba48);
1668
1815
s->error = 0;
1669
1816
s->status = SEEK_STAT | READY_STAT;
1670
1817
s->req_nb_sectors = 1;
1671
1818
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1819
s->media_changed = 1;
1672
1820
break;
1673
1821
case WIN_MULTREAD_EXT:
1674
1822
lba48 = 1;
1682
1830
case WIN_MULTWRITE_EXT:
1683
1831
lba48 = 1;
1684
1832
case WIN_MULTWRITE:
1833
case CFA_WRITE_MULTI_WO_ERASE:
1685
1834
if (!s->mult_sectors)
1686
1835
goto abort_cmd;
1687
1836
ide_cmd_lba48_transform(s, lba48);
1692
1841
if (n > s->req_nb_sectors)
1693
1842
n = s->req_nb_sectors;
1694
1843
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1844
s->media_changed = 1;
1695
1845
break;
1696
1846
case WIN_READDMA_EXT:
1697
1847
lba48 = 1;
1710
1860
goto abort_cmd;
1711
1861
ide_cmd_lba48_transform(s, lba48);
1712
1862
ide_sector_write_dma(s);
1863
s->media_changed = 1;
1713
1864
break;
1714
1865
case WIN_READ_NATIVE_MAX_EXT:
1715
1866
lba48 = 1;
1720
1871
ide_set_irq(s);
1721
1872
break;
1722
1873
case WIN_CHECKPOWERMODE1:
1874
case WIN_CHECKPOWERMODE2:
1723
1875
s->nsector = 0xff; /* device active or idle */
1724
1876
s->status = READY_STAT;
1725
1877
ide_set_irq(s);
1729
1881
goto abort_cmd;
1730
1882
/* XXX: valid for CDROM ? */
1731
1883
switch(s->feature) {
1884
case 0xcc: /* reverting to power-on defaults enable */
1885
case 0x66: /* reverting to power-on defaults disable */
1732
1886
case 0x02: /* write cache enable */
1733
1887
case 0x82: /* write cache disable */
1734
1888
case 0xaa: /* read look-ahead enable */
1735
1889
case 0x55: /* read look-ahead disable */
1890
case 0x05: /* set advanced power management mode */
1891
case 0x85: /* disable advanced power management mode */
1892
case 0x69: /* NOP */
1893
case 0x67: /* NOP */
1894
case 0x96: /* NOP */
1895
case 0x9a: /* NOP */
1736
1896
s->status = READY_STAT | SEEK_STAT;
1737
1897
ide_set_irq(s);
1738
1898
break;
1772
1932
ide_set_irq(s);
1773
1933
break;
1774
1934
case WIN_STANDBYNOW1:
1935
case WIN_STANDBYNOW2:
1775
1936
case WIN_IDLEIMMEDIATE:
1937
case CFA_IDLEIMMEDIATE:
1938
case WIN_SETIDLE1:
1939
case WIN_SETIDLE2:
1776
1940
s->status = READY_STAT;
1777
1941
ide_set_irq(s);
1778
1942
break;
1810
1974
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1811
1975
ide_atapi_cmd);
1812
1976
break;
1977
/* CF-ATA commands */
1978
case CFA_REQ_EXT_ERROR_CODE:
1979
if (!s->is_cf)
1980
goto abort_cmd;
1981
s->error = 0x09; /* miscellaneous error */
1982
s->status = READY_STAT;
1983
ide_set_irq(s);
1984
break;
1985
case CFA_ERASE_SECTORS:
1986
case CFA_WEAR_LEVEL:
1987
if (!s->is_cf)
1988
goto abort_cmd;
1989
if (val == CFA_WEAR_LEVEL)
1990
s->nsector = 0;
1991
if (val == CFA_ERASE_SECTORS)
1992
s->media_changed = 1;
1993
s->error = 0x00;
1994
s->status = READY_STAT;
1995
ide_set_irq(s);
1996
break;
1997
case CFA_TRANSLATE_SECTOR:
1998
if (!s->is_cf)
1999
goto abort_cmd;
2000
s->error = 0x00;
2001
s->status = READY_STAT;
2002
memset(s->io_buffer, 0, 0x200);
2003
s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
2004
s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
2005
s->io_buffer[0x02] = s->select; /* Head */
2006
s->io_buffer[0x03] = s->sector; /* Sector */
2007
s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
2008
s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
2009
s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
2010
s->io_buffer[0x13] = 0x00; /* Erase flag */
2011
s->io_buffer[0x18] = 0x00; /* Hot count */
2012
s->io_buffer[0x19] = 0x00; /* Hot count */
2013
s->io_buffer[0x1a] = 0x01; /* Hot count */
2014
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2015
ide_set_irq(s);
2016
break;
2017
case CFA_ACCESS_METADATA_STORAGE:
2018
if (!s->is_cf)
2019
goto abort_cmd;
2020
switch (s->feature) {
2021
case 0x02: /* Inquiry Metadata Storage */
2022
ide_cfata_metadata_inquiry(s);
2023
break;
2024
case 0x03: /* Read Metadata Storage */
2025
ide_cfata_metadata_read(s);
2026
break;
2027
case 0x04: /* Write Metadata Storage */
2028
ide_cfata_metadata_write(s);
2029
break;
2030
default:
2031
goto abort_cmd;
2032
}
2033
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2034
s->status = 0x00; /* NOTE: READY is _not_ set */
2035
ide_set_irq(s);
2036
break;
2037
case IBM_SENSE_CONDITION:
2038
if (!s->is_cf)
2039
goto abort_cmd;
2040
switch (s->feature) {
2041
case 0x01: /* sense temperature in device */
2042
s->nsector = 0x50; /* +20 C */
2043
break;
2044
default:
2045
goto abort_cmd;
2046
}
2047
s->status = READY_STAT;
2048
ide_set_irq(s);
2049
break;
1813
2050
default:
1814
2051
abort_cmd:
1815
2052
ide_abort_command(s);
1887
2124
ret = 0;
1888
2125
else
1889
2126
ret = s->status;
1890
s->set_irq(s->irq_opaque, s->irq, 0);
2127
qemu_irq_lower(s->irq);
1891
2128
break;
1892
2129
}
1893
2130
#ifdef DEBUG_IDE
2015
2252
2016
2253
static void ide_reset(IDEState *s)
2017
2254
{
2018
s->mult_sectors = MAX_MULT_SECTORS;
2255
if (s->is_cf)
2256
s->mult_sectors = 0;
2257
else
2258
s->mult_sectors = MAX_MULT_SECTORS;
2019
2259
s->cur_drive = s;
2020
2260
s->select = 0xa0;
2021
2261
s->status = READY_STAT;
2024
2264
accesses */
2025
2265
s->end_transfer_func = ide_dummy_transfer_stop;
2026
2266
ide_dummy_transfer_stop(s);
2267
s->media_changed = 0;
2027
2268
}
2028
2269
2029
2270
struct partition {
2082
2323
2083
2324
static void ide_init2(IDEState *ide_state,
2084
2325
BlockDriverState *hd0, BlockDriverState *hd1,
2085
SetIRQFunc *set_irq, void *irq_opaque, int irq)
2326
qemu_irq irq)
2086
2327
{
2087
2328
IDEState *s;
2088
2329
static int drive_serial = 1;
2153
2394
}
2154
2395
}
2155
2396
s->drive_serial = drive_serial++;
2156
s->set_irq = set_irq;
2157
s->irq_opaque = irq_opaque;
2158
2397
s->irq = irq;
2159
2398
s->sector_write_timer = qemu_new_timer(vm_clock,
2160
2399
ide_sector_write_timer_cb, s);
2178
2417
register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
2179
2418
}
2180
2419
2420
/* save per IDE drive data */
2421
static void ide_save(QEMUFile* f, IDEState *s)
2422
{
2423
qemu_put_be32s(f, &s->mult_sectors);
2424
qemu_put_be32s(f, &s->identify_set);
2425
if (s->identify_set) {
2426
qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2427
}
2428
qemu_put_8s(f, &s->feature);
2429
qemu_put_8s(f, &s->error);
2430
qemu_put_be32s(f, &s->nsector);
2431
qemu_put_8s(f, &s->sector);
2432
qemu_put_8s(f, &s->lcyl);
2433
qemu_put_8s(f, &s->hcyl);
2434
qemu_put_8s(f, &s->hob_feature);
2435
qemu_put_8s(f, &s->hob_nsector);
2436
qemu_put_8s(f, &s->hob_sector);
2437
qemu_put_8s(f, &s->hob_lcyl);
2438
qemu_put_8s(f, &s->hob_hcyl);
2439
qemu_put_8s(f, &s->select);
2440
qemu_put_8s(f, &s->status);
2441
qemu_put_8s(f, &s->lba48);
2442
2443
qemu_put_8s(f, &s->sense_key);
2444
qemu_put_8s(f, &s->asc);
2445
/* XXX: if a transfer is pending, we do not save it yet */
2446
}
2447
2448
/* load per IDE drive data */
2449
static void ide_load(QEMUFile* f, IDEState *s)
2450
{
2451
qemu_get_be32s(f, &s->mult_sectors);
2452
qemu_get_be32s(f, &s->identify_set);
2453
if (s->identify_set) {
2454
qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2455
}
2456
qemu_get_8s(f, &s->feature);
2457
qemu_get_8s(f, &s->error);
2458
qemu_get_be32s(f, &s->nsector);
2459
qemu_get_8s(f, &s->sector);
2460
qemu_get_8s(f, &s->lcyl);
2461
qemu_get_8s(f, &s->hcyl);
2462
qemu_get_8s(f, &s->hob_feature);
2463
qemu_get_8s(f, &s->hob_nsector);
2464
qemu_get_8s(f, &s->hob_sector);
2465
qemu_get_8s(f, &s->hob_lcyl);
2466
qemu_get_8s(f, &s->hob_hcyl);
2467
qemu_get_8s(f, &s->select);
2468
qemu_get_8s(f, &s->status);
2469
qemu_get_8s(f, &s->lba48);
2470
2471
qemu_get_8s(f, &s->sense_key);
2472
qemu_get_8s(f, &s->asc);
2473
/* XXX: if a transfer is pending, we do not save it yet */
2474
}
2475
2181
2476
/***********************************************************/
2182
2477
/* ISA IDE definitions */
2183
2478
2184
void isa_ide_init(int iobase, int iobase2, int irq,
2479
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
2185
2480
BlockDriverState *hd0, BlockDriverState *hd1)
2186
2481
{
2187
2482
IDEState *ide_state;
2190
2485
if (!ide_state)
2191
2486
return;
2192
2487
2193
ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq);
2488
ide_init2(ide_state, hd0, hd1, irq);
2194
2489
ide_init_ioport(ide_state, iobase, iobase2);
2195
2490
}
2196
2491
2397
2692
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
2398
2693
((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
2399
2694
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
2400
pci_set_irq((PCIDevice *)d, 0, pci_level);
2695
qemu_set_irq(d->dev.irq[0], pci_level);
2401
2696
}
2402
2697
2403
2698
/* the PCI irq level is the logical OR of the two channels */
2421
2716
PCIIDEState *d;
2422
2717
uint8_t *pci_conf;
2423
2718
int i;
2719
qemu_irq *irq;
2424
2720
2425
2721
d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
2426
2722
sizeof(PCIIDEState),
2460
2756
2461
2757
for(i = 0; i < 4; i++)
2462
2758
d->ide_if[i].pci_dev = (PCIDevice *)d;
2463
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
2464
cmd646_set_irq, d, 0);
2465
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
2466
cmd646_set_irq, d, 1);
2759
2760
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
2761
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
2762
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
2467
2763
}
2468
2764
2469
2765
static void pci_ide_save(QEMUFile* f, void *opaque)
2492
2788
2493
2789
/* per IDE drive data */
2494
2790
for(i = 0; i < 4; i++) {
2495
IDEState *s = &d->ide_if[i];
2496
qemu_put_be32s(f, &s->mult_sectors);
2497
qemu_put_be32s(f, &s->identify_set);
2498
if (s->identify_set) {
2499
qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2500
}
2501
qemu_put_8s(f, &s->feature);
2502
qemu_put_8s(f, &s->error);
2503
qemu_put_be32s(f, &s->nsector);
2504
qemu_put_8s(f, &s->sector);
2505
qemu_put_8s(f, &s->lcyl);
2506
qemu_put_8s(f, &s->hcyl);
2507
qemu_put_8s(f, &s->hob_feature);
2508
qemu_put_8s(f, &s->hob_nsector);
2509
qemu_put_8s(f, &s->hob_sector);
2510
qemu_put_8s(f, &s->hob_lcyl);
2511
qemu_put_8s(f, &s->hob_hcyl);
2512
qemu_put_8s(f, &s->select);
2513
qemu_put_8s(f, &s->status);
2514
qemu_put_8s(f, &s->lba48);
2515
2516
qemu_put_8s(f, &s->sense_key);
2517
qemu_put_8s(f, &s->asc);
2518
/* XXX: if a transfer is pending, we do not save it yet */
2791
ide_save(f, &d->ide_if[i]);
2519
2792
}
2520
2793
}
2521
2794
2549
2822
2550
2823
/* per IDE drive data */
2551
2824
for(i = 0; i < 4; i++) {
2552
IDEState *s = &d->ide_if[i];
2553
qemu_get_be32s(f, &s->mult_sectors);
2554
qemu_get_be32s(f, &s->identify_set);
2555
if (s->identify_set) {
2556
qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2557
}
2558
qemu_get_8s(f, &s->feature);
2559
qemu_get_8s(f, &s->error);
2560
qemu_get_be32s(f, &s->nsector);
2561
qemu_get_8s(f, &s->sector);
2562
qemu_get_8s(f, &s->lcyl);
2563
qemu_get_8s(f, &s->hcyl);
2564
qemu_get_8s(f, &s->hob_feature);
2565
qemu_get_8s(f, &s->hob_nsector);
2566
qemu_get_8s(f, &s->hob_sector);
2567
qemu_get_8s(f, &s->hob_lcyl);
2568
qemu_get_8s(f, &s->hob_hcyl);
2569
qemu_get_8s(f, &s->select);
2570
qemu_get_8s(f, &s->status);
2571
qemu_get_8s(f, &s->lba48);
2572
2573
qemu_get_8s(f, &s->sense_key);
2574
qemu_get_8s(f, &s->asc);
2575
/* XXX: if a transfer is pending, we do not save it yet */
2825
ide_load(f, &d->ide_if[i]);
2576
2826
}
2577
2827
return 0;
2578
2828
}
2588
2838
pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
2589
2839
}
2590
2840
2591
void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
2592
{
2593
PCIIDEState *d;
2594
uint8_t *pci_conf;
2595
2596
/* register a function 1 of PIIX */
2597
d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE",
2598
sizeof(PCIIDEState),
2599
devfn,
2600
NULL, NULL);
2601
d->type = IDE_TYPE_PIIX3;
2602
2603
pci_conf = d->dev.config;
2604
pci_conf[0x00] = 0x86; // Intel
2605
pci_conf[0x01] = 0x80;
2606
pci_conf[0x02] = 0x30;
2607
pci_conf[0x03] = 0x12;
2608
pci_conf[0x08] = 0x02; // Step A1
2609
pci_conf[0x09] = 0x80; // legacy ATA mode
2610
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2611
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2612
pci_conf[0x0e] = 0x00; // header_type
2613
2614
piix3_reset(d);
2615
2616
pci_register_io_region((PCIDevice *)d, 4, 0x10,
2617
PCI_ADDRESS_SPACE_IO, bmdma_map);
2618
2619
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
2620
pic_set_irq_new, isa_pic, 14);
2621
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
2622
pic_set_irq_new, isa_pic, 15);
2623
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2624
ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2625
2626
register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2627
}
2628
2629
2841
/* hd_table must contain 4 block drivers */
2630
2842
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2631
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
2843
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2844
qemu_irq *pic)
2632
2845
{
2633
2846
PCIIDEState *d;
2634
2847
uint8_t *pci_conf;
2655
2868
pci_register_io_region((PCIDevice *)d, 4, 0x10,
2656
2869
PCI_ADDRESS_SPACE_IO, bmdma_map);
2657
2870
2658
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
2659
pic_set_irq_new, isa_pic, 14);
2660
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
2661
pic_set_irq_new, isa_pic, 15);
2871
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2872
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2873
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2874
ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2875
2876
register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2877
}
2878
2879
/* hd_table must contain 4 block drivers */
2880
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
2881
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2882
qemu_irq *pic)
2883
{
2884
PCIIDEState *d;
2885
uint8_t *pci_conf;
2886
2887
/* register a function 1 of PIIX4 */
2888
d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
2889
sizeof(PCIIDEState),
2890
devfn,
2891
NULL, NULL);
2892
d->type = IDE_TYPE_PIIX4;
2893
2894
pci_conf = d->dev.config;
2895
pci_conf[0x00] = 0x86; // Intel
2896
pci_conf[0x01] = 0x80;
2897
pci_conf[0x02] = 0x11;
2898
pci_conf[0x03] = 0x71;
2899
pci_conf[0x09] = 0x80; // legacy ATA mode
2900
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2901
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2902
pci_conf[0x0e] = 0x00; // header_type
2903
2904
piix3_reset(d);
2905
2906
pci_register_io_region((PCIDevice *)d, 4, 0x10,
2907
PCI_ADDRESS_SPACE_IO, bmdma_map);
2908
2909
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2910
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2662
2911
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2663
2912
ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2664
2913
2777
3026
/* hd_table must contain 4 block drivers */
2778
3027
/* PowerMac uses memory mapped registers, not I/O. Return the memory
2779
3028
I/O index to access the ide. */
2780
int pmac_ide_init (BlockDriverState **hd_table,
2781
SetIRQFunc *set_irq, void *irq_opaque, int irq)
3029
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
2782
3030
{
2783
3031
IDEState *ide_if;
2784
3032
int pmac_ide_memory;
2785
3033
2786
3034
ide_if = qemu_mallocz(sizeof(IDEState) * 2);
2787
ide_init2(&ide_if[0], hd_table[0], hd_table[1],
2788
set_irq, irq_opaque, irq);
3035
ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
2789
3036
2790
3037
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
2791
3038
pmac_ide_write, &ide_if[0]);
2792
3039
return pmac_ide_memory;
2793
3040
}
3041
3042
/***********************************************************/
3043
/* CF-ATA Microdrive */
3044
3045
#define METADATA_SIZE 0x20
3046
3047
/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
3048
struct md_s {
3049
IDEState ide[2];
3050
struct pcmcia_card_s card;
3051
uint32_t attr_base;
3052
uint32_t io_base;
3053
3054
/* Card state */
3055
uint8_t opt;
3056
uint8_t stat;
3057
uint8_t pins;
3058
3059
uint8_t ctrl;
3060
uint16_t io;
3061
int cycle;
3062
};
3063
3064
/* Register bitfields */
3065
enum md_opt {
3066
OPT_MODE_MMAP = 0,
3067
OPT_MODE_IOMAP16 = 1,
3068
OPT_MODE_IOMAP1 = 2,
3069
OPT_MODE_IOMAP2 = 3,
3070
OPT_MODE = 0x3f,
3071
OPT_LEVIREQ = 0x40,
3072
OPT_SRESET = 0x80,
3073
};
3074
enum md_cstat {
3075
STAT_INT = 0x02,
3076
STAT_PWRDWN = 0x04,
3077
STAT_XE = 0x10,
3078
STAT_IOIS8 = 0x20,
3079
STAT_SIGCHG = 0x40,
3080
STAT_CHANGED = 0x80,
3081
};
3082
enum md_pins {
3083
PINS_MRDY = 0x02,
3084
PINS_CRDY = 0x20,
3085
};
3086
enum md_ctrl {
3087
CTRL_IEN = 0x02,
3088
CTRL_SRST = 0x04,
3089
};
3090
3091
static inline void md_interrupt_update(struct md_s *s)
3092
{
3093
if (!s->card.slot)
3094
return;
3095
3096
qemu_set_irq(s->card.slot->irq,
3097
!(s->stat & STAT_INT) && /* Inverted */
3098
!(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
3099
!(s->opt & OPT_SRESET));
3100
}
3101
3102
static void md_set_irq(void *opaque, int irq, int level)
3103
{
3104
struct md_s *s = (struct md_s *) opaque;
3105
if (level)
3106
s->stat |= STAT_INT;
3107
else
3108
s->stat &= ~STAT_INT;
3109
3110
md_interrupt_update(s);
3111
}
3112
3113
static void md_reset(struct md_s *s)
3114
{
3115
s->opt = OPT_MODE_MMAP;
3116
s->stat = 0;
3117
s->pins = 0;
3118
s->cycle = 0;
3119
s->ctrl = 0;
3120
ide_reset(s->ide);
3121
}
3122
3123
static uint8_t md_attr_read(void *opaque, uint32_t at)
3124
{
3125
struct md_s *s = (struct md_s *) opaque;
3126
if (at < s->attr_base) {
3127
if (at < s->card.cis_len)
3128
return s->card.cis[at];
3129
else
3130
return 0x00;
3131
}
3132
3133
at -= s->attr_base;
3134
3135
switch (at) {
3136
case 0x00: /* Configuration Option Register */
3137
return s->opt;
3138
case 0x02: /* Card Configuration Status Register */
3139
if (s->ctrl & CTRL_IEN)
3140
return s->stat & ~STAT_INT;
3141
else
3142
return s->stat;
3143
case 0x04: /* Pin Replacement Register */
3144
return (s->pins & PINS_CRDY) | 0x0c;
3145
case 0x06: /* Socket and Copy Register */
3146
return 0x00;
3147
#ifdef VERBOSE
3148
default:
3149
printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3150
#endif
3151
}
3152
3153
return 0;
3154
}
3155
3156
static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
3157
{
3158
struct md_s *s = (struct md_s *) opaque;
3159
at -= s->attr_base;
3160
3161
switch (at) {
3162
case 0x00: /* Configuration Option Register */
3163
s->opt = value & 0xcf;
3164
if (value & OPT_SRESET)
3165
md_reset(s);
3166
md_interrupt_update(s);
3167
break;
3168
case 0x02: /* Card Configuration Status Register */
3169
if ((s->stat ^ value) & STAT_PWRDWN)
3170
s->pins |= PINS_CRDY;
3171
s->stat &= 0x82;
3172
s->stat |= value & 0x74;
3173
md_interrupt_update(s);
3174
/* Word 170 in Identify Device must be equal to STAT_XE */
3175
break;
3176
case 0x04: /* Pin Replacement Register */
3177
s->pins &= PINS_CRDY;
3178
s->pins |= value & PINS_MRDY;
3179
break;
3180
case 0x06: /* Socket and Copy Register */
3181
break;
3182
default:
3183
printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3184
}
3185
}
3186
3187
static uint16_t md_common_read(void *opaque, uint32_t at)
3188
{
3189
struct md_s *s = (struct md_s *) opaque;
3190
uint16_t ret;
3191
at -= s->io_base;
3192
3193
switch (s->opt & OPT_MODE) {
3194
case OPT_MODE_MMAP:
3195
if ((at & ~0x3ff) == 0x400)
3196
at = 0;
3197
break;
3198
case OPT_MODE_IOMAP16:
3199
at &= 0xf;
3200
break;
3201
case OPT_MODE_IOMAP1:
3202
if ((at & ~0xf) == 0x3f0)
3203
at -= 0x3e8;
3204
else if ((at & ~0xf) == 0x1f0)
3205
at -= 0x1f0;
3206
break;
3207
case OPT_MODE_IOMAP2:
3208
if ((at & ~0xf) == 0x370)
3209
at -= 0x368;
3210
else if ((at & ~0xf) == 0x170)
3211
at -= 0x170;
3212
}
3213
3214
switch (at) {
3215
case 0x0: /* Even RD Data */
3216
case 0x8:
3217
return ide_data_readw(s->ide, 0);
3218
3219
/* TODO: 8-bit accesses */
3220
if (s->cycle)
3221
ret = s->io >> 8;
3222
else {
3223
s->io = ide_data_readw(s->ide, 0);
3224
ret = s->io & 0xff;
3225
}
3226
s->cycle = !s->cycle;
3227
return ret;
3228
case 0x9: /* Odd RD Data */
3229
return s->io >> 8;
3230
case 0xd: /* Error */
3231
return ide_ioport_read(s->ide, 0x1);
3232
case 0xe: /* Alternate Status */
3233
if (s->ide->cur_drive->bs)
3234
return s->ide->cur_drive->status;
3235
else
3236
return 0;
3237
case 0xf: /* Device Address */
3238
return 0xc2 | ((~s->ide->select << 2) & 0x3c);
3239
default:
3240
return ide_ioport_read(s->ide, at);
3241
}
3242
3243
return 0;
3244
}
3245
3246
static void md_common_write(void *opaque, uint32_t at, uint16_t value)
3247
{
3248
struct md_s *s = (struct md_s *) opaque;
3249
at -= s->io_base;
3250
3251
switch (s->opt & OPT_MODE) {
3252
case OPT_MODE_MMAP:
3253
if ((at & ~0x3ff) == 0x400)
3254
at = 0;
3255
break;
3256
case OPT_MODE_IOMAP16:
3257
at &= 0xf;
3258
break;
3259
case OPT_MODE_IOMAP1:
3260
if ((at & ~0xf) == 0x3f0)
3261
at -= 0x3e8;
3262
else if ((at & ~0xf) == 0x1f0)
3263
at -= 0x1f0;
3264
break;
3265
case OPT_MODE_IOMAP2:
3266
if ((at & ~0xf) == 0x370)
3267
at -= 0x368;
3268
else if ((at & ~0xf) == 0x170)
3269
at -= 0x170;
3270
}
3271
3272
switch (at) {
3273
case 0x0: /* Even WR Data */
3274
case 0x8:
3275
ide_data_writew(s->ide, 0, value);
3276
break;
3277
3278
/* TODO: 8-bit accesses */
3279
if (s->cycle)
3280
ide_data_writew(s->ide, 0, s->io | (value << 8));
3281
else
3282
s->io = value & 0xff;
3283
s->cycle = !s->cycle;
3284
break;
3285
case 0x9:
3286
s->io = value & 0xff;
3287
s->cycle = !s->cycle;
3288
break;
3289
case 0xd: /* Features */
3290
ide_ioport_write(s->ide, 0x1, value);
3291
break;
3292
case 0xe: /* Device Control */
3293
s->ctrl = value;
3294
if (value & CTRL_SRST)
3295
md_reset(s);
3296
md_interrupt_update(s);
3297
break;
3298
default:
3299
if (s->stat & STAT_PWRDWN) {
3300
s->pins |= PINS_CRDY;
3301
s->stat &= ~STAT_PWRDWN;
3302
}
3303
ide_ioport_write(s->ide, at, value);
3304
}
3305
}
3306
3307
static void md_save(QEMUFile *f, void *opaque)
3308
{
3309
struct md_s *s = (struct md_s *) opaque;
3310
int i;
3311
uint8_t drive1_selected;
3312
3313
qemu_put_8s(f, &s->opt);
3314
qemu_put_8s(f, &s->stat);
3315
qemu_put_8s(f, &s->pins);
3316
3317
qemu_put_8s(f, &s->ctrl);
3318
qemu_put_be16s(f, &s->io);
3319
qemu_put_byte(f, s->cycle);
3320
3321
drive1_selected = (s->ide->cur_drive != s->ide);
3322
qemu_put_8s(f, &s->ide->cmd);
3323
qemu_put_8s(f, &drive1_selected);
3324
3325
for (i = 0; i < 2; i ++)
3326
ide_save(f, &s->ide[i]);
3327
}
3328
3329
static int md_load(QEMUFile *f, void *opaque, int version_id)
3330
{
3331
struct md_s *s = (struct md_s *) opaque;
3332
int i;
3333
uint8_t drive1_selected;
3334
3335
qemu_get_8s(f, &s->opt);
3336
qemu_get_8s(f, &s->stat);
3337
qemu_get_8s(f, &s->pins);
3338
3339
qemu_get_8s(f, &s->ctrl);
3340
qemu_get_be16s(f, &s->io);
3341
s->cycle = qemu_get_byte(f);
3342
3343
qemu_get_8s(f, &s->ide->cmd);
3344
qemu_get_8s(f, &drive1_selected);
3345
s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
3346
3347
for (i = 0; i < 2; i ++)
3348
ide_load(f, &s->ide[i]);
3349
3350
return 0;
3351
}
3352
3353
static int md_iid = 0;
3354
3355
static const uint8_t dscm1xxxx_cis[0x14a] = {
3356
[0x000] = CISTPL_DEVICE, /* 5V Device Information */
3357
[0x002] = 0x03, /* Tuple length = 4 bytes */
3358
[0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3359
[0x006] = 0x01, /* Size = 2K bytes */
3360
[0x008] = CISTPL_ENDMARK,
3361
3362
[0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
3363
[0x00c] = 0x04, /* Tuple length = 4 byest */
3364
[0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
3365
[0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3366
[0x012] = 0x01, /* Size = 2K bytes */
3367
[0x014] = CISTPL_ENDMARK,
3368
3369
[0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
3370
[0x018] = 0x02, /* Tuple length = 2 bytes */
3371
[0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
3372
[0x01c] = 0x01,
3373
3374
[0x01e] = CISTPL_MANFID, /* Manufacture ID */
3375
[0x020] = 0x04, /* Tuple length = 4 bytes */
3376
[0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
3377
[0x024] = 0x00,
3378
[0x026] = 0x00, /* PLMID_CARD = 0000 */
3379
[0x028] = 0x00,
3380
3381
[0x02a] = CISTPL_VERS_1, /* Level 1 Version */
3382
[0x02c] = 0x12, /* Tuple length = 23 bytes */
3383
[0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
3384
[0x030] = 0x01, /* Minor Version = 1 */
3385
[0x032] = 'I',
3386
[0x034] = 'B',
3387
[0x036] = 'M',
3388
[0x038] = 0x00,
3389
[0x03a] = 'm',
3390
[0x03c] = 'i',
3391
[0x03e] = 'c',
3392
[0x040] = 'r',
3393
[0x042] = 'o',
3394
[0x044] = 'd',
3395
[0x046] = 'r',
3396
[0x048] = 'i',
3397
[0x04a] = 'v',
3398
[0x04c] = 'e',
3399
[0x04e] = 0x00,
3400
[0x050] = CISTPL_ENDMARK,
3401
3402
[0x052] = CISTPL_FUNCID, /* Function ID */
3403
[0x054] = 0x02, /* Tuple length = 2 bytes */
3404
[0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
3405
[0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
3406
3407
[0x05a] = CISTPL_FUNCE, /* Function Extension */
3408
[0x05c] = 0x02, /* Tuple length = 2 bytes */
3409
[0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
3410
[0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
3411
3412
[0x062] = CISTPL_FUNCE, /* Function Extension */
3413
[0x064] = 0x03, /* Tuple length = 3 bytes */
3414
[0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
3415
[0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
3416
[0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
3417
3418
[0x06c] = CISTPL_CONFIG, /* Configuration */
3419
[0x06e] = 0x05, /* Tuple length = 5 bytes */
3420
[0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
3421
[0x072] = 0x07, /* TPCC_LAST = 7 */
3422
[0x074] = 0x00, /* TPCC_RADR = 0200 */
3423
[0x076] = 0x02,
3424
[0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
3425
3426
[0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3427
[0x07c] = 0x0b, /* Tuple length = 11 bytes */
3428
[0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
3429
[0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
3430
[0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
3431
[0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3432
[0x086] = 0x55, /* NomV: 5.0 V */
3433
[0x088] = 0x4d, /* MinV: 4.5 V */
3434
[0x08a] = 0x5d, /* MaxV: 5.5 V */
3435
[0x08c] = 0x4e, /* Peakl: 450 mA */
3436
[0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
3437
[0x090] = 0x00, /* Window descriptor: Window length = 0 */
3438
[0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
3439
3440
[0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3441
[0x096] = 0x06, /* Tuple length = 6 bytes */
3442
[0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
3443
[0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3444
[0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3445
[0x09e] = 0xb5, /* NomV: 3.3 V */
3446
[0x0a0] = 0x1e,
3447
[0x0a2] = 0x3e, /* Peakl: 350 mA */
3448
3449
[0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3450
[0x0a6] = 0x0d, /* Tuple length = 13 bytes */
3451
[0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
3452
[0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3453
[0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3454
[0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3455
[0x0b0] = 0x55, /* NomV: 5.0 V */
3456
[0x0b2] = 0x4d, /* MinV: 4.5 V */
3457
[0x0b4] = 0x5d, /* MaxV: 5.5 V */
3458
[0x0b6] = 0x4e, /* Peakl: 450 mA */
3459
[0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
3460
[0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
3461
[0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
3462
[0x0be] = 0xff, /* IRQ8..IRQ15 supported */
3463
[0x0c0] = 0x20, /* TPCE_MI = support power down mode */
3464
3465
[0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3466
[0x0c4] = 0x06, /* Tuple length = 6 bytes */
3467
[0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
3468
[0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3469
[0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3470
[0x0cc] = 0xb5, /* NomV: 3.3 V */
3471
[0x0ce] = 0x1e,
3472
[0x0d0] = 0x3e, /* Peakl: 350 mA */
3473
3474
[0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3475
[0x0d4] = 0x12, /* Tuple length = 18 bytes */
3476
[0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
3477
[0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3478
[0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3479
[0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3480
[0x0de] = 0x55, /* NomV: 5.0 V */
3481
[0x0e0] = 0x4d, /* MinV: 4.5 V */
3482
[0x0e2] = 0x5d, /* MaxV: 5.5 V */
3483
[0x0e4] = 0x4e, /* Peakl: 450 mA */
3484
[0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3485
[0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
3486
[0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
3487
[0x0ec] = 0x01,
3488
[0x0ee] = 0x07, /* Address block length = 8 */
3489
[0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
3490
[0x0f2] = 0x03,
3491
[0x0f4] = 0x01, /* Address block length = 2 */
3492
[0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3493
[0x0f8] = 0x20, /* TPCE_MI = support power down mode */
3494
3495
[0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3496
[0x0fc] = 0x06, /* Tuple length = 6 bytes */
3497
[0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
3498
[0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3499
[0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3500
[0x104] = 0xb5, /* NomV: 3.3 V */
3501
[0x106] = 0x1e,
3502
[0x108] = 0x3e, /* Peakl: 350 mA */
3503
3504
[0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3505
[0x10c] = 0x12, /* Tuple length = 18 bytes */
3506
[0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
3507
[0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3508
[0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3509
[0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3510
[0x116] = 0x55, /* NomV: 5.0 V */
3511
[0x118] = 0x4d, /* MinV: 4.5 V */
3512
[0x11a] = 0x5d, /* MaxV: 5.5 V */
3513
[0x11c] = 0x4e, /* Peakl: 450 mA */
3514
[0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3515
[0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
3516
[0x122] = 0x70, /* Field 1 address = 0x0170 */
3517
[0x124] = 0x01,
3518
[0x126] = 0x07, /* Address block length = 8 */
3519
[0x128] = 0x76, /* Field 2 address = 0x0376 */
3520
[0x12a] = 0x03,
3521
[0x12c] = 0x01, /* Address block length = 2 */
3522
[0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3523
[0x130] = 0x20, /* TPCE_MI = support power down mode */
3524
3525
[0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3526
[0x134] = 0x06, /* Tuple length = 6 bytes */
3527
[0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
3528
[0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3529
[0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3530
[0x13c] = 0xb5, /* NomV: 3.3 V */
3531
[0x13e] = 0x1e,
3532
[0x140] = 0x3e, /* Peakl: 350 mA */
3533
3534
[0x142] = CISTPL_NO_LINK, /* No Link */
3535
[0x144] = 0x00, /* Tuple length = 0 bytes */
3536
3537
[0x146] = CISTPL_END, /* Tuple End */
3538
};
3539
3540
static int dscm1xxxx_attach(void *opaque)
3541
{
3542
struct md_s *md = (struct md_s *) opaque;
3543
md->card.attr_read = md_attr_read;
3544
md->card.attr_write = md_attr_write;
3545
md->card.common_read = md_common_read;
3546
md->card.common_write = md_common_write;
3547
md->card.io_read = md_common_read;
3548
md->card.io_write = md_common_write;
3549
3550
md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
3551
md->io_base = 0x0;
3552
3553
md_reset(md);
3554
md_interrupt_update(md);
3555
3556
md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3557
return 0;
3558
}
3559
3560
static int dscm1xxxx_detach(void *opaque)
3561
{
3562
struct md_s *md = (struct md_s *) opaque;
3563
md_reset(md);
3564
return 0;
3565
}
3566
3567
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
3568
{
3569
struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
3570
md->card.state = md;
3571
md->card.attach = dscm1xxxx_attach;
3572
md->card.detach = dscm1xxxx_detach;
3573
md->card.cis = dscm1xxxx_cis;
3574
md->card.cis_len = sizeof(dscm1xxxx_cis);
3575
3576
ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
3577
md->ide->is_cf = 1;
3578
md->ide->mdata_size = METADATA_SIZE;
3579
md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
3580
3581
register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md);
3582
3583
return &md->card;
3584
}
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Version: 2.0.1