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Viewing changes to cpu-defs.h

Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816

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cpu-defs.h
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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#define TARGET_FMT_lx "%08x"
 
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#define TARGET_FMT_ld "%d"
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#elif TARGET_LONG_SIZE == 8
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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#define TARGET_FMT_lx "%016" PRIx64
 
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#define TARGET_FMT_ld "%" PRId64
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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#if TARGET_PHYS_ADDR_BITS == 32
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typedef uint32_t target_phys_addr_t;
 
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#define TARGET_FMT_plx "%08x"
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#elif TARGET_PHYS_ADDR_BITS == 64
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typedef uint64_t target_phys_addr_t;
 
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#define TARGET_FMT_plx "%016" PRIx64
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#else
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#error TARGET_PHYS_ADDR_BITS undefined
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#endif
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#define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
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#define MAX_BREAKPOINTS 32
 
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#define MAX_WATCHPOINTS 32
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#define TB_JMP_CACHE_BITS 12
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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    target_phys_addr_t addend; 
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} CPUTLBEntry;
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/* Alpha has 4 different running levels */
 
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#if defined(TARGET_ALPHA)
 
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#define NB_MMU_MODES 4
 
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#elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 
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#define NB_MMU_MODES 3
 
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#else
 
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#define NB_MMU_MODES 2
 
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#endif
 
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#define CPU_COMMON                                                      \
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    struct TranslationBlock *current_tb; /* currently executing TB  */  \
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    /* soft mmu support */                                              \
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    target_ulong mem_write_vaddr; /* target virtual addr at which the   \
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                                     memory was written */              \
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    /* 0 = kernel, 1 = user */                                          \
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    CPUTLBEntry tlb_table[2][CPU_TLB_SIZE];                             \
 
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    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
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    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
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                                                                        \
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    /* from this point: preserved by CPU reset */                       \
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    int nb_breakpoints;                                                 \
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    int singlestep_enabled;                                             \
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                                                                        \
 
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    struct {                                                            \
 
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        target_ulong vaddr;                                             \
 
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        target_phys_addr_t addend;                                      \
 
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    } watchpoint[MAX_WATCHPOINTS];                                      \
 
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    int nb_watchpoints;                                                 \
 
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    int watchpoint_hit;                                                 \
 
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                                                                        \
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    void *next_cpu; /* next CPU sharing TB cache */                     \
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    int cpu_index; /* CPU index (informative) */                        \
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    /* user data */                                                     \