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* OMAP on-chip MMC/SD host emulation.
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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target_phys_addr_t base;
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uint16_t blen_counter;
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uint16_t nblk_counter;
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static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
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qemu_set_irq(s->irq, !!(s->status & s->mask));
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static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
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if (!host->transfer && !host->fifo_len) {
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host->status &= 0xf3ff;
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if (host->fifo_len > host->af_level && host->ddir) {
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host->status &= 0xfbff;
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qemu_irq_raise(host->dma[1]);
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host->status |= 0x0400;
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host->status &= 0xfbff;
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qemu_irq_lower(host->dma[1]);
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if (host->fifo_len < host->ae_level && !host->ddir) {
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host->status &= 0xf7ff;
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qemu_irq_raise(host->dma[0]);
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host->status |= 0x0800;
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qemu_irq_lower(host->dma[0]);
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host->status &= 0xf7ff;
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sd_nore = 0, /* no response */
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sd_r1, /* normal response command */
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sd_r2, /* CID, CSD registers */
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sd_r3, /* OCR register */
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sd_r6 = 6, /* Published RCA response */
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static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
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sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
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uint32_t rspstatus, mask;
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struct sd_request_s request;
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uint8_t response[16];
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if (resptype == sd_r1 && busy)
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if (type == sd_adtc) {
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host->fifo_start = 0;
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request.arg = host->arg;
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request.crc = 0; /* FIXME */
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rsplen = sd_do_command(host->card, &request, response);
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/* TODO: validate CRCs */
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mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
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ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
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LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
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CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
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if (host->sdio & (1 << 13))
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mask |= AKE_SEQ_ERROR;
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rspstatus = (response[0] << 24) | (response[1] << 16) |
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(response[2] << 8) | (response[3] << 0);
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rspstatus = (response[0] << 24) | (response[1] << 16) |
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(response[2] << 8) | (response[3] << 0);
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if (rspstatus & 0x80000000)
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host->status &= 0xe000;
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host->status |= 0x1000;
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mask = 0xe000 | AKE_SEQ_ERROR;
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rspstatus = (response[2] << 8) | (response[3] << 0);
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if (rspstatus & mask)
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host->status |= 0x4000;
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host->status &= 0xb000;
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for (rsplen = 0; rsplen < 8; rsplen ++)
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host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
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(response[(rsplen << 1) | 0] << 8);
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host->status |= 0x0080;
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host->status |= 0x0005; /* Makes it more real */
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host->status |= 0x0001;
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static void omap_mmc_transfer(struct omap_mmc_s *host)
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if (host->fifo_len > host->af_level)
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value = sd_read_data(host->card);
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host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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if (-- host->blen_counter) {
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value = sd_read_data(host->card);
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host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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host->blen_counter --;
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value = host->fifo[host->fifo_start] & 0xff;
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sd_write_data(host->card, value);
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if (-- host->blen_counter) {
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value = host->fifo[host->fifo_start] >> 8;
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sd_write_data(host->card, value);
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host->blen_counter --;
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host->fifo_start &= 31;
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if (host->blen_counter == 0) {
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host->nblk_counter --;
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host->blen_counter = host->blen;
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if (host->nblk_counter == 0) {
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host->nblk_counter = host->nblk;
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host->status |= 0x0008;
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static void omap_mmc_update(void *opaque)
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struct omap_mmc_s *s = opaque;
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omap_mmc_transfer(s);
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
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struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
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case 0x00: /* MMC_CMD */
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case 0x04: /* MMC_ARGL */
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return s->arg & 0x0000ffff;
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case 0x08: /* MMC_ARGH */
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case 0x0c: /* MMC_CON */
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return (s->dw << 15) | (s->mode << 12) | (s->enable << 11);
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case 0x10: /* MMC_STAT */
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case 0x14: /* MMC_IE */
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case 0x18: /* MMC_CTO */
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case 0x1c: /* MMC_DTO */
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case 0x20: /* MMC_DATA */
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/* TODO: support 8-bit access */
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i = s->fifo[s->fifo_start];
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if (s->fifo_len == 0) {
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printf("MMC: FIFO underrun\n");
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omap_mmc_transfer(s);
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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case 0x24: /* MMC_BLEN */
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return s->blen_counter;
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case 0x28: /* MMC_NBLK */
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return s->nblk_counter;
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case 0x2c: /* MMC_BUF */
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return (s->rx_dma << 15) | (s->af_level << 8) |
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(s->tx_dma << 7) | s->ae_level;
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case 0x30: /* MMC_SPI */
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case 0x34: /* MMC_SDIO */
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case 0x38: /* MMC_SYST */
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case 0x3c: /* MMC_REV */
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case 0x40: /* MMC_RSP0 */
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case 0x44: /* MMC_RSP1 */
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case 0x48: /* MMC_RSP2 */
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case 0x4c: /* MMC_RSP3 */
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case 0x50: /* MMC_RSP4 */
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case 0x54: /* MMC_RSP5 */
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case 0x58: /* MMC_RSP6 */
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case 0x5c: /* MMC_RSP7 */
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return s->rsp[(offset - 0x40) >> 2];
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OMAP_BAD_REG(offset);
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static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
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struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
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case 0x00: /* MMC_CMD */
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for (i = 0; i < 8; i ++)
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omap_mmc_command(s, value & 63, (value >> 15) & 1,
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(sd_cmd_type_t) ((value >> 12) & 3),
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(sd_rsp_type_t) ((value >> 8) & 7),
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case 0x04: /* MMC_ARGL */
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s->arg &= 0xffff0000;
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s->arg |= 0x0000ffff & value;
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case 0x08: /* MMC_ARGH */
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s->arg &= 0x0000ffff;
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s->arg |= value << 16;
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case 0x0c: /* MMC_CON */
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s->dw = (value >> 15) & 1;
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s->mode = (value >> 12) & 3;
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s->enable = (value >> 11) & 1;
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printf("SD mode %i unimplemented!\n", s->mode);
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printf("4-bit SD bus enabled\n");
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case 0x10: /* MMC_STAT */
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omap_mmc_interrupts_update(s);
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case 0x14: /* MMC_IE */
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omap_mmc_interrupts_update(s);
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case 0x18: /* MMC_CTO */
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s->cto = value & 0xff;
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printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
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case 0x1c: /* MMC_DTO */
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s->dto = value & 0xffff;
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case 0x20: /* MMC_DATA */
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/* TODO: support 8-bit access */
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if (s->fifo_len == 32)
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s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
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omap_mmc_transfer(s);
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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case 0x24: /* MMC_BLEN */
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s->blen = (value & 0x07ff) + 1;
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s->blen_counter = s->blen;
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case 0x28: /* MMC_NBLK */
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s->nblk = (value & 0x07ff) + 1;
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s->nblk_counter = s->nblk;
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s->blen_counter = s->blen;
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case 0x2c: /* MMC_BUF */
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s->rx_dma = (value >> 15) & 1;
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s->af_level = (value >> 8) & 0x1f;
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s->tx_dma = (value >> 7) & 1;
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s->ae_level = value & 0x1f;
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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/* SPI, SDIO and TEST modes unimplemented */
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case 0x30: /* MMC_SPI */
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case 0x34: /* MMC_SDIO */
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s->sdio = value & 0x2020;
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case 0x38: /* MMC_SYST */
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case 0x3c: /* MMC_REV */
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case 0x40: /* MMC_RSP0 */
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case 0x44: /* MMC_RSP1 */
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case 0x48: /* MMC_RSP2 */
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case 0x4c: /* MMC_RSP3 */
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case 0x50: /* MMC_RSP4 */
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case 0x54: /* MMC_RSP5 */
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case 0x58: /* MMC_RSP6 */
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case 0x5c: /* MMC_RSP7 */
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OMAP_BAD_REG(offset);
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static CPUReadMemoryFunc *omap_mmc_readfn[] = {
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omap_badwidth_read16,
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omap_badwidth_read16,
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static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
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omap_badwidth_write16,
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omap_badwidth_write16,
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void omap_mmc_reset(struct omap_mmc_s *host)
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memset(host->rsp, 0, sizeof(host->rsp));
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host->blen_counter = 0;
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host->nblk_counter = 0;
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host->ae_level = 0x00;
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host->af_level = 0x1f;
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struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
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qemu_irq irq, qemu_irq dma[], omap_clk clk)
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struct omap_mmc_s *s = (struct omap_mmc_s *)
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qemu_mallocz(sizeof(struct omap_mmc_s));
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iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
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omap_mmc_writefn, s);
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cpu_register_physical_memory(s->base, 0x800, iomemtype);
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/* Instantiate the storage */
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s->card = sd_init(sd_bdrv);
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/* TODO: insertion and read-only handlers */