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- Committer: Bazaar Package Importer
- Author(s): Soren Hansen
- Date: 2007-10-22 17:07:29 UTC
- mto: (1.5.1) (10.1.1 squeeze) (11.1.1 experimental) (12.1.1 sid) (6.1.1 sid)
- mto: This revision was merged to the branch mainline in revision 3.
- Revision ID: james.westby@ubuntu.com-20071022170729-4ihaxntpl01xg29n
Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816
- files added:
- block-parallels.c
- linux-user/alpha
- linux-user/ppc64
- linux-user/x86_64
- target-alpha
- files removed:
- linux-user/m68k-semi.c
- files modified:
- Changelog
added
removed
hw/pxa2xx.c
1
/*
2
* Intel XScale PXA255/270 processor support.
3
*
4
* Copyright (c) 2006 Openedhand Ltd.
5
* Written by Andrzej Zaborowski <balrog@zabor.org>
6
*
7
* This code is licenced under the GPL.
8
*/
9
10
# include "vl.h"
11
12
static struct {
13
target_phys_addr_t io_base;
14
int irqn;
15
} pxa255_serial[] = {
16
{ 0x40100000, PXA2XX_PIC_FFUART },
17
{ 0x40200000, PXA2XX_PIC_BTUART },
18
{ 0x40700000, PXA2XX_PIC_STUART },
19
{ 0x41600000, PXA25X_PIC_HWUART },
20
{ 0, 0 }
21
}, pxa270_serial[] = {
22
{ 0x40100000, PXA2XX_PIC_FFUART },
23
{ 0x40200000, PXA2XX_PIC_BTUART },
24
{ 0x40700000, PXA2XX_PIC_STUART },
25
{ 0, 0 }
26
};
27
28
static struct {
29
target_phys_addr_t io_base;
30
int irqn;
31
} pxa250_ssp[] = {
32
{ 0x41000000, PXA2XX_PIC_SSP },
33
{ 0, 0 }
34
}, pxa255_ssp[] = {
35
{ 0x41000000, PXA2XX_PIC_SSP },
36
{ 0x41400000, PXA25X_PIC_NSSP },
37
{ 0, 0 }
38
}, pxa26x_ssp[] = {
39
{ 0x41000000, PXA2XX_PIC_SSP },
40
{ 0x41400000, PXA25X_PIC_NSSP },
41
{ 0x41500000, PXA26X_PIC_ASSP },
42
{ 0, 0 }
43
}, pxa27x_ssp[] = {
44
{ 0x41000000, PXA2XX_PIC_SSP },
45
{ 0x41700000, PXA27X_PIC_SSP2 },
46
{ 0x41900000, PXA2XX_PIC_SSP3 },
47
{ 0, 0 }
48
};
49
50
#define PMCR 0x00 /* Power Manager Control register */
51
#define PSSR 0x04 /* Power Manager Sleep Status register */
52
#define PSPR 0x08 /* Power Manager Scratch-Pad register */
53
#define PWER 0x0c /* Power Manager Wake-Up Enable register */
54
#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55
#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56
#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57
#define PCFR 0x1c /* Power Manager General Configuration register */
58
#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59
#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60
#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61
#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62
#define RCSR 0x30 /* Reset Controller Status register */
63
#define PSLR 0x34 /* Power Manager Sleep Configuration register */
64
#define PTSR 0x38 /* Power Manager Standby Configuration register */
65
#define PVCR 0x40 /* Power Manager Voltage Change Control register */
66
#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67
#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68
#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
71
72
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
73
{
74
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
75
addr -= s->pm_base;
76
77
switch (addr) {
78
case PMCR ... PCMD31:
79
if (addr & 3)
80
goto fail;
81
82
return s->pm_regs[addr >> 2];
83
default:
84
fail:
85
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
86
break;
87
}
88
return 0;
89
}
90
91
static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
92
uint32_t value)
93
{
94
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
95
addr -= s->pm_base;
96
97
switch (addr) {
98
case PMCR:
99
s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
100
s->pm_regs[addr >> 2] |= value & 0x15;
101
break;
102
103
case PSSR: /* Read-clean registers */
104
case RCSR:
105
case PKSR:
106
s->pm_regs[addr >> 2] &= ~value;
107
break;
108
109
default: /* Read-write registers */
110
if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
111
s->pm_regs[addr >> 2] = value;
112
break;
113
}
114
115
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
116
break;
117
}
118
}
119
120
static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
121
pxa2xx_pm_read,
122
pxa2xx_pm_read,
123
pxa2xx_pm_read,
124
};
125
126
static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
127
pxa2xx_pm_write,
128
pxa2xx_pm_write,
129
pxa2xx_pm_write,
130
};
131
132
static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
133
{
134
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
135
int i;
136
137
for (i = 0; i < 0x40; i ++)
138
qemu_put_be32s(f, &s->pm_regs[i]);
139
}
140
141
static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
142
{
143
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
144
int i;
145
146
for (i = 0; i < 0x40; i ++)
147
qemu_get_be32s(f, &s->pm_regs[i]);
148
149
return 0;
150
}
151
152
#define CCCR 0x00 /* Core Clock Configuration register */
153
#define CKEN 0x04 /* Clock Enable register */
154
#define OSCC 0x08 /* Oscillator Configuration register */
155
#define CCSR 0x0c /* Core Clock Status register */
156
157
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
158
{
159
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
160
addr -= s->cm_base;
161
162
switch (addr) {
163
case CCCR:
164
case CKEN:
165
case OSCC:
166
return s->cm_regs[addr >> 2];
167
168
case CCSR:
169
return s->cm_regs[CCCR >> 2] | (3 << 28);
170
171
default:
172
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
173
break;
174
}
175
return 0;
176
}
177
178
static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
179
uint32_t value)
180
{
181
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
182
addr -= s->cm_base;
183
184
switch (addr) {
185
case CCCR:
186
case CKEN:
187
s->cm_regs[addr >> 2] = value;
188
break;
189
190
case OSCC:
191
s->cm_regs[addr >> 2] &= ~0x6c;
192
s->cm_regs[addr >> 2] |= value & 0x6e;
193
if ((value >> 1) & 1) /* OON */
194
s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
195
break;
196
197
default:
198
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
199
break;
200
}
201
}
202
203
static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
204
pxa2xx_cm_read,
205
pxa2xx_cm_read,
206
pxa2xx_cm_read,
207
};
208
209
static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
210
pxa2xx_cm_write,
211
pxa2xx_cm_write,
212
pxa2xx_cm_write,
213
};
214
215
static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
216
{
217
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
218
int i;
219
220
for (i = 0; i < 4; i ++)
221
qemu_put_be32s(f, &s->cm_regs[i]);
222
qemu_put_be32s(f, &s->clkcfg);
223
qemu_put_be32s(f, &s->pmnc);
224
}
225
226
static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
227
{
228
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
229
int i;
230
231
for (i = 0; i < 4; i ++)
232
qemu_get_be32s(f, &s->cm_regs[i]);
233
qemu_get_be32s(f, &s->clkcfg);
234
qemu_get_be32s(f, &s->pmnc);
235
236
return 0;
237
}
238
239
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
240
{
241
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
242
243
switch (reg) {
244
case 6: /* Clock Configuration register */
245
return s->clkcfg;
246
247
case 7: /* Power Mode register */
248
return 0;
249
250
default:
251
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
252
break;
253
}
254
return 0;
255
}
256
257
static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
258
uint32_t value)
259
{
260
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
261
static const char *pwrmode[8] = {
262
"Normal", "Idle", "Deep-idle", "Standby",
263
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
264
};
265
266
switch (reg) {
267
case 6: /* Clock Configuration register */
268
s->clkcfg = value & 0xf;
269
if (value & 2)
270
printf("%s: CPU frequency change attempt\n", __FUNCTION__);
271
break;
272
273
case 7: /* Power Mode register */
274
if (value & 8)
275
printf("%s: CPU voltage change attempt\n", __FUNCTION__);
276
switch (value & 7) {
277
case 0:
278
/* Do nothing */
279
break;
280
281
case 1:
282
/* Idle */
283
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
284
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
285
break;
286
}
287
/* Fall through. */
288
289
case 2:
290
/* Deep-Idle */
291
cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
292
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
293
goto message;
294
295
case 3:
296
s->env->uncached_cpsr =
297
ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
298
s->env->cp15.c1_sys = 0;
299
s->env->cp15.c1_coproc = 0;
300
s->env->cp15.c2_base = 0;
301
s->env->cp15.c3 = 0;
302
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
303
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
304
305
/*
306
* The scratch-pad register is almost universally used
307
* for storing the return address on suspend. For the
308
* lack of a resuming bootloader, perform a jump
309
* directly to that address.
310
*/
311
memset(s->env->regs, 0, 4 * 15);
312
s->env->regs[15] = s->pm_regs[PSPR >> 2];
313
314
#if 0
315
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
316
cpu_physical_memory_write(0, &buffer, 4);
317
buffer = s->pm_regs[PSPR >> 2];
318
cpu_physical_memory_write(8, &buffer, 4);
319
#endif
320
321
/* Suspend */
322
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
323
324
goto message;
325
326
default:
327
message:
328
printf("%s: machine entered %s mode\n", __FUNCTION__,
329
pwrmode[value & 7]);
330
}
331
break;
332
333
default:
334
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
335
break;
336
}
337
}
338
339
/* Performace Monitoring Registers */
340
#define CPPMNC 0 /* Performance Monitor Control register */
341
#define CPCCNT 1 /* Clock Counter register */
342
#define CPINTEN 4 /* Interrupt Enable register */
343
#define CPFLAG 5 /* Overflow Flag register */
344
#define CPEVTSEL 8 /* Event Selection register */
345
346
#define CPPMN0 0 /* Performance Count register 0 */
347
#define CPPMN1 1 /* Performance Count register 1 */
348
#define CPPMN2 2 /* Performance Count register 2 */
349
#define CPPMN3 3 /* Performance Count register 3 */
350
351
static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
352
{
353
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
354
355
switch (reg) {
356
case CPPMNC:
357
return s->pmnc;
358
case CPCCNT:
359
if (s->pmnc & 1)
360
return qemu_get_clock(vm_clock);
361
else
362
return 0;
363
case CPINTEN:
364
case CPFLAG:
365
case CPEVTSEL:
366
return 0;
367
368
default:
369
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
370
break;
371
}
372
return 0;
373
}
374
375
static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
376
uint32_t value)
377
{
378
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
379
380
switch (reg) {
381
case CPPMNC:
382
s->pmnc = value;
383
break;
384
385
case CPCCNT:
386
case CPINTEN:
387
case CPFLAG:
388
case CPEVTSEL:
389
break;
390
391
default:
392
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
393
break;
394
}
395
}
396
397
static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
398
{
399
switch (crm) {
400
case 0:
401
return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
402
case 1:
403
return pxa2xx_perf_read(opaque, op2, reg, crm);
404
case 2:
405
switch (reg) {
406
case CPPMN0:
407
case CPPMN1:
408
case CPPMN2:
409
case CPPMN3:
410
return 0;
411
}
412
/* Fall through */
413
default:
414
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
415
break;
416
}
417
return 0;
418
}
419
420
static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
421
uint32_t value)
422
{
423
switch (crm) {
424
case 0:
425
pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
426
break;
427
case 1:
428
pxa2xx_perf_write(opaque, op2, reg, crm, value);
429
break;
430
case 2:
431
switch (reg) {
432
case CPPMN0:
433
case CPPMN1:
434
case CPPMN2:
435
case CPPMN3:
436
return;
437
}
438
/* Fall through */
439
default:
440
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
441
break;
442
}
443
}
444
445
#define MDCNFG 0x00 /* SDRAM Configuration register */
446
#define MDREFR 0x04 /* SDRAM Refresh Control register */
447
#define MSC0 0x08 /* Static Memory Control register 0 */
448
#define MSC1 0x0c /* Static Memory Control register 1 */
449
#define MSC2 0x10 /* Static Memory Control register 2 */
450
#define MECR 0x14 /* Expansion Memory Bus Config register */
451
#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
452
#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
453
#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
454
#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
455
#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
456
#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
457
#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
458
#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
459
#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
460
#define ARB_CNTL 0x48 /* Arbiter Control register */
461
#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
462
#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
463
#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
464
#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
465
#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
466
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
467
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
468
469
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
470
{
471
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
472
addr -= s->mm_base;
473
474
switch (addr) {
475
case MDCNFG ... SA1110:
476
if ((addr & 3) == 0)
477
return s->mm_regs[addr >> 2];
478
479
default:
480
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
481
break;
482
}
483
return 0;
484
}
485
486
static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
487
uint32_t value)
488
{
489
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
490
addr -= s->mm_base;
491
492
switch (addr) {
493
case MDCNFG ... SA1110:
494
if ((addr & 3) == 0) {
495
s->mm_regs[addr >> 2] = value;
496
break;
497
}
498
499
default:
500
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
501
break;
502
}
503
}
504
505
static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
506
pxa2xx_mm_read,
507
pxa2xx_mm_read,
508
pxa2xx_mm_read,
509
};
510
511
static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
512
pxa2xx_mm_write,
513
pxa2xx_mm_write,
514
pxa2xx_mm_write,
515
};
516
517
static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
518
{
519
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
520
int i;
521
522
for (i = 0; i < 0x1a; i ++)
523
qemu_put_be32s(f, &s->mm_regs[i]);
524
}
525
526
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
527
{
528
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
529
int i;
530
531
for (i = 0; i < 0x1a; i ++)
532
qemu_get_be32s(f, &s->mm_regs[i]);
533
534
return 0;
535
}
536
537
/* Synchronous Serial Ports */
538
struct pxa2xx_ssp_s {
539
target_phys_addr_t base;
540
qemu_irq irq;
541
int enable;
542
543
uint32_t sscr[2];
544
uint32_t sspsp;
545
uint32_t ssto;
546
uint32_t ssitr;
547
uint32_t sssr;
548
uint8_t sstsa;
549
uint8_t ssrsa;
550
uint8_t ssacd;
551
552
uint32_t rx_fifo[16];
553
int rx_level;
554
int rx_start;
555
556
uint32_t (*readfn)(void *opaque);
557
void (*writefn)(void *opaque, uint32_t value);
558
void *opaque;
559
};
560
561
#define SSCR0 0x00 /* SSP Control register 0 */
562
#define SSCR1 0x04 /* SSP Control register 1 */
563
#define SSSR 0x08 /* SSP Status register */
564
#define SSITR 0x0c /* SSP Interrupt Test register */
565
#define SSDR 0x10 /* SSP Data register */
566
#define SSTO 0x28 /* SSP Time-Out register */
567
#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
568
#define SSTSA 0x30 /* SSP TX Time Slot Active register */
569
#define SSRSA 0x34 /* SSP RX Time Slot Active register */
570
#define SSTSS 0x38 /* SSP Time Slot Status register */
571
#define SSACD 0x3c /* SSP Audio Clock Divider register */
572
573
/* Bitfields for above registers */
574
#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
575
#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
576
#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
577
#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
578
#define SSCR0_SSE (1 << 7)
579
#define SSCR0_RIM (1 << 22)
580
#define SSCR0_TIM (1 << 23)
581
#define SSCR0_MOD (1 << 31)
582
#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
583
#define SSCR1_RIE (1 << 0)
584
#define SSCR1_TIE (1 << 1)
585
#define SSCR1_LBM (1 << 2)
586
#define SSCR1_MWDS (1 << 5)
587
#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
588
#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
589
#define SSCR1_EFWR (1 << 14)
590
#define SSCR1_PINTE (1 << 18)
591
#define SSCR1_TINTE (1 << 19)
592
#define SSCR1_RSRE (1 << 20)
593
#define SSCR1_TSRE (1 << 21)
594
#define SSCR1_EBCEI (1 << 29)
595
#define SSITR_INT (7 << 5)
596
#define SSSR_TNF (1 << 2)
597
#define SSSR_RNE (1 << 3)
598
#define SSSR_TFS (1 << 5)
599
#define SSSR_RFS (1 << 6)
600
#define SSSR_ROR (1 << 7)
601
#define SSSR_PINT (1 << 18)
602
#define SSSR_TINT (1 << 19)
603
#define SSSR_EOC (1 << 20)
604
#define SSSR_TUR (1 << 21)
605
#define SSSR_BCE (1 << 23)
606
#define SSSR_RW 0x00bc0080
607
608
static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
609
{
610
int level = 0;
611
612
level |= s->ssitr & SSITR_INT;
613
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
614
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
615
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
616
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
617
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
618
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
619
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
620
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
621
qemu_set_irq(s->irq, !!level);
622
}
623
624
static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
625
{
626
s->sssr &= ~(0xf << 12); /* Clear RFL */
627
s->sssr &= ~(0xf << 8); /* Clear TFL */
628
s->sssr &= ~SSSR_TNF;
629
if (s->enable) {
630
s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
631
if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
632
s->sssr |= SSSR_RFS;
633
else
634
s->sssr &= ~SSSR_RFS;
635
if (0 <= SSCR1_TFT(s->sscr[1]))
636
s->sssr |= SSSR_TFS;
637
else
638
s->sssr &= ~SSSR_TFS;
639
if (s->rx_level)
640
s->sssr |= SSSR_RNE;
641
else
642
s->sssr &= ~SSSR_RNE;
643
s->sssr |= SSSR_TNF;
644
}
645
646
pxa2xx_ssp_int_update(s);
647
}
648
649
static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
650
{
651
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
652
uint32_t retval;
653
addr -= s->base;
654
655
switch (addr) {
656
case SSCR0:
657
return s->sscr[0];
658
case SSCR1:
659
return s->sscr[1];
660
case SSPSP:
661
return s->sspsp;
662
case SSTO:
663
return s->ssto;
664
case SSITR:
665
return s->ssitr;
666
case SSSR:
667
return s->sssr | s->ssitr;
668
case SSDR:
669
if (!s->enable)
670
return 0xffffffff;
671
if (s->rx_level < 1) {
672
printf("%s: SSP Rx Underrun\n", __FUNCTION__);
673
return 0xffffffff;
674
}
675
s->rx_level --;
676
retval = s->rx_fifo[s->rx_start ++];
677
s->rx_start &= 0xf;
678
pxa2xx_ssp_fifo_update(s);
679
return retval;
680
case SSTSA:
681
return s->sstsa;
682
case SSRSA:
683
return s->ssrsa;
684
case SSTSS:
685
return 0;
686
case SSACD:
687
return s->ssacd;
688
default:
689
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
690
break;
691
}
692
return 0;
693
}
694
695
static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
696
uint32_t value)
697
{
698
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
699
addr -= s->base;
700
701
switch (addr) {
702
case SSCR0:
703
s->sscr[0] = value & 0xc7ffffff;
704
s->enable = value & SSCR0_SSE;
705
if (value & SSCR0_MOD)
706
printf("%s: Attempt to use network mode\n", __FUNCTION__);
707
if (s->enable && SSCR0_DSS(value) < 4)
708
printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
709
SSCR0_DSS(value));
710
if (!(value & SSCR0_SSE)) {
711
s->sssr = 0;
712
s->ssitr = 0;
713
s->rx_level = 0;
714
}
715
pxa2xx_ssp_fifo_update(s);
716
break;
717
718
case SSCR1:
719
s->sscr[1] = value;
720
if (value & (SSCR1_LBM | SSCR1_EFWR))
721
printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
722
pxa2xx_ssp_fifo_update(s);
723
break;
724
725
case SSPSP:
726
s->sspsp = value;
727
break;
728
729
case SSTO:
730
s->ssto = value;
731
break;
732
733
case SSITR:
734
s->ssitr = value & SSITR_INT;
735
pxa2xx_ssp_int_update(s);
736
break;
737
738
case SSSR:
739
s->sssr &= ~(value & SSSR_RW);
740
pxa2xx_ssp_int_update(s);
741
break;
742
743
case SSDR:
744
if (SSCR0_UWIRE(s->sscr[0])) {
745
if (s->sscr[1] & SSCR1_MWDS)
746
value &= 0xffff;
747
else
748
value &= 0xff;
749
} else
750
/* Note how 32bits overflow does no harm here */
751
value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
752
753
/* Data goes from here to the Tx FIFO and is shifted out from
754
* there directly to the slave, no need to buffer it.
755
*/
756
if (s->enable) {
757
if (s->writefn)
758
s->writefn(s->opaque, value);
759
760
if (s->rx_level < 0x10) {
761
if (s->readfn)
762
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
763
s->readfn(s->opaque);
764
else
765
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
766
} else
767
s->sssr |= SSSR_ROR;
768
}
769
pxa2xx_ssp_fifo_update(s);
770
break;
771
772
case SSTSA:
773
s->sstsa = value;
774
break;
775
776
case SSRSA:
777
s->ssrsa = value;
778
break;
779
780
case SSACD:
781
s->ssacd = value;
782
break;
783
784
default:
785
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
786
break;
787
}
788
}
789
790
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
791
uint32_t (*readfn)(void *opaque),
792
void (*writefn)(void *opaque, uint32_t value), void *opaque)
793
{
794
if (!port) {
795
printf("%s: no such SSP\n", __FUNCTION__);
796
exit(-1);
797
}
798
799
port->opaque = opaque;
800
port->readfn = readfn;
801
port->writefn = writefn;
802
}
803
804
static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
805
pxa2xx_ssp_read,
806
pxa2xx_ssp_read,
807
pxa2xx_ssp_read,
808
};
809
810
static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
811
pxa2xx_ssp_write,
812
pxa2xx_ssp_write,
813
pxa2xx_ssp_write,
814
};
815
816
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
817
{
818
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
819
int i;
820
821
qemu_put_be32(f, s->enable);
822
823
qemu_put_be32s(f, &s->sscr[0]);
824
qemu_put_be32s(f, &s->sscr[1]);
825
qemu_put_be32s(f, &s->sspsp);
826
qemu_put_be32s(f, &s->ssto);
827
qemu_put_be32s(f, &s->ssitr);
828
qemu_put_be32s(f, &s->sssr);
829
qemu_put_8s(f, &s->sstsa);
830
qemu_put_8s(f, &s->ssrsa);
831
qemu_put_8s(f, &s->ssacd);
832
833
qemu_put_byte(f, s->rx_level);
834
for (i = 0; i < s->rx_level; i ++)
835
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
836
}
837
838
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
839
{
840
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
841
int i;
842
843
s->enable = qemu_get_be32(f);
844
845
qemu_get_be32s(f, &s->sscr[0]);
846
qemu_get_be32s(f, &s->sscr[1]);
847
qemu_get_be32s(f, &s->sspsp);
848
qemu_get_be32s(f, &s->ssto);
849
qemu_get_be32s(f, &s->ssitr);
850
qemu_get_be32s(f, &s->sssr);
851
qemu_get_8s(f, &s->sstsa);
852
qemu_get_8s(f, &s->ssrsa);
853
qemu_get_8s(f, &s->ssacd);
854
855
s->rx_level = qemu_get_byte(f);
856
s->rx_start = 0;
857
for (i = 0; i < s->rx_level; i ++)
858
s->rx_fifo[i] = qemu_get_byte(f);
859
860
return 0;
861
}
862
863
/* Real-Time Clock */
864
#define RCNR 0x00 /* RTC Counter register */
865
#define RTAR 0x04 /* RTC Alarm register */
866
#define RTSR 0x08 /* RTC Status register */
867
#define RTTR 0x0c /* RTC Timer Trim register */
868
#define RDCR 0x10 /* RTC Day Counter register */
869
#define RYCR 0x14 /* RTC Year Counter register */
870
#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
871
#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
872
#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
873
#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
874
#define SWCR 0x28 /* RTC Stopwatch Counter register */
875
#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
876
#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
877
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
878
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
879
880
static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
881
{
882
qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
883
}
884
885
static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
886
{
887
int64_t rt = qemu_get_clock(rt_clock);
888
s->last_rcnr += ((rt - s->last_hz) << 15) /
889
(1000 * ((s->rttr & 0xffff) + 1));
890
s->last_rdcr += ((rt - s->last_hz) << 15) /
891
(1000 * ((s->rttr & 0xffff) + 1));
892
s->last_hz = rt;
893
}
894
895
static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
896
{
897
int64_t rt = qemu_get_clock(rt_clock);
898
if (s->rtsr & (1 << 12))
899
s->last_swcr += (rt - s->last_sw) / 10;
900
s->last_sw = rt;
901
}
902
903
static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
904
{
905
int64_t rt = qemu_get_clock(rt_clock);
906
if (s->rtsr & (1 << 15))
907
s->last_swcr += rt - s->last_pi;
908
s->last_pi = rt;
909
}
910
911
static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
912
uint32_t rtsr)
913
{
914
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
915
qemu_mod_timer(s->rtc_hz, s->last_hz +
916
(((s->rtar - s->last_rcnr) * 1000 *
917
((s->rttr & 0xffff) + 1)) >> 15));
918
else
919
qemu_del_timer(s->rtc_hz);
920
921
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
922
qemu_mod_timer(s->rtc_rdal1, s->last_hz +
923
(((s->rdar1 - s->last_rdcr) * 1000 *
924
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
925
else
926
qemu_del_timer(s->rtc_rdal1);
927
928
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
929
qemu_mod_timer(s->rtc_rdal2, s->last_hz +
930
(((s->rdar2 - s->last_rdcr) * 1000 *
931
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
932
else
933
qemu_del_timer(s->rtc_rdal2);
934
935
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
936
qemu_mod_timer(s->rtc_swal1, s->last_sw +
937
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
938
else
939
qemu_del_timer(s->rtc_swal1);
940
941
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
942
qemu_mod_timer(s->rtc_swal2, s->last_sw +
943
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
944
else
945
qemu_del_timer(s->rtc_swal2);
946
947
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
948
qemu_mod_timer(s->rtc_pi, s->last_pi +
949
(s->piar & 0xffff) - s->last_rtcpicr);
950
else
951
qemu_del_timer(s->rtc_pi);
952
}
953
954
static inline void pxa2xx_rtc_hz_tick(void *opaque)
955
{
956
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
957
s->rtsr |= (1 << 0);
958
pxa2xx_rtc_alarm_update(s, s->rtsr);
959
pxa2xx_rtc_int_update(s);
960
}
961
962
static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
963
{
964
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
965
s->rtsr |= (1 << 4);
966
pxa2xx_rtc_alarm_update(s, s->rtsr);
967
pxa2xx_rtc_int_update(s);
968
}
969
970
static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
971
{
972
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
973
s->rtsr |= (1 << 6);
974
pxa2xx_rtc_alarm_update(s, s->rtsr);
975
pxa2xx_rtc_int_update(s);
976
}
977
978
static inline void pxa2xx_rtc_swal1_tick(void *opaque)
979
{
980
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
981
s->rtsr |= (1 << 8);
982
pxa2xx_rtc_alarm_update(s, s->rtsr);
983
pxa2xx_rtc_int_update(s);
984
}
985
986
static inline void pxa2xx_rtc_swal2_tick(void *opaque)
987
{
988
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
989
s->rtsr |= (1 << 10);
990
pxa2xx_rtc_alarm_update(s, s->rtsr);
991
pxa2xx_rtc_int_update(s);
992
}
993
994
static inline void pxa2xx_rtc_pi_tick(void *opaque)
995
{
996
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
997
s->rtsr |= (1 << 13);
998
pxa2xx_rtc_piupdate(s);
999
s->last_rtcpicr = 0;
1000
pxa2xx_rtc_alarm_update(s, s->rtsr);
1001
pxa2xx_rtc_int_update(s);
1002
}
1003
1004
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1005
{
1006
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1007
addr -= s->rtc_base;
1008
1009
switch (addr) {
1010
case RTTR:
1011
return s->rttr;
1012
case RTSR:
1013
return s->rtsr;
1014
case RTAR:
1015
return s->rtar;
1016
case RDAR1:
1017
return s->rdar1;
1018
case RDAR2:
1019
return s->rdar2;
1020
case RYAR1:
1021
return s->ryar1;
1022
case RYAR2:
1023
return s->ryar2;
1024
case SWAR1:
1025
return s->swar1;
1026
case SWAR2:
1027
return s->swar2;
1028
case PIAR:
1029
return s->piar;
1030
case RCNR:
1031
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1032
(1000 * ((s->rttr & 0xffff) + 1));
1033
case RDCR:
1034
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1035
(1000 * ((s->rttr & 0xffff) + 1));
1036
case RYCR:
1037
return s->last_rycr;
1038
case SWCR:
1039
if (s->rtsr & (1 << 12))
1040
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1041
else
1042
return s->last_swcr;
1043
default:
1044
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1045
break;
1046
}
1047
return 0;
1048
}
1049
1050
static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1051
uint32_t value)
1052
{
1053
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1054
addr -= s->rtc_base;
1055
1056
switch (addr) {
1057
case RTTR:
1058
if (!(s->rttr & (1 << 31))) {
1059
pxa2xx_rtc_hzupdate(s);
1060
s->rttr = value;
1061
pxa2xx_rtc_alarm_update(s, s->rtsr);
1062
}
1063
break;
1064
1065
case RTSR:
1066
if ((s->rtsr ^ value) & (1 << 15))
1067
pxa2xx_rtc_piupdate(s);
1068
1069
if ((s->rtsr ^ value) & (1 << 12))
1070
pxa2xx_rtc_swupdate(s);
1071
1072
if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1073
pxa2xx_rtc_alarm_update(s, value);
1074
1075
s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1076
pxa2xx_rtc_int_update(s);
1077
break;
1078
1079
case RTAR:
1080
s->rtar = value;
1081
pxa2xx_rtc_alarm_update(s, s->rtsr);
1082
break;
1083
1084
case RDAR1:
1085
s->rdar1 = value;
1086
pxa2xx_rtc_alarm_update(s, s->rtsr);
1087
break;
1088
1089
case RDAR2:
1090
s->rdar2 = value;
1091
pxa2xx_rtc_alarm_update(s, s->rtsr);
1092
break;
1093
1094
case RYAR1:
1095
s->ryar1 = value;
1096
pxa2xx_rtc_alarm_update(s, s->rtsr);
1097
break;
1098
1099
case RYAR2:
1100
s->ryar2 = value;
1101
pxa2xx_rtc_alarm_update(s, s->rtsr);
1102
break;
1103
1104
case SWAR1:
1105
pxa2xx_rtc_swupdate(s);
1106
s->swar1 = value;
1107
s->last_swcr = 0;
1108
pxa2xx_rtc_alarm_update(s, s->rtsr);
1109
break;
1110
1111
case SWAR2:
1112
s->swar2 = value;
1113
pxa2xx_rtc_alarm_update(s, s->rtsr);
1114
break;
1115
1116
case PIAR:
1117
s->piar = value;
1118
pxa2xx_rtc_alarm_update(s, s->rtsr);
1119
break;
1120
1121
case RCNR:
1122
pxa2xx_rtc_hzupdate(s);
1123
s->last_rcnr = value;
1124
pxa2xx_rtc_alarm_update(s, s->rtsr);
1125
break;
1126
1127
case RDCR:
1128
pxa2xx_rtc_hzupdate(s);
1129
s->last_rdcr = value;
1130
pxa2xx_rtc_alarm_update(s, s->rtsr);
1131
break;
1132
1133
case RYCR:
1134
s->last_rycr = value;
1135
break;
1136
1137
case SWCR:
1138
pxa2xx_rtc_swupdate(s);
1139
s->last_swcr = value;
1140
pxa2xx_rtc_alarm_update(s, s->rtsr);
1141
break;
1142
1143
case RTCPICR:
1144
pxa2xx_rtc_piupdate(s);
1145
s->last_rtcpicr = value & 0xffff;
1146
pxa2xx_rtc_alarm_update(s, s->rtsr);
1147
break;
1148
1149
default:
1150
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1151
}
1152
}
1153
1154
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1155
pxa2xx_rtc_read,
1156
pxa2xx_rtc_read,
1157
pxa2xx_rtc_read,
1158
};
1159
1160
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1161
pxa2xx_rtc_write,
1162
pxa2xx_rtc_write,
1163
pxa2xx_rtc_write,
1164
};
1165
1166
static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
1167
{
1168
struct tm *tm;
1169
time_t ti;
1170
int wom;
1171
1172
s->rttr = 0x7fff;
1173
s->rtsr = 0;
1174
1175
time(&ti);
1176
if (rtc_utc)
1177
tm = gmtime(&ti);
1178
else
1179
tm = localtime(&ti);
1180
wom = ((tm->tm_mday - 1) / 7) + 1;
1181
1182
s->last_rcnr = (uint32_t) ti;
1183
s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1184
(tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1185
s->last_rycr = ((tm->tm_year + 1900) << 9) |
1186
((tm->tm_mon + 1) << 5) | tm->tm_mday;
1187
s->last_swcr = (tm->tm_hour << 19) |
1188
(tm->tm_min << 13) | (tm->tm_sec << 7);
1189
s->last_rtcpicr = 0;
1190
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1191
1192
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1193
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1194
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1195
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1196
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1197
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1198
}
1199
1200
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1201
{
1202
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1203
1204
pxa2xx_rtc_hzupdate(s);
1205
pxa2xx_rtc_piupdate(s);
1206
pxa2xx_rtc_swupdate(s);
1207
1208
qemu_put_be32s(f, &s->rttr);
1209
qemu_put_be32s(f, &s->rtsr);
1210
qemu_put_be32s(f, &s->rtar);
1211
qemu_put_be32s(f, &s->rdar1);
1212
qemu_put_be32s(f, &s->rdar2);
1213
qemu_put_be32s(f, &s->ryar1);
1214
qemu_put_be32s(f, &s->ryar2);
1215
qemu_put_be32s(f, &s->swar1);
1216
qemu_put_be32s(f, &s->swar2);
1217
qemu_put_be32s(f, &s->piar);
1218
qemu_put_be32s(f, &s->last_rcnr);
1219
qemu_put_be32s(f, &s->last_rdcr);
1220
qemu_put_be32s(f, &s->last_rycr);
1221
qemu_put_be32s(f, &s->last_swcr);
1222
qemu_put_be32s(f, &s->last_rtcpicr);
1223
qemu_put_be64s(f, &s->last_hz);
1224
qemu_put_be64s(f, &s->last_sw);
1225
qemu_put_be64s(f, &s->last_pi);
1226
}
1227
1228
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1229
{
1230
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1231
1232
qemu_get_be32s(f, &s->rttr);
1233
qemu_get_be32s(f, &s->rtsr);
1234
qemu_get_be32s(f, &s->rtar);
1235
qemu_get_be32s(f, &s->rdar1);
1236
qemu_get_be32s(f, &s->rdar2);
1237
qemu_get_be32s(f, &s->ryar1);
1238
qemu_get_be32s(f, &s->ryar2);
1239
qemu_get_be32s(f, &s->swar1);
1240
qemu_get_be32s(f, &s->swar2);
1241
qemu_get_be32s(f, &s->piar);
1242
qemu_get_be32s(f, &s->last_rcnr);
1243
qemu_get_be32s(f, &s->last_rdcr);
1244
qemu_get_be32s(f, &s->last_rycr);
1245
qemu_get_be32s(f, &s->last_swcr);
1246
qemu_get_be32s(f, &s->last_rtcpicr);
1247
qemu_get_be64s(f, &s->last_hz);
1248
qemu_get_be64s(f, &s->last_sw);
1249
qemu_get_be64s(f, &s->last_pi);
1250
1251
pxa2xx_rtc_alarm_update(s, s->rtsr);
1252
1253
return 0;
1254
}
1255
1256
/* I2C Interface */
1257
struct pxa2xx_i2c_s {
1258
i2c_slave slave;
1259
i2c_bus *bus;
1260
target_phys_addr_t base;
1261
qemu_irq irq;
1262
1263
uint16_t control;
1264
uint16_t status;
1265
uint8_t ibmr;
1266
uint8_t data;
1267
};
1268
1269
#define IBMR 0x80 /* I2C Bus Monitor register */
1270
#define IDBR 0x88 /* I2C Data Buffer register */
1271
#define ICR 0x90 /* I2C Control register */
1272
#define ISR 0x98 /* I2C Status register */
1273
#define ISAR 0xa0 /* I2C Slave Address register */
1274
1275
static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1276
{
1277
uint16_t level = 0;
1278
level |= s->status & s->control & (1 << 10); /* BED */
1279
level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1280
level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1281
level |= s->status & (1 << 9); /* SAD */
1282
qemu_set_irq(s->irq, !!level);
1283
}
1284
1285
/* These are only stubs now. */
1286
static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1287
{
1288
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1289
1290
switch (event) {
1291
case I2C_START_SEND:
1292
s->status |= (1 << 9); /* set SAD */
1293
s->status &= ~(1 << 0); /* clear RWM */
1294
break;
1295
case I2C_START_RECV:
1296
s->status |= (1 << 9); /* set SAD */
1297
s->status |= 1 << 0; /* set RWM */
1298
break;
1299
case I2C_FINISH:
1300
s->status |= (1 << 4); /* set SSD */
1301
break;
1302
case I2C_NACK:
1303
s->status |= 1 << 1; /* set ACKNAK */
1304
break;
1305
}
1306
pxa2xx_i2c_update(s);
1307
}
1308
1309
static int pxa2xx_i2c_rx(i2c_slave *i2c)
1310
{
1311
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1312
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1313
return 0;
1314
1315
if (s->status & (1 << 0)) { /* RWM */
1316
s->status |= 1 << 6; /* set ITE */
1317
}
1318
pxa2xx_i2c_update(s);
1319
1320
return s->data;
1321
}
1322
1323
static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1324
{
1325
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1326
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1327
return 1;
1328
1329
if (!(s->status & (1 << 0))) { /* RWM */
1330
s->status |= 1 << 7; /* set IRF */
1331
s->data = data;
1332
}
1333
pxa2xx_i2c_update(s);
1334
1335
return 1;
1336
}
1337
1338
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1339
{
1340
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1341
addr -= s->base;
1342
1343
switch (addr) {
1344
case ICR:
1345
return s->control;
1346
case ISR:
1347
return s->status | (i2c_bus_busy(s->bus) << 2);
1348
case ISAR:
1349
return s->slave.address;
1350
case IDBR:
1351
return s->data;
1352
case IBMR:
1353
if (s->status & (1 << 2))
1354
s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1355
else
1356
s->ibmr = 0;
1357
return s->ibmr;
1358
default:
1359
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1360
break;
1361
}
1362
return 0;
1363
}
1364
1365
static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1366
uint32_t value)
1367
{
1368
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1369
int ack;
1370
addr -= s->base;
1371
1372
switch (addr) {
1373
case ICR:
1374
s->control = value & 0xfff7;
1375
if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1376
/* TODO: slave mode */
1377
if (value & (1 << 0)) { /* START condition */
1378
if (s->data & 1)
1379
s->status |= 1 << 0; /* set RWM */
1380
else
1381
s->status &= ~(1 << 0); /* clear RWM */
1382
ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1383
} else {
1384
if (s->status & (1 << 0)) { /* RWM */
1385
s->data = i2c_recv(s->bus);
1386
if (value & (1 << 2)) /* ACKNAK */
1387
i2c_nack(s->bus);
1388
ack = 1;
1389
} else
1390
ack = !i2c_send(s->bus, s->data);
1391
}
1392
1393
if (value & (1 << 1)) /* STOP condition */
1394
i2c_end_transfer(s->bus);
1395
1396
if (ack) {
1397
if (value & (1 << 0)) /* START condition */
1398
s->status |= 1 << 6; /* set ITE */
1399
else
1400
if (s->status & (1 << 0)) /* RWM */
1401
s->status |= 1 << 7; /* set IRF */
1402
else
1403
s->status |= 1 << 6; /* set ITE */
1404
s->status &= ~(1 << 1); /* clear ACKNAK */
1405
} else {
1406
s->status |= 1 << 6; /* set ITE */
1407
s->status |= 1 << 10; /* set BED */
1408
s->status |= 1 << 1; /* set ACKNAK */
1409
}
1410
}
1411
if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1412
if (value & (1 << 4)) /* MA */
1413
i2c_end_transfer(s->bus);
1414
pxa2xx_i2c_update(s);
1415
break;
1416
1417
case ISR:
1418
s->status &= ~(value & 0x07f0);
1419
pxa2xx_i2c_update(s);
1420
break;
1421
1422
case ISAR:
1423
i2c_set_slave_address(&s->slave, value & 0x7f);
1424
break;
1425
1426
case IDBR:
1427
s->data = value & 0xff;
1428
break;
1429
1430
default:
1431
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1432
}
1433
}
1434
1435
static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1436
pxa2xx_i2c_read,
1437
pxa2xx_i2c_read,
1438
pxa2xx_i2c_read,
1439
};
1440
1441
static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1442
pxa2xx_i2c_write,
1443
pxa2xx_i2c_write,
1444
pxa2xx_i2c_write,
1445
};
1446
1447
static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1448
{
1449
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1450
1451
qemu_put_be16s(f, &s->control);
1452
qemu_put_be16s(f, &s->status);
1453
qemu_put_8s(f, &s->ibmr);
1454
qemu_put_8s(f, &s->data);
1455
1456
i2c_bus_save(f, s->bus);
1457
i2c_slave_save(f, &s->slave);
1458
}
1459
1460
static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1461
{
1462
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1463
1464
qemu_get_be16s(f, &s->control);
1465
qemu_get_be16s(f, &s->status);
1466
qemu_get_8s(f, &s->ibmr);
1467
qemu_get_8s(f, &s->data);
1468
1469
i2c_bus_load(f, s->bus);
1470
i2c_slave_load(f, &s->slave);
1471
return 0;
1472
}
1473
1474
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
1475
qemu_irq irq, uint32_t page_size)
1476
{
1477
int iomemtype;
1478
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
1479
i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
1480
1481
s->base = base;
1482
s->irq = irq;
1483
s->slave.event = pxa2xx_i2c_event;
1484
s->slave.recv = pxa2xx_i2c_rx;
1485
s->slave.send = pxa2xx_i2c_tx;
1486
s->bus = i2c_init_bus();
1487
1488
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1489
pxa2xx_i2c_writefn, s);
1490
cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
1491
1492
register_savevm("pxa2xx_i2c", base, 0,
1493
pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1494
1495
return s;
1496
}
1497
1498
i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1499
{
1500
return s->bus;
1501
}
1502
1503
/* PXA Inter-IC Sound Controller */
1504
static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1505
{
1506
i2s->rx_len = 0;
1507
i2s->tx_len = 0;
1508
i2s->fifo_len = 0;
1509
i2s->clk = 0x1a;
1510
i2s->control[0] = 0x00;
1511
i2s->control[1] = 0x00;
1512
i2s->status = 0x00;
1513
i2s->mask = 0x00;
1514
}
1515
1516
#define SACR_TFTH(val) ((val >> 8) & 0xf)
1517
#define SACR_RFTH(val) ((val >> 12) & 0xf)
1518
#define SACR_DREC(val) (val & (1 << 3))
1519
#define SACR_DPRL(val) (val & (1 << 4))
1520
1521
static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1522
{
1523
int rfs, tfs;
1524
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1525
!SACR_DREC(i2s->control[1]);
1526
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1527
i2s->enable && !SACR_DPRL(i2s->control[1]);
1528
1529
pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1530
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1531
1532
i2s->status &= 0xe0;
1533
if (i2s->fifo_len < 16 || !i2s->enable)
1534
i2s->status |= 1 << 0; /* TNF */
1535
if (i2s->rx_len)
1536
i2s->status |= 1 << 1; /* RNE */
1537
if (i2s->enable)
1538
i2s->status |= 1 << 2; /* BSY */
1539
if (tfs)
1540
i2s->status |= 1 << 3; /* TFS */
1541
if (rfs)
1542
i2s->status |= 1 << 4; /* RFS */
1543
if (!(i2s->tx_len && i2s->enable))
1544
i2s->status |= i2s->fifo_len << 8; /* TFL */
1545
i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1546
1547
qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1548
}
1549
1550
#define SACR0 0x00 /* Serial Audio Global Control register */
1551
#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1552
#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1553
#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1554
#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1555
#define SADIV 0x60 /* Serial Audio Clock Divider register */
1556
#define SADR 0x80 /* Serial Audio Data register */
1557
1558
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1559
{
1560
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1561
addr -= s->base;
1562
1563
switch (addr) {
1564
case SACR0:
1565
return s->control[0];
1566
case SACR1:
1567
return s->control[1];
1568
case SASR0:
1569
return s->status;
1570
case SAIMR:
1571
return s->mask;
1572
case SAICR:
1573
return 0;
1574
case SADIV:
1575
return s->clk;
1576
case SADR:
1577
if (s->rx_len > 0) {
1578
s->rx_len --;
1579
pxa2xx_i2s_update(s);
1580
return s->codec_in(s->opaque);
1581
}
1582
return 0;
1583
default:
1584
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1585
break;
1586
}
1587
return 0;
1588
}
1589
1590
static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1591
uint32_t value)
1592
{
1593
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1594
uint32_t *sample;
1595
addr -= s->base;
1596
1597
switch (addr) {
1598
case SACR0:
1599
if (value & (1 << 3)) /* RST */
1600
pxa2xx_i2s_reset(s);
1601
s->control[0] = value & 0xff3d;
1602
if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1603
for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1604
s->codec_out(s->opaque, *sample);
1605
s->status &= ~(1 << 7); /* I2SOFF */
1606
}
1607
if (value & (1 << 4)) /* EFWR */
1608
printf("%s: Attempt to use special function\n", __FUNCTION__);
1609
s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1610
pxa2xx_i2s_update(s);
1611
break;
1612
case SACR1:
1613
s->control[1] = value & 0x0039;
1614
if (value & (1 << 5)) /* ENLBF */
1615
printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1616
if (value & (1 << 4)) /* DPRL */
1617
s->fifo_len = 0;
1618
pxa2xx_i2s_update(s);
1619
break;
1620
case SAIMR:
1621
s->mask = value & 0x0078;
1622
pxa2xx_i2s_update(s);
1623
break;
1624
case SAICR:
1625
s->status &= ~(value & (3 << 5));
1626
pxa2xx_i2s_update(s);
1627
break;
1628
case SADIV:
1629
s->clk = value & 0x007f;
1630
break;
1631
case SADR:
1632
if (s->tx_len && s->enable) {
1633
s->tx_len --;
1634
pxa2xx_i2s_update(s);
1635
s->codec_out(s->opaque, value);
1636
} else if (s->fifo_len < 16) {
1637
s->fifo[s->fifo_len ++] = value;
1638
pxa2xx_i2s_update(s);
1639
}
1640
break;
1641
default:
1642
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1643
}
1644
}
1645
1646
static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1647
pxa2xx_i2s_read,
1648
pxa2xx_i2s_read,
1649
pxa2xx_i2s_read,
1650
};
1651
1652
static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1653
pxa2xx_i2s_write,
1654
pxa2xx_i2s_write,
1655
pxa2xx_i2s_write,
1656
};
1657
1658
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1659
{
1660
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1661
1662
qemu_put_be32s(f, &s->control[0]);
1663
qemu_put_be32s(f, &s->control[1]);
1664
qemu_put_be32s(f, &s->status);
1665
qemu_put_be32s(f, &s->mask);
1666
qemu_put_be32s(f, &s->clk);
1667
1668
qemu_put_be32(f, s->enable);
1669
qemu_put_be32(f, s->rx_len);
1670
qemu_put_be32(f, s->tx_len);
1671
qemu_put_be32(f, s->fifo_len);
1672
}
1673
1674
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1675
{
1676
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1677
1678
qemu_get_be32s(f, &s->control[0]);
1679
qemu_get_be32s(f, &s->control[1]);
1680
qemu_get_be32s(f, &s->status);
1681
qemu_get_be32s(f, &s->mask);
1682
qemu_get_be32s(f, &s->clk);
1683
1684
s->enable = qemu_get_be32(f);
1685
s->rx_len = qemu_get_be32(f);
1686
s->tx_len = qemu_get_be32(f);
1687
s->fifo_len = qemu_get_be32(f);
1688
1689
return 0;
1690
}
1691
1692
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1693
{
1694
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1695
uint32_t *sample;
1696
1697
/* Signal FIFO errors */
1698
if (s->enable && s->tx_len)
1699
s->status |= 1 << 5; /* TUR */
1700
if (s->enable && s->rx_len)
1701
s->status |= 1 << 6; /* ROR */
1702
1703
/* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1704
* handle the cases where it makes a difference. */
1705
s->tx_len = tx - s->fifo_len;
1706
s->rx_len = rx;
1707
/* Note that is s->codec_out wasn't set, we wouldn't get called. */
1708
if (s->enable)
1709
for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1710
s->codec_out(s->opaque, *sample);
1711
pxa2xx_i2s_update(s);
1712
}
1713
1714
static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1715
qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1716
{
1717
int iomemtype;
1718
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1719
qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1720
1721
s->base = base;
1722
s->irq = irq;
1723
s->dma = dma;
1724
s->data_req = pxa2xx_i2s_data_req;
1725
1726
pxa2xx_i2s_reset(s);
1727
1728
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1729
pxa2xx_i2s_writefn, s);
1730
cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
1731
1732
register_savevm("pxa2xx_i2s", base, 0,
1733
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1734
1735
return s;
1736
}
1737
1738
/* PXA Fast Infra-red Communications Port */
1739
struct pxa2xx_fir_s {
1740
target_phys_addr_t base;
1741
qemu_irq irq;
1742
struct pxa2xx_dma_state_s *dma;
1743
int enable;
1744
CharDriverState *chr;
1745
1746
uint8_t control[3];
1747
uint8_t status[2];
1748
1749
int rx_len;
1750
int rx_start;
1751
uint8_t rx_fifo[64];
1752
};
1753
1754
static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1755
{
1756
s->control[0] = 0x00;
1757
s->control[1] = 0x00;
1758
s->control[2] = 0x00;
1759
s->status[0] = 0x00;
1760
s->status[1] = 0x00;
1761
s->enable = 0;
1762
}
1763
1764
static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1765
{
1766
static const int tresh[4] = { 8, 16, 32, 0 };
1767
int intr = 0;
1768
if ((s->control[0] & (1 << 4)) && /* RXE */
1769
s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1770
s->status[0] |= 1 << 4; /* RFS */
1771
else
1772
s->status[0] &= ~(1 << 4); /* RFS */
1773
if (s->control[0] & (1 << 3)) /* TXE */
1774
s->status[0] |= 1 << 3; /* TFS */
1775
else
1776
s->status[0] &= ~(1 << 3); /* TFS */
1777
if (s->rx_len)
1778
s->status[1] |= 1 << 2; /* RNE */
1779
else
1780
s->status[1] &= ~(1 << 2); /* RNE */
1781
if (s->control[0] & (1 << 4)) /* RXE */
1782
s->status[1] |= 1 << 0; /* RSY */
1783
else
1784
s->status[1] &= ~(1 << 0); /* RSY */
1785
1786
intr |= (s->control[0] & (1 << 5)) && /* RIE */
1787
(s->status[0] & (1 << 4)); /* RFS */
1788
intr |= (s->control[0] & (1 << 6)) && /* TIE */
1789
(s->status[0] & (1 << 3)); /* TFS */
1790
intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1791
(s->status[0] & (1 << 6)); /* EOC */
1792
intr |= (s->control[0] & (1 << 2)) && /* TUS */
1793
(s->status[0] & (1 << 1)); /* TUR */
1794
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1795
1796
pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1797
pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1798
1799
qemu_set_irq(s->irq, intr && s->enable);
1800
}
1801
1802
#define ICCR0 0x00 /* FICP Control register 0 */
1803
#define ICCR1 0x04 /* FICP Control register 1 */
1804
#define ICCR2 0x08 /* FICP Control register 2 */
1805
#define ICDR 0x0c /* FICP Data register */
1806
#define ICSR0 0x14 /* FICP Status register 0 */
1807
#define ICSR1 0x18 /* FICP Status register 1 */
1808
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1809
1810
static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1811
{
1812
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1813
uint8_t ret;
1814
addr -= s->base;
1815
1816
switch (addr) {
1817
case ICCR0:
1818
return s->control[0];
1819
case ICCR1:
1820
return s->control[1];
1821
case ICCR2:
1822
return s->control[2];
1823
case ICDR:
1824
s->status[0] &= ~0x01;
1825
s->status[1] &= ~0x72;
1826
if (s->rx_len) {
1827
s->rx_len --;
1828
ret = s->rx_fifo[s->rx_start ++];
1829
s->rx_start &= 63;
1830
pxa2xx_fir_update(s);
1831
return ret;
1832
}
1833
printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1834
break;
1835
case ICSR0:
1836
return s->status[0];
1837
case ICSR1:
1838
return s->status[1] | (1 << 3); /* TNF */
1839
case ICFOR:
1840
return s->rx_len;
1841
default:
1842
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1843
break;
1844
}
1845
return 0;
1846
}
1847
1848
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1849
uint32_t value)
1850
{
1851
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1852
uint8_t ch;
1853
addr -= s->base;
1854
1855
switch (addr) {
1856
case ICCR0:
1857
s->control[0] = value;
1858
if (!(value & (1 << 4))) /* RXE */
1859
s->rx_len = s->rx_start = 0;
1860
if (!(value & (1 << 3))) /* TXE */
1861
/* Nop */;
1862
s->enable = value & 1; /* ITR */
1863
if (!s->enable)
1864
s->status[0] = 0;
1865
pxa2xx_fir_update(s);
1866
break;
1867
case ICCR1:
1868
s->control[1] = value;
1869
break;
1870
case ICCR2:
1871
s->control[2] = value & 0x3f;
1872
pxa2xx_fir_update(s);
1873
break;
1874
case ICDR:
1875
if (s->control[2] & (1 << 2)) /* TXP */
1876
ch = value;
1877
else
1878
ch = ~value;
1879
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1880
qemu_chr_write(s->chr, &ch, 1);
1881
break;
1882
case ICSR0:
1883
s->status[0] &= ~(value & 0x66);
1884
pxa2xx_fir_update(s);
1885
break;
1886
case ICFOR:
1887
break;
1888
default:
1889
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1890
}
1891
}
1892
1893
static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1894
pxa2xx_fir_read,
1895
pxa2xx_fir_read,
1896
pxa2xx_fir_read,
1897
};
1898
1899
static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1900
pxa2xx_fir_write,
1901
pxa2xx_fir_write,
1902
pxa2xx_fir_write,
1903
};
1904
1905
static int pxa2xx_fir_is_empty(void *opaque)
1906
{
1907
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1908
return (s->rx_len < 64);
1909
}
1910
1911
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1912
{
1913
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1914
if (!(s->control[0] & (1 << 4))) /* RXE */
1915
return;
1916
1917
while (size --) {
1918
s->status[1] |= 1 << 4; /* EOF */
1919
if (s->rx_len >= 64) {
1920
s->status[1] |= 1 << 6; /* ROR */
1921
break;
1922
}
1923
1924
if (s->control[2] & (1 << 3)) /* RXP */
1925
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1926
else
1927
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1928
}
1929
1930
pxa2xx_fir_update(s);
1931
}
1932
1933
static void pxa2xx_fir_event(void *opaque, int event)
1934
{
1935
}
1936
1937
static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1938
{
1939
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1940
int i;
1941
1942
qemu_put_be32(f, s->enable);
1943
1944
qemu_put_8s(f, &s->control[0]);
1945
qemu_put_8s(f, &s->control[1]);
1946
qemu_put_8s(f, &s->control[2]);
1947
qemu_put_8s(f, &s->status[0]);
1948
qemu_put_8s(f, &s->status[1]);
1949
1950
qemu_put_byte(f, s->rx_len);
1951
for (i = 0; i < s->rx_len; i ++)
1952
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1953
}
1954
1955
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1956
{
1957
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1958
int i;
1959
1960
s->enable = qemu_get_be32(f);
1961
1962
qemu_get_8s(f, &s->control[0]);
1963
qemu_get_8s(f, &s->control[1]);
1964
qemu_get_8s(f, &s->control[2]);
1965
qemu_get_8s(f, &s->status[0]);
1966
qemu_get_8s(f, &s->status[1]);
1967
1968
s->rx_len = qemu_get_byte(f);
1969
s->rx_start = 0;
1970
for (i = 0; i < s->rx_len; i ++)
1971
s->rx_fifo[i] = qemu_get_byte(f);
1972
1973
return 0;
1974
}
1975
1976
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1977
qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1978
CharDriverState *chr)
1979
{
1980
int iomemtype;
1981
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1982
qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1983
1984
s->base = base;
1985
s->irq = irq;
1986
s->dma = dma;
1987
s->chr = chr;
1988
1989
pxa2xx_fir_reset(s);
1990
1991
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1992
pxa2xx_fir_writefn, s);
1993
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
1994
1995
if (chr)
1996
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1997
pxa2xx_fir_rx, pxa2xx_fir_event, s);
1998
1999
register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
2000
2001
return s;
2002
}
2003
2004
void pxa2xx_reset(int line, int level, void *opaque)
2005
{
2006
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
2007
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2008
cpu_reset(s->env);
2009
/* TODO: reset peripherals */
2010
}
2011
}
2012
2013
/* Initialise a PXA270 integrated chip (ARM based core). */
2014
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2015
DisplayState *ds, const char *revision)
2016
{
2017
struct pxa2xx_state_s *s;
2018
struct pxa2xx_ssp_s *ssp;
2019
int iomemtype, i;
2020
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2021
2022
if (revision && strncmp(revision, "pxa27", 5)) {
2023
fprintf(stderr, "Machine requires a PXA27x processor.\n");
2024
exit(1);
2025
}
2026
2027
s->env = cpu_init();
2028
cpu_arm_set_model(s->env, revision ?: "pxa270");
2029
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
2030
2031
/* SDRAM & Internal Memory Storage */
2032
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2033
sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2034
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2035
0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2036
2037
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2038
2039
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2040
2041
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2042
s->pic[PXA27X_PIC_OST_4_11]);
2043
2044
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2045
2046
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
2047
2048
for (i = 0; pxa270_serial[i].io_base; i ++)
2049
if (serial_hds[i])
2050
serial_mm_init(pxa270_serial[i].io_base, 2,
2051
s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
2052
else
2053
break;
2054
if (serial_hds[i])
2055
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2056
s->dma, serial_hds[i]);
2057
2058
if (ds)
2059
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2060
2061
s->cm_base = 0x41300000;
2062
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2063
s->clkcfg = 0x00000009; /* Turbo mode active */
2064
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2065
pxa2xx_cm_writefn, s);
2066
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2067
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2068
2069
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2070
2071
s->mm_base = 0x48000000;
2072
s->mm_regs[MDMRS >> 2] = 0x00020002;
2073
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2074
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2075
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2076
pxa2xx_mm_writefn, s);
2077
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2078
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2079
2080
s->pm_base = 0x40f00000;
2081
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2082
pxa2xx_pm_writefn, s);
2083
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2084
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2085
2086
for (i = 0; pxa27x_ssp[i].io_base; i ++);
2087
s->ssp = (struct pxa2xx_ssp_s **)
2088
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2089
ssp = (struct pxa2xx_ssp_s *)
2090
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2091
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2092
s->ssp[i] = &ssp[i];
2093
ssp[i].base = pxa27x_ssp[i].io_base;
2094
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2095
2096
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2097
pxa2xx_ssp_writefn, &ssp[i]);
2098
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2099
register_savevm("pxa2xx_ssp", i, 0,
2100
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2101
}
2102
2103
if (usb_enabled) {
2104
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2105
}
2106
2107
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2108
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2109
2110
s->rtc_base = 0x40900000;
2111
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2112
pxa2xx_rtc_writefn, s);
2113
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2114
pxa2xx_rtc_init(s);
2115
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2116
2117
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2118
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2119
2120
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2121
2122
/* GPIO1 resets the processor */
2123
/* The handler can be overridden by board-specific code */
2124
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
2125
return s;
2126
}
2127
2128
/* Initialise a PXA255 integrated chip (ARM based core). */
2129
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2130
DisplayState *ds)
2131
{
2132
struct pxa2xx_state_s *s;
2133
struct pxa2xx_ssp_s *ssp;
2134
int iomemtype, i;
2135
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2136
2137
s->env = cpu_init();
2138
cpu_arm_set_model(s->env, "pxa255");
2139
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
2140
2141
/* SDRAM & Internal Memory Storage */
2142
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2143
qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2144
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2145
qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2146
2147
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2148
2149
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2150
2151
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2152
2153
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2154
2155
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
2156
2157
for (i = 0; pxa255_serial[i].io_base; i ++)
2158
if (serial_hds[i])
2159
serial_mm_init(pxa255_serial[i].io_base, 2,
2160
s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
2161
else
2162
break;
2163
if (serial_hds[i])
2164
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2165
s->dma, serial_hds[i]);
2166
2167
if (ds)
2168
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2169
2170
s->cm_base = 0x41300000;
2171
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2172
s->clkcfg = 0x00000009; /* Turbo mode active */
2173
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2174
pxa2xx_cm_writefn, s);
2175
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2176
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2177
2178
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2179
2180
s->mm_base = 0x48000000;
2181
s->mm_regs[MDMRS >> 2] = 0x00020002;
2182
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2183
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2184
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2185
pxa2xx_mm_writefn, s);
2186
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2187
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2188
2189
s->pm_base = 0x40f00000;
2190
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2191
pxa2xx_pm_writefn, s);
2192
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2193
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2194
2195
for (i = 0; pxa255_ssp[i].io_base; i ++);
2196
s->ssp = (struct pxa2xx_ssp_s **)
2197
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2198
ssp = (struct pxa2xx_ssp_s *)
2199
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2200
for (i = 0; pxa255_ssp[i].io_base; i ++) {
2201
s->ssp[i] = &ssp[i];
2202
ssp[i].base = pxa255_ssp[i].io_base;
2203
ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2204
2205
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2206
pxa2xx_ssp_writefn, &ssp[i]);
2207
cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
2208
register_savevm("pxa2xx_ssp", i, 0,
2209
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
2210
}
2211
2212
if (usb_enabled) {
2213
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2214
}
2215
2216
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2217
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2218
2219
s->rtc_base = 0x40900000;
2220
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2221
pxa2xx_rtc_writefn, s);
2222
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2223
pxa2xx_rtc_init(s);
2224
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2225
2226
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2227
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2228
2229
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2230
2231
/* GPIO1 resets the processor */
2232
/* The handler can be overridden by board-specific code */
2233
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
2234
return s;
2235
}
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Version: 2.0.1