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- Committer: Bazaar Package Importer
- Author(s): Soren Hansen
- Date: 2007-10-22 17:07:29 UTC
- mto: (1.5.1) (10.1.1 squeeze) (11.1.1 experimental) (12.1.1 sid) (6.1.1 sid)
- mto: This revision was merged to the branch mainline in revision 3.
- Revision ID: james.westby@ubuntu.com-20071022170729-4ihaxntpl01xg29n
Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816
- files added:
- block-parallels.c
- linux-user/alpha
- linux-user/ppc64
- linux-user/x86_64
- target-alpha
- files removed:
- linux-user/m68k-semi.c
- files modified:
- Changelog
added
removed
target-mips/translate.c
305
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};
306
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307
307
/* MFMC0 opcodes */
308
#define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
308
#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
309
309
310
310
enum {
311
311
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
333
333
OPC_MFC1 = (0x00 << 21) | OPC_CP1,
334
334
OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
335
335
OPC_CFC1 = (0x02 << 21) | OPC_CP1,
336
OPC_MFHCI = (0x03 << 21) | OPC_CP1,
336
OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
337
337
OPC_MTC1 = (0x04 << 21) | OPC_CP1,
338
338
OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
339
339
OPC_CTC1 = (0x06 << 21) | OPC_CP1,
340
OPC_MTHCI = (0x07 << 21) | OPC_CP1,
340
OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
341
341
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
342
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
343
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
342
344
OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
343
345
OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
344
346
OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
345
347
OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
346
348
OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
347
349
OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
350
OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */
348
351
};
349
352
353
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
354
#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
355
350
356
enum {
351
357
OPC_BC1F = (0x00 << 16) | OPC_BC1,
352
358
OPC_BC1T = (0x01 << 16) | OPC_BC1,
354
360
OPC_BC1TL = (0x03 << 16) | OPC_BC1,
355
361
};
356
362
357
#define MASK_CP1_BCOND(op) MASK_CP1(op) | (op & (0x3 << 16))
358
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
363
enum {
364
OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
365
OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
366
};
367
368
enum {
369
OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
370
OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
371
};
359
372
360
373
#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361
#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
374
375
enum {
376
OPC_MFC2 = (0x00 << 21) | OPC_CP2,
377
OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
378
OPC_CFC2 = (0x02 << 21) | OPC_CP2,
379
OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
380
OPC_MTC2 = (0x04 << 21) | OPC_CP2,
381
OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
382
OPC_CTC2 = (0x06 << 21) | OPC_CP2,
383
OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
384
OPC_BC2 = (0x08 << 21) | OPC_CP2,
385
};
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#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
388
389
enum {
390
OPC_LWXC1 = 0x00 | OPC_CP3,
391
OPC_LDXC1 = 0x01 | OPC_CP3,
392
OPC_LUXC1 = 0x05 | OPC_CP3,
393
OPC_SWXC1 = 0x08 | OPC_CP3,
394
OPC_SDXC1 = 0x09 | OPC_CP3,
395
OPC_SUXC1 = 0x0D | OPC_CP3,
396
OPC_PREFX = 0x0F | OPC_CP3,
397
OPC_ALNV_PS = 0x1E | OPC_CP3,
398
OPC_MADD_S = 0x20 | OPC_CP3,
399
OPC_MADD_D = 0x21 | OPC_CP3,
400
OPC_MADD_PS = 0x26 | OPC_CP3,
401
OPC_MSUB_S = 0x28 | OPC_CP3,
402
OPC_MSUB_D = 0x29 | OPC_CP3,
403
OPC_MSUB_PS = 0x2E | OPC_CP3,
404
OPC_NMADD_S = 0x30 | OPC_CP3,
405
OPC_NMADD_D = 0x31 | OPC_CP3,
406
OPC_NMADD_PS= 0x36 | OPC_CP3,
407
OPC_NMSUB_S = 0x38 | OPC_CP3,
408
OPC_NMSUB_D = 0x39 | OPC_CP3,
409
OPC_NMSUB_PS= 0x3E | OPC_CP3,
410
};
411
362
412
363
413
const unsigned char *regnames[] =
364
414
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
367
417
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
368
418
369
419
/* Warning: no function for r0 register (hard wired to zero) */
370
#define GEN32(func, NAME) \
371
static GenOpFunc *NAME ## _table [32] = { \
372
NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
373
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
374
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
375
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
376
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
377
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
378
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
379
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
380
}; \
381
static inline void func(int n) \
382
{ \
383
NAME ## _table[n](); \
420
#define GEN32(func, NAME) \
421
static GenOpFunc *NAME ## _table [32] = { \
422
NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
423
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
424
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
425
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
426
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
427
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
428
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
429
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
430
}; \
431
static inline void func(int n) \
432
{ \
433
NAME ## _table[n](); \
384
434
}
385
435
386
436
/* General purpose registers moves */
391
441
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
392
442
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
393
443
394
#ifdef MIPS_USES_FPU
395
396
444
static const char *fregnames[] =
397
445
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
398
446
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
399
447
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
400
448
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
401
449
402
# define SFGEN32(func, NAME) \
403
static GenOpFunc *NAME ## _table [32] = { \
404
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
405
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
406
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
407
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
408
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
409
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
410
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
411
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
412
}; \
413
static inline void func(int n) \
414
{ \
415
NAME ## _table[n](); \
416
}
417
418
# define DFGEN32(func, NAME) \
419
static GenOpFunc *NAME ## _table [32] = { \
420
NAME ## 0, 0, NAME ## 2, 0, \
421
NAME ## 4, 0, NAME ## 6, 0, \
422
NAME ## 8, 0, NAME ## 10, 0, \
423
NAME ## 12, 0, NAME ## 14, 0, \
424
NAME ## 16, 0, NAME ## 18, 0, \
425
NAME ## 20, 0, NAME ## 22, 0, \
426
NAME ## 24, 0, NAME ## 26, 0, \
427
NAME ## 28, 0, NAME ## 30, 0, \
428
}; \
429
static inline void func(int n) \
430
{ \
431
NAME ## _table[n](); \
432
}
433
434
SFGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr);
435
SFGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr);
436
437
SFGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr);
438
SFGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr);
439
440
SFGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr);
441
SFGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr);
442
443
DFGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr);
444
DFGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr);
445
446
DFGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr);
447
DFGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr);
448
449
DFGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr);
450
DFGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr);
451
452
#define FOP_CONDS(fmt) \
453
static GenOpFunc * cond_ ## fmt ## _table[16] = { \
454
gen_op_cmp_ ## fmt ## _f, \
455
gen_op_cmp_ ## fmt ## _un, \
456
gen_op_cmp_ ## fmt ## _eq, \
457
gen_op_cmp_ ## fmt ## _ueq, \
458
gen_op_cmp_ ## fmt ## _olt, \
459
gen_op_cmp_ ## fmt ## _ult, \
460
gen_op_cmp_ ## fmt ## _ole, \
461
gen_op_cmp_ ## fmt ## _ule, \
462
gen_op_cmp_ ## fmt ## _sf, \
463
gen_op_cmp_ ## fmt ## _ngle, \
464
gen_op_cmp_ ## fmt ## _seq, \
465
gen_op_cmp_ ## fmt ## _ngl, \
466
gen_op_cmp_ ## fmt ## _lt, \
467
gen_op_cmp_ ## fmt ## _nge, \
468
gen_op_cmp_ ## fmt ## _le, \
469
gen_op_cmp_ ## fmt ## _ngt, \
450
#define FGEN32(func, NAME) \
451
static GenOpFunc *NAME ## _table [32] = { \
452
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
453
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
454
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
455
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
456
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
457
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
458
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
459
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
460
}; \
461
static inline void func(int n) \
462
{ \
463
NAME ## _table[n](); \
464
}
465
466
FGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr);
467
FGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr);
468
469
FGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr);
470
FGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr);
471
472
FGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr);
473
FGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr);
474
475
FGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr);
476
FGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr);
477
478
FGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr);
479
FGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr);
480
481
FGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr);
482
FGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr);
483
484
FGEN32(gen_op_load_fpr_WTH0, gen_op_load_fpr_WTH0_fpr);
485
FGEN32(gen_op_store_fpr_WTH0, gen_op_store_fpr_WTH0_fpr);
486
487
FGEN32(gen_op_load_fpr_WTH1, gen_op_load_fpr_WTH1_fpr);
488
FGEN32(gen_op_store_fpr_WTH1, gen_op_store_fpr_WTH1_fpr);
489
490
FGEN32(gen_op_load_fpr_WTH2, gen_op_load_fpr_WTH2_fpr);
491
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr);
492
493
#define FOP_CONDS(type, fmt) \
494
static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
495
gen_op_cmp ## type ## _ ## fmt ## _f, \
496
gen_op_cmp ## type ## _ ## fmt ## _un, \
497
gen_op_cmp ## type ## _ ## fmt ## _eq, \
498
gen_op_cmp ## type ## _ ## fmt ## _ueq, \
499
gen_op_cmp ## type ## _ ## fmt ## _olt, \
500
gen_op_cmp ## type ## _ ## fmt ## _ult, \
501
gen_op_cmp ## type ## _ ## fmt ## _ole, \
502
gen_op_cmp ## type ## _ ## fmt ## _ule, \
503
gen_op_cmp ## type ## _ ## fmt ## _sf, \
504
gen_op_cmp ## type ## _ ## fmt ## _ngle, \
505
gen_op_cmp ## type ## _ ## fmt ## _seq, \
506
gen_op_cmp ## type ## _ ## fmt ## _ngl, \
507
gen_op_cmp ## type ## _ ## fmt ## _lt, \
508
gen_op_cmp ## type ## _ ## fmt ## _nge, \
509
gen_op_cmp ## type ## _ ## fmt ## _le, \
510
gen_op_cmp ## type ## _ ## fmt ## _ngt, \
470
511
}; \
471
static inline void gen_cmp_ ## fmt(int n) \
512
static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
472
513
{ \
473
cond_ ## fmt ## _table[n](); \
514
gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
474
515
}
475
516
476
FOP_CONDS(d)
477
FOP_CONDS(s)
478
479
#endif /* MIPS_USES_FPU */
517
FOP_CONDS(, d)
518
FOP_CONDS(abs, d)
519
FOP_CONDS(, s)
520
FOP_CONDS(abs, s)
521
FOP_CONDS(, ps)
522
FOP_CONDS(abs, ps)
480
523
481
524
typedef struct DisasContext {
482
525
struct TranslationBlock *tb;
483
526
target_ulong pc, saved_pc;
484
527
uint32_t opcode;
528
uint32_t fp_status;
485
529
/* Routine used to access memory */
486
530
int mem_idx;
487
531
uint32_t hflags, saved_hflags;
488
uint32_t CP0_Status;
489
532
int bstate;
490
533
target_ulong btarget;
491
534
} DisasContext;
499
542
BS_EXCP = 3, /* We reached an exception condition */
500
543
};
501
544
502
#if defined MIPS_DEBUG_DISAS
545
#ifdef MIPS_DEBUG_DISAS
503
546
#define MIPS_DEBUG(fmt, args...) \
504
547
do { \
505
548
if (loglevel & CPU_LOG_TB_IN_ASM) { \
506
fprintf(logfile, TLSZ ": %08x " fmt "\n", \
549
fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
507
550
ctx->pc, ctx->opcode , ##args); \
508
551
} \
509
552
} while (0)
526
569
} \
527
570
} while (0)
528
571
529
#define GEN_LOAD_IMM_TN(Tn, Imm) \
530
do { \
531
if (Imm == 0) { \
532
glue(gen_op_reset_, Tn)(); \
533
} else { \
534
glue(gen_op_set_, Tn)(Imm); \
535
} \
536
} while (0)
572
#ifdef TARGET_MIPS64
573
#define GEN_LOAD_IMM_TN(Tn, Imm) \
574
do { \
575
if (Imm == 0) { \
576
glue(gen_op_reset_, Tn)(); \
577
} else if ((int32_t)Imm == Imm) { \
578
glue(gen_op_set_, Tn)(Imm); \
579
} else { \
580
glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
581
} \
582
} while (0)
583
#else
584
#define GEN_LOAD_IMM_TN(Tn, Imm) \
585
do { \
586
if (Imm == 0) { \
587
glue(gen_op_reset_, Tn)(); \
588
} else { \
589
glue(gen_op_set_, Tn)(Imm); \
590
} \
591
} while (0)
592
#endif
537
593
538
594
#define GEN_STORE_TN_REG(Rn, Tn) \
539
595
do { \
552
608
glue(gen_op_store_fpr_, FTn)(Fn); \
553
609
} while (0)
554
610
611
static inline void gen_save_pc(target_ulong pc)
612
{
613
#ifdef TARGET_MIPS64
614
if (pc == (int32_t)pc) {
615
gen_op_save_pc(pc);
616
} else {
617
gen_op_save_pc64(pc >> 32, (uint32_t)pc);
618
}
619
#else
620
gen_op_save_pc(pc);
621
#endif
622
}
623
624
static inline void gen_save_btarget(target_ulong btarget)
625
{
626
#ifdef TARGET_MIPS64
627
if (btarget == (int32_t)btarget) {
628
gen_op_save_btarget(btarget);
629
} else {
630
gen_op_save_btarget64(btarget >> 32, (uint32_t)btarget);
631
}
632
#else
633
gen_op_save_btarget(btarget);
634
#endif
635
}
636
555
637
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
556
638
{
557
639
#if defined MIPS_DEBUG_DISAS
561
643
}
562
644
#endif
563
645
if (do_save_pc && ctx->pc != ctx->saved_pc) {
564
gen_op_save_pc(ctx->pc);
646
gen_save_pc(ctx->pc);
565
647
ctx->saved_pc = ctx->pc;
566
648
}
567
649
if (ctx->hflags != ctx->saved_hflags) {
568
650
gen_op_save_state(ctx->hflags);
569
651
ctx->saved_hflags = ctx->hflags;
570
if (ctx->hflags & MIPS_HFLAG_BR) {
652
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
653
case MIPS_HFLAG_BR:
571
654
gen_op_save_breg_target();
572
} else if (ctx->hflags & MIPS_HFLAG_B) {
573
gen_op_save_btarget(ctx->btarget);
574
} else if (ctx->hflags & MIPS_HFLAG_BMASK) {
655
break;
656
case MIPS_HFLAG_BC:
575
657
gen_op_save_bcond();
576
gen_op_save_btarget(ctx->btarget);
658
/* fall through */
659
case MIPS_HFLAG_BL:
660
/* bcond was already saved by the BL insn */
661
/* fall through */
662
case MIPS_HFLAG_B:
663
gen_save_btarget(ctx->btarget);
664
break;
577
665
}
578
666
}
579
667
}
580
668
669
static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
670
{
671
ctx->saved_hflags = ctx->hflags;
672
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
673
case MIPS_HFLAG_BR:
674
gen_op_restore_breg_target();
675
break;
676
case MIPS_HFLAG_B:
677
ctx->btarget = env->btarget;
678
break;
679
case MIPS_HFLAG_BC:
680
case MIPS_HFLAG_BL:
681
ctx->btarget = env->btarget;
682
gen_op_restore_bcond();
683
break;
684
}
685
}
686
581
687
static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
582
688
{
583
689
#if defined MIPS_DEBUG_DISAS
597
703
generate_exception_err (ctx, excp, 0);
598
704
}
599
705
706
static inline void check_cp1_enabled(DisasContext *ctx)
707
{
708
if (!(ctx->hflags & MIPS_HFLAG_FPU))
709
generate_exception_err(ctx, EXCP_CpU, 1);
710
}
711
712
static inline void check_cp1_64bitmode(DisasContext *ctx)
713
{
714
if (!(ctx->hflags & MIPS_HFLAG_F64))
715
generate_exception(ctx, EXCP_RI);
716
}
717
718
/*
719
* Verify if floating point register is valid; an operation is not defined
720
* if bit 0 of any register specification is set and the FR bit in the
721
* Status register equals zero, since the register numbers specify an
722
* even-odd pair of adjacent coprocessor general registers. When the FR bit
723
* in the Status register equals one, both even and odd register numbers
724
* are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
725
*
726
* Multiple 64 bit wide registers can be checked by calling
727
* gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
728
*/
729
void check_cp1_registers(DisasContext *ctx, int regs)
730
{
731
if (!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))
732
generate_exception(ctx, EXCP_RI);
733
}
734
735
/* This code generates a "reserved instruction" exception if the
736
CPU is not a MIPS R2 (or higher) CPU. */
737
static inline void check_mips_r2(CPUState *env, DisasContext *ctx)
738
{
739
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) < (1 << CP0C0_AR))
740
generate_exception(ctx, EXCP_RI);
741
}
742
600
743
#if defined(CONFIG_USER_ONLY)
601
744
#define op_ldst(name) gen_op_##name##_raw()
602
745
#define OP_LD_TABLE(width)
615
758
}
616
759
#endif
617
760
618
#ifdef MIPS_HAS_MIPS64
761
#ifdef TARGET_MIPS64
619
762
OP_LD_TABLE(d);
620
763
OP_LD_TABLE(dl);
621
764
OP_LD_TABLE(dr);
624
767
OP_ST_TABLE(dr);
625
768
OP_LD_TABLE(ld);
626
769
OP_ST_TABLE(cd);
770
OP_LD_TABLE(wu);
627
771
#endif
628
772
OP_LD_TABLE(w);
629
OP_LD_TABLE(wu);
630
773
OP_LD_TABLE(wl);
631
774
OP_LD_TABLE(wr);
632
775
OP_ST_TABLE(w);
640
783
OP_ST_TABLE(b);
641
784
OP_LD_TABLE(l);
642
785
OP_ST_TABLE(c);
643
#ifdef MIPS_USES_FPU
644
786
OP_LD_TABLE(wc1);
645
787
OP_ST_TABLE(wc1);
646
788
OP_LD_TABLE(dc1);
647
789
OP_ST_TABLE(dc1);
648
#endif
790
OP_LD_TABLE(uxc1);
791
OP_ST_TABLE(uxc1);
649
792
650
793
/* Load and store */
651
794
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
652
795
int base, int16_t offset)
653
796
{
654
const char *opn = "unk";
797
const char *opn = "ldst";
655
798
656
799
if (base == 0) {
657
800
GEN_LOAD_IMM_TN(T0, offset);
660
803
} else {
661
804
gen_op_load_gpr_T0(base);
662
805
gen_op_set_T1(offset);
663
gen_op_add();
806
gen_op_addr_add();
664
807
}
665
808
/* Don't do NOP if destination is zero: we must perform the actual
666
809
* memory access
667
810
*/
668
811
switch (opc) {
669
#ifdef MIPS_HAS_MIPS64
812
#ifdef TARGET_MIPS64
813
case OPC_LWU:
814
op_ldst(lwu);
815
GEN_STORE_TN_REG(rt, T0);
816
opn = "lwu";
817
break;
670
818
case OPC_LD:
671
819
op_ldst(ld);
672
820
GEN_STORE_TN_REG(rt, T0);
683
831
opn = "sd";
684
832
break;
685
833
case OPC_SCD:
834
save_cpu_state(ctx, 1);
686
835
GEN_LOAD_REG_TN(T1, rt);
687
836
op_ldst(scd);
837
GEN_STORE_TN_REG(rt, T0);
688
838
opn = "scd";
689
839
break;
690
840
case OPC_LDL:
841
GEN_LOAD_REG_TN(T1, rt);
691
842
op_ldst(ldl);
692
843
GEN_STORE_TN_REG(rt, T0);
693
844
opn = "ldl";
698
849
opn = "sdl";
699
850
break;
700
851
case OPC_LDR:
852
GEN_LOAD_REG_TN(T1, rt);
701
853
op_ldst(ldr);
702
854
GEN_STORE_TN_REG(rt, T0);
703
855
opn = "ldr";
713
865
GEN_STORE_TN_REG(rt, T0);
714
866
opn = "lw";
715
867
break;
716
case OPC_LWU:
717
op_ldst(lwu);
718
GEN_STORE_TN_REG(rt, T0);
719
opn = "lwu";
720
break;
721
868
case OPC_SW:
722
869
GEN_LOAD_REG_TN(T1, rt);
723
870
op_ldst(sw);
781
928
opn = "ll";
782
929
break;
783
930
case OPC_SC:
931
save_cpu_state(ctx, 1);
784
932
GEN_LOAD_REG_TN(T1, rt);
785
933
op_ldst(sc);
786
934
GEN_STORE_TN_REG(rt, T0);
787
935
opn = "sc";
788
936
break;
789
937
default:
790
MIPS_INVAL("load/store");
938
MIPS_INVAL(opn);
791
939
generate_exception(ctx, EXCP_RI);
792
940
return;
793
941
}
794
942
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
795
943
}
796
944
797
#ifdef MIPS_USES_FPU
798
799
945
/* Load and store */
800
946
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
801
947
int base, int16_t offset)
802
948
{
803
const char *opn = "unk";
949
const char *opn = "flt_ldst";
804
950
805
951
if (base == 0) {
806
952
GEN_LOAD_IMM_TN(T0, offset);
809
955
} else {
810
956
gen_op_load_gpr_T0(base);
811
957
gen_op_set_T1(offset);
812
gen_op_add();
958
gen_op_addr_add();
813
959
}
814
960
/* Don't do NOP if destination is zero: we must perform the actual
815
961
* memory access
836
982
opn = "sdc1";
837
983
break;
838
984
default:
839
MIPS_INVAL("float load/store");
840
generate_exception_err(ctx, EXCP_CpU, 1);
985
MIPS_INVAL(opn);
986
generate_exception(ctx, EXCP_RI);
841
987
return;
842
988
}
843
989
MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
844
990
}
845
991
846
#endif /* MIPS_USES_FPU */
847
848
992
/* Arithmetic with immediate operand */
849
993
static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
850
994
int rs, int16_t imm)
851
995
{
852
uint32_t uimm;
853
const char *opn = "unk";
996
target_ulong uimm;
997
const char *opn = "imm arith";
854
998
855
999
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
856
1000
/* if no destination, treat it as a NOP
859
1003
MIPS_DEBUG("NOP");
860
1004
return;
861
1005
}
862
if (opc == OPC_ADDI || opc == OPC_ADDIU ||
863
opc == OPC_DADDI || opc == OPC_DADDIU ||
864
opc == OPC_SLTI || opc == OPC_SLTIU)
865
uimm = (int32_t)imm; /* Sign extend to 32 bits */
866
else
867
uimm = (uint16_t)imm;
868
if (opc != OPC_LUI) {
869
GEN_LOAD_REG_TN(T0, rs);
870
GEN_LOAD_IMM_TN(T1, uimm);
871
} else {
872
uimm = uimm << 16;
873
GEN_LOAD_IMM_TN(T0, uimm);
1006
uimm = (uint16_t)imm;
1007
switch (opc) {
1008
case OPC_ADDI:
1009
case OPC_ADDIU:
1010
#ifdef TARGET_MIPS64
1011
case OPC_DADDI:
1012
case OPC_DADDIU:
1013
#endif
1014
case OPC_SLTI:
1015
case OPC_SLTIU:
1016
uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1017
/* Fall through. */
1018
case OPC_ANDI:
1019
case OPC_ORI:
1020
case OPC_XORI:
1021
GEN_LOAD_REG_TN(T0, rs);
1022
GEN_LOAD_IMM_TN(T1, uimm);
1023
break;
1024
case OPC_LUI:
1025
GEN_LOAD_IMM_TN(T0, imm << 16);
1026
break;
1027
case OPC_SLL:
1028
case OPC_SRA:
1029
case OPC_SRL:
1030
#ifdef TARGET_MIPS64
1031
case OPC_DSLL:
1032
case OPC_DSRA:
1033
case OPC_DSRL:
1034
case OPC_DSLL32:
1035
case OPC_DSRA32:
1036
case OPC_DSRL32:
1037
#endif
1038
uimm &= 0x1f;
1039
GEN_LOAD_REG_TN(T0, rs);
1040
GEN_LOAD_IMM_TN(T1, uimm);
1041
break;
874
1042
}
875
1043
switch (opc) {
876
1044
case OPC_ADDI:
882
1050
gen_op_add();
883
1051
opn = "addiu";
884
1052
break;
885
#ifdef MIPS_HAS_MIPS64
1053
#ifdef TARGET_MIPS64
886
1054
case OPC_DADDI:
887
1055
save_cpu_state(ctx, 1);
888
1056
gen_op_daddo();
925
1093
opn = "sra";
926
1094
break;
927
1095
case OPC_SRL:
928
if ((ctx->opcode >> 21) & 1) {
1096
switch ((ctx->opcode >> 21) & 0x1f) {
1097
case 0:
1098
gen_op_srl();
1099
opn = "srl";
1100
break;
1101
case 1:
929
1102
gen_op_rotr();
930
1103
opn = "rotr";
931
} else {
932
gen_op_srl();
933
opn = "srl";
934
}
1104
break;
1105
default:
1106
MIPS_INVAL("invalid srl flag");
1107
generate_exception(ctx, EXCP_RI);
1108
break;
1109
}
935
1110
break;
936
#ifdef MIPS_HAS_MIPS64
1111
#ifdef TARGET_MIPS64
937
1112
case OPC_DSLL:
938
1113
gen_op_dsll();
939
1114
opn = "dsll";
943
1118
opn = "dsra";
944
1119
break;
945
1120
case OPC_DSRL:
946
if ((ctx->opcode >> 21) & 1) {
1121
switch ((ctx->opcode >> 21) & 0x1f) {
1122
case 0:
1123
gen_op_dsrl();
1124
opn = "dsrl";
1125
break;
1126
case 1:
947
1127
gen_op_drotr();
948
1128
opn = "drotr";
949
} else {
950
gen_op_dsrl();
951
opn = "dsrl";
952
}
1129
break;
1130
default:
1131
MIPS_INVAL("invalid dsrl flag");
1132
generate_exception(ctx, EXCP_RI);
1133
break;
1134
}
953
1135
break;
954
1136
case OPC_DSLL32:
955
1137
gen_op_dsll32();
960
1142
opn = "dsra32";
961
1143
break;
962
1144
case OPC_DSRL32:
963
if ((ctx->opcode >> 21) & 1) {
1145
switch ((ctx->opcode >> 21) & 0x1f) {
1146
case 0:
1147
gen_op_dsrl32();
1148
opn = "dsrl32";
1149
break;
1150
case 1:
964
1151
gen_op_drotr32();
965
1152
opn = "drotr32";
966
} else {
967
gen_op_dsrl32();
968
opn = "dsrl32";
969
}
1153
break;
1154
default:
1155
MIPS_INVAL("invalid dsrl32 flag");
1156
generate_exception(ctx, EXCP_RI);
1157
break;
1158
}
970
1159
break;
971
1160
#endif
972
1161
default:
973
MIPS_INVAL("imm arith");
1162
MIPS_INVAL(opn);
974
1163
generate_exception(ctx, EXCP_RI);
975
1164
return;
976
1165
}
977
1166
GEN_STORE_TN_REG(rt, T0);
978
MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
1167
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
979
1168
}
980
1169
981
1170
/* Arithmetic */
982
1171
static void gen_arith (DisasContext *ctx, uint32_t opc,
983
1172
int rd, int rs, int rt)
984
1173
{
985
const char *opn = "unk";
1174
const char *opn = "arith";
986
1175
987
1176
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
988
1177
&& opc != OPC_DADD && opc != OPC_DSUB) {
1013
1202
gen_op_sub();
1014
1203
opn = "subu";
1015
1204
break;
1016
#ifdef MIPS_HAS_MIPS64
1205
#ifdef TARGET_MIPS64
1017
1206
case OPC_DADD:
1018
1207
save_cpu_state(ctx, 1);
1019
1208
gen_op_daddo();
1078
1267
opn = "srav";
1079
1268
break;
1080
1269
case OPC_SRLV:
1081
if ((ctx->opcode >> 6) & 1) {
1270
switch ((ctx->opcode >> 6) & 0x1f) {
1271
case 0:
1272
gen_op_srlv();
1273
opn = "srlv";
1274
break;
1275
case 1:
1082
1276
gen_op_rotrv();
1083
1277
opn = "rotrv";
1084
} else {
1085
gen_op_srlv();
1086
opn = "srlv";
1087
}
1278
break;
1279
default:
1280
MIPS_INVAL("invalid srlv flag");
1281
generate_exception(ctx, EXCP_RI);
1282
break;
1283
}
1088
1284
break;
1089
#ifdef MIPS_HAS_MIPS64
1285
#ifdef TARGET_MIPS64
1090
1286
case OPC_DSLLV:
1091
1287
gen_op_dsllv();
1092
1288
opn = "dsllv";
1096
1292
opn = "dsrav";
1097
1293
break;
1098
1294
case OPC_DSRLV:
1099
if ((ctx->opcode >> 6) & 1) {
1295
switch ((ctx->opcode >> 6) & 0x1f) {
1296
case 0:
1297
gen_op_dsrlv();
1298
opn = "dsrlv";
1299
break;
1300
case 1:
1100
1301
gen_op_drotrv();
1101
1302
opn = "drotrv";
1102
} else {
1103
gen_op_dsrlv();
1104
opn = "dsrlv";
1105
}
1303
break;
1304
default:
1305
MIPS_INVAL("invalid dsrlv flag");
1306
generate_exception(ctx, EXCP_RI);
1307
break;
1308
}
1106
1309
break;
1107
1310
#endif
1108
1311
default:
1109
MIPS_INVAL("arith");
1312
MIPS_INVAL(opn);
1110
1313
generate_exception(ctx, EXCP_RI);
1111
1314
return;
1112
1315
}
1118
1321
/* Arithmetic on HI/LO registers */
1119
1322
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1120
1323
{
1121
const char *opn = "unk";
1324
const char *opn = "hilo";
1122
1325
1123
1326
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1124
1327
/* Treat as a NOP */
1147
1350
opn = "mtlo";
1148
1351
break;
1149
1352
default:
1150
MIPS_INVAL("HILO");
1353
MIPS_INVAL(opn);
1151
1354
generate_exception(ctx, EXCP_RI);
1152
1355
return;
1153
1356
}
1157
1360
static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1158
1361
int rs, int rt)
1159
1362
{
1160
const char *opn = "unk";
1363
const char *opn = "mul/div";
1161
1364
1162
1365
GEN_LOAD_REG_TN(T0, rs);
1163
1366
GEN_LOAD_REG_TN(T1, rt);
1178
1381
gen_op_multu();
1179
1382
opn = "multu";
1180
1383
break;
1181
#ifdef MIPS_HAS_MIPS64
1384
#ifdef TARGET_MIPS64
1182
1385
case OPC_DDIV:
1183
1386
gen_op_ddiv();
1184
1387
opn = "ddiv";
1213
1416
opn = "msubu";
1214
1417
break;
1215
1418
default:
1216
MIPS_INVAL("mul/div");
1419
MIPS_INVAL(opn);
1217
1420
generate_exception(ctx, EXCP_RI);
1218
1421
return;
1219
1422
}
1223
1426
static void gen_cl (DisasContext *ctx, uint32_t opc,
1224
1427
int rd, int rs)
1225
1428
{
1226
const char *opn = "unk";
1429
const char *opn = "CLx";
1227
1430
if (rd == 0) {
1228
1431
/* Treat as a NOP */
1229
1432
MIPS_DEBUG("NOP");
1239
1442
gen_op_clz();
1240
1443
opn = "clz";
1241
1444
break;
1242
#ifdef MIPS_HAS_MIPS64
1445
#ifdef TARGET_MIPS64
1243
1446
case OPC_DCLO:
1244
1447
gen_op_dclo();
1245
1448
opn = "dclo";
1250
1453
break;
1251
1454
#endif
1252
1455
default:
1253
MIPS_INVAL("CLx");
1456
MIPS_INVAL(opn);
1254
1457
generate_exception(ctx, EXCP_RI);
1255
1458
return;
1256
1459
}
1314
1517
/* Never trap: treat as NOP */
1315
1518
return;
1316
1519
default:
1317
MIPS_INVAL("TRAP");
1520
MIPS_INVAL("trap");
1318
1521
generate_exception(ctx, EXCP_RI);
1319
1522
return;
1320
1523
}
1345
1548
gen_op_ne();
1346
1549
break;
1347
1550
default:
1348
MIPS_INVAL("TRAP");
1551
MIPS_INVAL("trap");
1349
1552
generate_exception(ctx, EXCP_RI);
1350
1553
return;
1351
1554
}
1364
1567
gen_op_goto_tb0(TBPARAM(tb));
1365
1568
else
1366
1569
gen_op_goto_tb1(TBPARAM(tb));
1367
gen_op_save_pc(dest);
1570
gen_save_pc(dest);
1368
1571
gen_op_set_T0((long)tb + n);
1369
gen_op_exit_tb();
1370
1572
} else {
1371
gen_op_save_pc(dest);
1372
gen_op_set_T0(0);
1373
gen_op_exit_tb();
1573
gen_save_pc(dest);
1574
gen_op_reset_T0();
1374
1575
}
1576
gen_op_exit_tb();
1375
1577
}
1376
1578
1377
1579
/* Branches (before delay slot) */
1378
1580
static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1379
1581
int rs, int rt, int32_t offset)
1380
1582
{
1381
target_ulong btarget;
1382
int blink, bcond;
1383
1384
btarget = -1;
1385
blink = 0;
1386
bcond = 0;
1583
target_ulong btarget = -1;
1584
int blink = 0;
1585
int bcond = 0;
1586
1587
if (ctx->hflags & MIPS_HFLAG_BMASK) {
1588
#ifdef MIPS_DEBUG_DISAS
1589
if (loglevel & CPU_LOG_TB_IN_ASM) {
1590
fprintf(logfile,
1591
"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
1592
ctx->pc);
1593
}
1594
#endif
1595
generate_exception(ctx, EXCP_RI);
1596
return;
1597
}
1598
1387
1599
/* Load needed operands */
1388
1600
switch (opc) {
1389
1601
case OPC_BEQ:
1420
1632
case OPC_J:
1421
1633
case OPC_JAL:
1422
1634
/* Jump to immediate */
1423
btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | offset;
1635
btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
1424
1636
break;
1425
1637
case OPC_JR:
1426
1638
case OPC_JALR:
1427
1639
/* Jump to register */
1428
1640
if (offset != 0 && offset != 16) {
1429
1641
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1430
others are reserved. */
1642
others are reserved. */
1643
MIPS_INVAL("jump hint");
1431
1644
generate_exception(ctx, EXCP_RI);
1432
1645
return;
1433
1646
}
1465
1678
MIPS_DEBUG("bnever (NOP)");
1466
1679
return;
1467
1680
case OPC_BLTZAL: /* 0 < 0 */
1468
gen_op_set_T0(ctx->pc + 8);
1681
GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
1469
1682
gen_op_store_T0_gpr(31);
1683
MIPS_DEBUG("bnever and link");
1470
1684
return;
1471
1685
case OPC_BLTZALL: /* 0 < 0 likely */
1472
gen_op_set_T0(ctx->pc + 8);
1686
GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
1473
1687
gen_op_store_T0_gpr(31);
1474
gen_goto_tb(ctx, 0, ctx->pc + 4);
1688
/* Skip the instruction in the delay slot */
1689
MIPS_DEBUG("bnever, link and skip");
1690
ctx->pc += 4;
1475
1691
return;
1476
1692
case OPC_BNEL: /* rx != rx likely */
1477
1693
case OPC_BGTZL: /* 0 > 0 likely */
1478
1694
case OPC_BLTZL: /* 0 < 0 likely */
1479
1695
/* Skip the instruction in the delay slot */
1480
1696
MIPS_DEBUG("bnever and skip");
1481
gen_goto_tb(ctx, 0, ctx->pc + 4);
1697
ctx->pc += 4;
1482
1698
return;
1483
1699
case OPC_J:
1484
1700
ctx->hflags |= MIPS_HFLAG_B;
1485
MIPS_DEBUG("j %08x", btarget);
1701
MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
1486
1702
break;
1487
1703
case OPC_JAL:
1488
1704
blink = 31;
1489
1705
ctx->hflags |= MIPS_HFLAG_B;
1490
MIPS_DEBUG("jal %08x", btarget);
1706
MIPS_DEBUG("jal " TARGET_FMT_lx, btarget);
1491
1707
break;
1492
1708
case OPC_JR:
1493
1709
ctx->hflags |= MIPS_HFLAG_BR;
1507
1723
switch (opc) {
1508
1724
case OPC_BEQ:
1509
1725
gen_op_eq();
1510
MIPS_DEBUG("beq %s, %s, %08x",
1726
MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
1511
1727
regnames[rs], regnames[rt], btarget);
1512
1728
goto not_likely;
1513
1729
case OPC_BEQL:
1514
1730
gen_op_eq();
1515
MIPS_DEBUG("beql %s, %s, %08x",
1731
MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
1516
1732
regnames[rs], regnames[rt], btarget);
1517
1733
goto likely;
1518
1734
case OPC_BNE:
1519
1735
gen_op_ne();
1520
MIPS_DEBUG("bne %s, %s, %08x",
1736
MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
1521
1737
regnames[rs], regnames[rt], btarget);
1522
1738
goto not_likely;
1523
1739
case OPC_BNEL:
1524
1740
gen_op_ne();
1525
MIPS_DEBUG("bnel %s, %s, %08x",
1741
MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
1526
1742
regnames[rs], regnames[rt], btarget);
1527
1743
goto likely;
1528
1744
case OPC_BGEZ:
1529
1745
gen_op_gez();
1530
MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
1746
MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
1531
1747
goto not_likely;
1532
1748
case OPC_BGEZL:
1533
1749
gen_op_gez();
1534
MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
1750
MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1535
1751
goto likely;
1536
1752
case OPC_BGEZAL:
1537
1753
gen_op_gez();
1538
MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
1754
MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
1539
1755
blink = 31;
1540
1756
goto not_likely;
1541
1757
case OPC_BGEZALL:
1542
1758
gen_op_gez();
1543
1759
blink = 31;
1544
MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
1760
MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
1545
1761
goto likely;
1546
1762
case OPC_BGTZ:
1547
1763
gen_op_gtz();
1548
MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
1764
MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
1549
1765
goto not_likely;
1550
1766
case OPC_BGTZL:
1551
1767
gen_op_gtz();
1552
MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
1768
MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1553
1769
goto likely;
1554
1770
case OPC_BLEZ:
1555
1771
gen_op_lez();
1556
MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
1772
MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
1557
1773
goto not_likely;
1558
1774
case OPC_BLEZL:
1559
1775
gen_op_lez();
1560
MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
1776
MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1561
1777
goto likely;
1562
1778
case OPC_BLTZ:
1563
1779
gen_op_ltz();
1564
MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
1780
MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
1565
1781
goto not_likely;
1566
1782
case OPC_BLTZL:
1567
1783
gen_op_ltz();
1568
MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
1784
MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
1569
1785
goto likely;
1570
1786
case OPC_BLTZAL:
1571
1787
gen_op_ltz();
1572
1788
blink = 31;
1573
MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
1789
MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
1574
1790
not_likely:
1575
1791
ctx->hflags |= MIPS_HFLAG_BC;
1792
gen_op_set_bcond();
1576
1793
break;
1577
1794
case OPC_BLTZALL:
1578
1795
gen_op_ltz();
1579
1796
blink = 31;
1580
MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
1797
MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
1581
1798
likely:
1582
1799
ctx->hflags |= MIPS_HFLAG_BL;
1800
gen_op_set_bcond();
1801
gen_op_save_bcond();
1583
1802
break;
1803
default:
1804
MIPS_INVAL("conditional branch/jump");
1805
generate_exception(ctx, EXCP_RI);
1806
return;
1584
1807
}
1585
gen_op_set_bcond();
1586
1808
}
1587
MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1809
MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
1588
1810
blink, ctx->hflags, btarget);
1811
1589
1812
ctx->btarget = btarget;
1590
1813
if (blink > 0) {
1591
gen_op_set_T0(ctx->pc + 8);
1814
GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
1592
1815
gen_op_store_T0_gpr(blink);
1593
1816
}
1594
return;
1595
1817
}
1596
1818
1597
1819
/* special3 bitfield operations */
1621
1843
case OPC_INS:
1622
1844
if (lsb > msb)
1623
1845
goto fail;
1624
GEN_LOAD_REG_TN(T2, rt);
1846
GEN_LOAD_REG_TN(T0, rt);
1625
1847
gen_op_ins(lsb, msb - lsb + 1);
1626
1848
break;
1627
1849
case OPC_DINSM:
1628
1850
if (lsb > msb)
1629
1851
goto fail;
1630
GEN_LOAD_REG_TN(T2, rt);
1852
GEN_LOAD_REG_TN(T0, rt);
1631
1853
gen_op_ins(lsb, msb - lsb + 1 + 32);
1632
1854
break;
1633
1855
case OPC_DINSU:
1634
1856
if (lsb > msb)
1635
1857
goto fail;
1636
GEN_LOAD_REG_TN(T2, rt);
1858
GEN_LOAD_REG_TN(T0, rt);
1637
1859
gen_op_ins(lsb + 32, msb - lsb + 1);
1638
1860
break;
1639
1861
case OPC_DINS:
1640
1862
if (lsb > msb)
1641
1863
goto fail;
1642
GEN_LOAD_REG_TN(T2, rt);
1864
GEN_LOAD_REG_TN(T0, rt);
1643
1865
gen_op_ins(lsb, msb - lsb + 1);
1644
1866
break;
1645
1867
default:
1652
1874
}
1653
1875
1654
1876
/* CP0 (MMU and control) */
1655
static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
1877
static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
1656
1878
{
1657
1879
const char *rn = "invalid";
1658
1880
1660
1882
case 0:
1661
1883
switch (sel) {
1662
1884
case 0:
1663
gen_op_mfc0_index();
1885
gen_op_mfc0_index();
1664
1886
rn = "Index";
1665
1887
break;
1666
1888
case 1:
1667
// gen_op_mfc0_mvpcontrol(); /* MT ASE */
1889
// gen_op_mfc0_mvpcontrol(); /* MT ASE */
1668
1890
rn = "MVPControl";
1669
// break;
1891
// break;
1670
1892
case 2:
1671
// gen_op_mfc0_mvpconf0(); /* MT ASE */
1893
// gen_op_mfc0_mvpconf0(); /* MT ASE */
1672
1894
rn = "MVPConf0";
1673
// break;
1895
// break;
1674
1896
case 3:
1675
// gen_op_mfc0_mvpconf1(); /* MT ASE */
1897
// gen_op_mfc0_mvpconf1(); /* MT ASE */
1676
1898
rn = "MVPConf1";
1677
// break;
1899
// break;
1678
1900
default:
1679
1901
goto die;
1680
1902
}
1684
1906
case 0:
1685
1907
gen_op_mfc0_random();
1686
1908
rn = "Random";
1687
break;
1909
break;
1688
1910
case 1:
1689
// gen_op_mfc0_vpecontrol(); /* MT ASE */
1911
// gen_op_mfc0_vpecontrol(); /* MT ASE */
1690
1912
rn = "VPEControl";
1691
// break;
1913
// break;
1692
1914
case 2:
1693
// gen_op_mfc0_vpeconf0(); /* MT ASE */
1915
// gen_op_mfc0_vpeconf0(); /* MT ASE */
1694
1916
rn = "VPEConf0";
1695
// break;
1917
// break;
1696
1918
case 3:
1697
// gen_op_mfc0_vpeconf1(); /* MT ASE */
1919
// gen_op_mfc0_vpeconf1(); /* MT ASE */
1698
1920
rn = "VPEConf1";
1699
// break;
1921
// break;
1700
1922
case 4:
1701
// gen_op_mfc0_YQMask(); /* MT ASE */
1923
// gen_op_mfc0_YQMask(); /* MT ASE */
1702
1924
rn = "YQMask";
1703
// break;
1925
// break;
1704
1926
case 5:
1705
// gen_op_mfc0_vpeschedule(); /* MT ASE */
1927
// gen_op_mfc0_vpeschedule(); /* MT ASE */
1706
1928
rn = "VPESchedule";
1707
// break;
1929
// break;
1708
1930
case 6:
1709
// gen_op_mfc0_vpeschefback(); /* MT ASE */
1931
// gen_op_mfc0_vpeschefback(); /* MT ASE */
1710
1932
rn = "VPEScheFBack";
1711
// break;
1933
// break;
1712
1934
case 7:
1713
// gen_op_mfc0_vpeopt(); /* MT ASE */
1935
// gen_op_mfc0_vpeopt(); /* MT ASE */
1714
1936
rn = "VPEOpt";
1715
// break;
1937
// break;
1716
1938
default:
1717
1939
goto die;
1718
1940
}
1720
1942
case 2:
1721
1943
switch (sel) {
1722
1944
case 0:
1723
gen_op_mfc0_entrylo0();
1724
rn = "EntryLo0";
1725
break;
1945
gen_op_mfc0_entrylo0();
1946
rn = "EntryLo0";
1947
break;
1726
1948
case 1:
1727
// gen_op_mfc0_tcstatus(); /* MT ASE */
1728
rn = "TCStatus";
1729
// break;
1949
// gen_op_mfc0_tcstatus(); /* MT ASE */
1950
rn = "TCStatus";
1951
// break;
1730
1952
case 2:
1731
// gen_op_mfc0_tcbind(); /* MT ASE */
1732
rn = "TCBind";
1733
// break;
1953
// gen_op_mfc0_tcbind(); /* MT ASE */
1954
rn = "TCBind";
1955
// break;
1734
1956
case 3:
1735
// gen_op_mfc0_tcrestart(); /* MT ASE */
1736
rn = "TCRestart";
1737
// break;
1957
// gen_op_mfc0_tcrestart(); /* MT ASE */
1958
rn = "TCRestart";
1959
// break;
1738
1960
case 4:
1739
// gen_op_mfc0_tchalt(); /* MT ASE */
1740
rn = "TCHalt";
1741
// break;
1961
// gen_op_mfc0_tchalt(); /* MT ASE */
1962
rn = "TCHalt";
1963
// break;
1742
1964
case 5:
1743
// gen_op_mfc0_tccontext(); /* MT ASE */
1744
rn = "TCContext";
1745
// break;
1965
// gen_op_mfc0_tccontext(); /* MT ASE */
1966
rn = "TCContext";
1967
// break;
1746
1968
case 6:
1747
// gen_op_mfc0_tcschedule(); /* MT ASE */
1748
rn = "TCSchedule";
1749
// break;
1969
// gen_op_mfc0_tcschedule(); /* MT ASE */
1970
rn = "TCSchedule";
1971
// break;
1750
1972
case 7:
1751
// gen_op_mfc0_tcschefback(); /* MT ASE */
1752
rn = "TCScheFBack";
1753
// break;
1973
// gen_op_mfc0_tcschefback(); /* MT ASE */
1974
rn = "TCScheFBack";
1975
// break;
1754
1976
default:
1755
1977
goto die;
1756
1978
}
1758
1980
case 3:
1759
1981
switch (sel) {
1760
1982
case 0:
1761
gen_op_mfc0_entrylo1();
1762
rn = "EntryLo1";
1763
break;
1983
gen_op_mfc0_entrylo1();
1984
rn = "EntryLo1";
1985
break;
1764
1986
default:
1765
1987
goto die;
1766
}
1988
}
1767
1989
break;
1768
1990
case 4:
1769
1991
switch (sel) {
1770
1992
case 0:
1771
gen_op_mfc0_context();
1772
rn = "Context";
1773
break;
1993
gen_op_mfc0_context();
1994
rn = "Context";
1995
break;
1774
1996
case 1:
1775
// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1776
rn = "ContextConfig";
1777
// break;
1997
// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1998
rn = "ContextConfig";
1999
// break;
1778
2000
default:
1779
2001
goto die;
1780
}
2002
}
1781
2003
break;
1782
2004
case 5:
1783
2005
switch (sel) {
1784
2006
case 0:
1785
gen_op_mfc0_pagemask();
1786
rn = "PageMask";
1787
break;
2007
gen_op_mfc0_pagemask();
2008
rn = "PageMask";
2009
break;
1788
2010
case 1:
1789
gen_op_mfc0_pagegrain();
1790
rn = "PageGrain";
1791
break;
2011
check_mips_r2(env, ctx);
2012
gen_op_mfc0_pagegrain();
2013
rn = "PageGrain";
2014
break;
1792
2015
default:
1793
2016
goto die;
1794
}
2017
}
1795
2018
break;
1796
2019
case 6:
1797
2020
switch (sel) {
1798
2021
case 0:
1799
gen_op_mfc0_wired();
1800
rn = "Wired";
1801
break;
2022
gen_op_mfc0_wired();
2023
rn = "Wired";
2024
break;
1802
2025
case 1:
1803
// gen_op_mfc0_srsconf0(); /* shadow registers */
1804
rn = "SRSConf0";
1805
// break;
2026
// gen_op_mfc0_srsconf0(); /* shadow registers */
2027
rn = "SRSConf0";
2028
// break;
1806
2029
case 2:
1807
// gen_op_mfc0_srsconf1(); /* shadow registers */
1808
rn = "SRSConf1";
1809
// break;
2030
// gen_op_mfc0_srsconf1(); /* shadow registers */
2031
rn = "SRSConf1";
2032
// break;
1810
2033
case 3:
1811
// gen_op_mfc0_srsconf2(); /* shadow registers */
1812
rn = "SRSConf2";
1813
// break;
2034
// gen_op_mfc0_srsconf2(); /* shadow registers */
2035
rn = "SRSConf2";
2036
// break;
1814
2037
case 4:
1815
// gen_op_mfc0_srsconf3(); /* shadow registers */
1816
rn = "SRSConf3";
1817
// break;
2038
// gen_op_mfc0_srsconf3(); /* shadow registers */
2039
rn = "SRSConf3";
2040
// break;
1818
2041
case 5:
1819
// gen_op_mfc0_srsconf4(); /* shadow registers */
1820
rn = "SRSConf4";
1821
// break;
2042
// gen_op_mfc0_srsconf4(); /* shadow registers */
2043
rn = "SRSConf4";
2044
// break;
1822
2045
default:
1823
2046
goto die;
1824
}
2047
}
1825
2048
break;
1826
2049
case 7:
1827
2050
switch (sel) {
1828
2051
case 0:
1829
gen_op_mfc0_hwrena();
1830
rn = "HWREna";
1831
break;
2052
check_mips_r2(env, ctx);
2053
gen_op_mfc0_hwrena();
2054
rn = "HWREna";
2055
break;
1832
2056
default:
1833
2057
goto die;
1834
}
2058
}
1835
2059
break;
1836
2060
case 8:
1837
2061
switch (sel) {
1838
2062
case 0:
1839
gen_op_mfc0_badvaddr();
1840
rn = "BadVaddr";
1841
break;
2063
gen_op_mfc0_badvaddr();
2064
rn = "BadVaddr";
2065
break;
1842
2066
default:
1843
2067
goto die;
1844
2068
}
1846
2070
case 9:
1847
2071
switch (sel) {
1848
2072
case 0:
1849
gen_op_mfc0_count();
1850
rn = "Count";
1851
break;
1852
/* 6,7 are implementation dependent */
2073
gen_op_mfc0_count();
2074
rn = "Count";
2075
break;
2076
/* 6,7 are implementation dependent */
1853
2077
default:
1854
2078
goto die;
1855
}
2079
}
1856
2080
break;
1857
2081
case 10:
1858
2082
switch (sel) {
1859
2083
case 0:
1860
gen_op_mfc0_entryhi();
1861
rn = "EntryHi";
1862
break;
2084
gen_op_mfc0_entryhi();
2085
rn = "EntryHi";
2086
break;
1863
2087
default:
1864
2088
goto die;
1865
}
2089
}
1866
2090
break;
1867
2091
case 11:
1868
2092
switch (sel) {
1869
2093
case 0:
1870
gen_op_mfc0_compare();
1871
rn = "Compare";
1872
break;
1873
/* 6,7 are implementation dependent */
2094
gen_op_mfc0_compare();
2095
rn = "Compare";
2096
break;
2097
/* 6,7 are implementation dependent */
1874
2098
default:
1875
2099
goto die;
1876
}
2100
}
1877
2101
break;
1878
2102
case 12:
1879
2103
switch (sel) {
1880
2104
case 0:
1881
gen_op_mfc0_status();
1882
rn = "Status";
1883
break;
2105
gen_op_mfc0_status();
2106
rn = "Status";
2107
break;
1884
2108
case 1:
1885
gen_op_mfc0_intctl();
1886
rn = "IntCtl";
1887
break;
2109
check_mips_r2(env, ctx);
2110
gen_op_mfc0_intctl();
2111
rn = "IntCtl";
2112
break;
1888
2113
case 2:
1889
gen_op_mfc0_srsctl();
1890
rn = "SRSCtl";
1891
break;
2114
check_mips_r2(env, ctx);
2115
gen_op_mfc0_srsctl();
2116
rn = "SRSCtl";
2117
break;
1892
2118
case 3:
1893
// gen_op_mfc0_srsmap(); /* shadow registers */
1894
rn = "SRSMap";
1895
// break;
2119
check_mips_r2(env, ctx);
2120
gen_op_mfc0_srsmap();
2121
rn = "SRSMap";
2122
break;
1896
2123
default:
1897
2124
goto die;
1898
2125
}
1900
2127
case 13:
1901
2128
switch (sel) {
1902
2129
case 0:
1903
gen_op_mfc0_cause();
1904
rn = "Cause";
1905
break;
2130
gen_op_mfc0_cause();
2131
rn = "Cause";
2132
break;
1906
2133
default:
1907
2134
goto die;
1908
2135
}
1910
2137
case 14:
1911
2138
switch (sel) {
1912
2139
case 0:
1913
gen_op_mfc0_epc();
1914
rn = "EPC";
1915
break;
2140
gen_op_mfc0_epc();
2141
rn = "EPC";
2142
break;
1916
2143
default:
1917
2144
goto die;
1918
}
2145
}
1919
2146
break;
1920
2147
case 15:
1921
2148
switch (sel) {
1922
2149
case 0:
1923
gen_op_mfc0_prid();
1924
rn = "PRid";
1925
break;
2150
gen_op_mfc0_prid();
2151
rn = "PRid";
2152
break;
1926
2153
case 1:
1927
gen_op_mfc0_ebase();
1928
rn = "EBase";
1929
break;
2154
check_mips_r2(env, ctx);
2155
gen_op_mfc0_ebase();
2156
rn = "EBase";
2157
break;
1930
2158
default:
1931
2159
goto die;
1932
2160
}
1934
2162
case 16:
1935
2163
switch (sel) {
1936
2164
case 0:
1937
gen_op_mfc0_config0();
2165
gen_op_mfc0_config0();
1938
2166
rn = "Config";
1939
2167
break;
1940
2168
case 1:
1941
gen_op_mfc0_config1();
2169
gen_op_mfc0_config1();
1942
2170
rn = "Config1";
1943
2171
break;
1944
2172
case 2:
1945
gen_op_mfc0_config2();
2173
gen_op_mfc0_config2();
1946
2174
rn = "Config2";
1947
2175
break;
1948
2176
case 3:
1949
gen_op_mfc0_config3();
2177
gen_op_mfc0_config3();
1950
2178
rn = "Config3";
1951
2179
break;
1952
/* 6,7 are implementation dependent */
2180
/* 4,5 are reserved */
2181
/* 6,7 are implementation dependent */
2182
case 6:
2183
gen_op_mfc0_config6();
2184
rn = "Config6";
2185
break;
2186
case 7:
2187
gen_op_mfc0_config7();
2188
rn = "Config7";
2189
break;
1953
2190
default:
1954
2191
goto die;
1955
2192
}
1957
2194
case 17:
1958
2195
switch (sel) {
1959
2196
case 0:
1960
gen_op_mfc0_lladdr();
1961
rn = "LLAddr";
1962
break;
2197
gen_op_mfc0_lladdr();
2198
rn = "LLAddr";
2199
break;
1963
2200
default:
1964
2201
goto die;
1965
2202
}
1966
2203
break;
1967
2204
case 18:
1968
2205
switch (sel) {
1969
case 0:
1970
gen_op_mfc0_watchlo0();
1971
rn = "WatchLo";
1972
break;
1973
case 1:
1974
// gen_op_mfc0_watchlo1();
1975
rn = "WatchLo1";
1976
// break;
1977
case 2:
1978
// gen_op_mfc0_watchlo2();
1979
rn = "WatchLo2";
1980
// break;
1981
case 3:
1982
// gen_op_mfc0_watchlo3();
1983
rn = "WatchLo3";
1984
// break;
1985
case 4:
1986
// gen_op_mfc0_watchlo4();
1987
rn = "WatchLo4";
1988
// break;
1989
case 5:
1990
// gen_op_mfc0_watchlo5();
1991
rn = "WatchLo5";
1992
// break;
1993
case 6:
1994
// gen_op_mfc0_watchlo6();
1995
rn = "WatchLo6";
1996
// break;
1997
case 7:
1998
// gen_op_mfc0_watchlo7();
1999
rn = "WatchLo7";
2000
// break;
2206
case 0 ... 7:
2207
gen_op_mfc0_watchlo(sel);
2208
rn = "WatchLo";
2209
break;
2001
2210
default:
2002
2211
goto die;
2003
2212
}
2004
2213
break;
2005
2214
case 19:
2006
2215
switch (sel) {
2007
case 0:
2008
gen_op_mfc0_watchhi0();
2009
rn = "WatchHi";
2010
break;
2011
case 1:
2012
// gen_op_mfc0_watchhi1();
2013
rn = "WatchHi1";
2014
// break;
2015
case 2:
2016
// gen_op_mfc0_watchhi2();
2017
rn = "WatchHi2";
2018
// break;
2019
case 3:
2020
// gen_op_mfc0_watchhi3();
2021
rn = "WatchHi3";
2022
// break;
2023
case 4:
2024
// gen_op_mfc0_watchhi4();
2025
rn = "WatchHi4";
2026
// break;
2027
case 5:
2028
// gen_op_mfc0_watchhi5();
2029
rn = "WatchHi5";
2030
// break;
2031
case 6:
2032
// gen_op_mfc0_watchhi6();
2033
rn = "WatchHi6";
2034
// break;
2035
case 7:
2036
// gen_op_mfc0_watchhi7();
2037
rn = "WatchHi7";
2038
// break;
2216
case 0 ...7:
2217
gen_op_mfc0_watchhi(sel);
2218
rn = "WatchHi";
2219
break;
2039
2220
default:
2040
2221
goto die;
2041
2222
}
2043
2224
case 20:
2044
2225
switch (sel) {
2045
2226
case 0:
2046
/* 64 bit MMU only */
2047
gen_op_mfc0_xcontext();
2048
rn = "XContext";
2049
break;
2227
#ifdef TARGET_MIPS64
2228
gen_op_mfc0_xcontext();
2229
rn = "XContext";
2230
break;
2231
#endif
2050
2232
default:
2051
2233
goto die;
2052
2234
}
2055
2237
/* Officially reserved, but sel 0 is used for R1x000 framemask */
2056
2238
switch (sel) {
2057
2239
case 0:
2058
gen_op_mfc0_framemask();
2059
rn = "Framemask";
2060
break;
2240
gen_op_mfc0_framemask();
2241
rn = "Framemask";
2242
break;
2061
2243
default:
2062
2244
goto die;
2063
2245
}
2064
2246
break;
2065
2247
case 22:
2066
/* ignored */
2067
rn = "'Diagnostic"; /* implementation dependent */
2068
break;
2248
/* ignored */
2249
rn = "'Diagnostic"; /* implementation dependent */
2250
break;
2069
2251
case 23:
2070
2252
switch (sel) {
2071
2253
case 0:
2072
gen_op_mfc0_debug(); /* EJTAG support */
2073
rn = "Debug";
2074
break;
2254
gen_op_mfc0_debug(); /* EJTAG support */
2255
rn = "Debug";
2256
break;
2075
2257
case 1:
2076
// gen_op_mfc0_tracecontrol(); /* PDtrace support */
2077
rn = "TraceControl";
2078
// break;
2258
// gen_op_mfc0_tracecontrol(); /* PDtrace support */
2259
rn = "TraceControl";
2260
// break;
2079
2261
case 2:
2080
// gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2081
rn = "TraceControl2";
2082
// break;
2262
// gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2263
rn = "TraceControl2";
2264
// break;
2083
2265
case 3:
2084
// gen_op_mfc0_usertracedata(); /* PDtrace support */
2085
rn = "UserTraceData";
2086
// break;
2266
// gen_op_mfc0_usertracedata(); /* PDtrace support */
2267
rn = "UserTraceData";
2268
// break;
2087
2269
case 4:
2088
// gen_op_mfc0_debug(); /* PDtrace support */
2089
rn = "TraceBPC";
2090
// break;
2270
// gen_op_mfc0_debug(); /* PDtrace support */
2271
rn = "TraceBPC";
2272
// break;
2091
2273
default:
2092
2274
goto die;
2093
2275
}
2095
2277
case 24:
2096
2278
switch (sel) {
2097
2279
case 0:
2098
gen_op_mfc0_depc(); /* EJTAG support */
2099
rn = "DEPC";
2100
break;
2280
gen_op_mfc0_depc(); /* EJTAG support */
2281
rn = "DEPC";
2282
break;
2101
2283
default:
2102
2284
goto die;
2103
2285
}
2105
2287
case 25:
2106
2288
switch (sel) {
2107
2289
case 0:
2108
gen_op_mfc0_performance0();
2109
rn = "Performance0";
2290
gen_op_mfc0_performance0();
2291
rn = "Performance0";
2110
2292
break;
2111
2293
case 1:
2112
// gen_op_mfc0_performance1();
2113
rn = "Performance1";
2114
// break;
2294
// gen_op_mfc0_performance1();
2295
rn = "Performance1";
2296
// break;
2115
2297
case 2:
2116
// gen_op_mfc0_performance2();
2117
rn = "Performance2";
2118
// break;
2298
// gen_op_mfc0_performance2();
2299
rn = "Performance2";
2300
// break;
2119
2301
case 3:
2120
// gen_op_mfc0_performance3();
2121
rn = "Performance3";
2122
// break;
2302
// gen_op_mfc0_performance3();
2303
rn = "Performance3";
2304
// break;
2123
2305
case 4:
2124
// gen_op_mfc0_performance4();
2125
rn = "Performance4";
2126
// break;
2306
// gen_op_mfc0_performance4();
2307
rn = "Performance4";
2308
// break;
2127
2309
case 5:
2128
// gen_op_mfc0_performance5();
2129
rn = "Performance5";
2130
// break;
2310
// gen_op_mfc0_performance5();
2311
rn = "Performance5";
2312
// break;
2131
2313
case 6:
2132
// gen_op_mfc0_performance6();
2133
rn = "Performance6";
2134
// break;
2314
// gen_op_mfc0_performance6();
2315
rn = "Performance6";
2316
// break;
2135
2317
case 7:
2136
// gen_op_mfc0_performance7();
2137
rn = "Performance7";
2138
// break;
2318
// gen_op_mfc0_performance7();
2319
rn = "Performance7";
2320
// break;
2139
2321
default:
2140
2322
goto die;
2141
2323
}
2147
2329
switch (sel) {
2148
2330
/* ignored */
2149
2331
case 0 ... 3:
2150
rn = "CacheErr";
2151
break;
2332
rn = "CacheErr";
2333
break;
2152
2334
default:
2153
2335
goto die;
2154
2336
}
2196
2378
case 30:
2197
2379
switch (sel) {
2198
2380
case 0:
2199
gen_op_mfc0_errorepc();
2200
rn = "ErrorEPC";
2201
break;
2381
gen_op_mfc0_errorepc();
2382
rn = "ErrorEPC";
2383
break;
2202
2384
default:
2203
2385
goto die;
2204
2386
}
2206
2388
case 31:
2207
2389
switch (sel) {
2208
2390
case 0:
2209
gen_op_mfc0_desave(); /* EJTAG support */
2210
rn = "DESAVE";
2211
break;
2391
gen_op_mfc0_desave(); /* EJTAG support */
2392
rn = "DESAVE";
2393
break;
2212
2394
default:
2213
2395
goto die;
2214
2396
}
2234
2416
generate_exception(ctx, EXCP_RI);
2235
2417
}
2236
2418
2237
static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
2419
static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2238
2420
{
2239
2421
const char *rn = "invalid";
2240
2422
2246
2428
rn = "Index";
2247
2429
break;
2248
2430
case 1:
2249
// gen_op_mtc0_mvpcontrol(); /* MT ASE */
2431
// gen_op_mtc0_mvpcontrol(); /* MT ASE */
2250
2432
rn = "MVPControl";
2251
// break;
2433
// break;
2252
2434
case 2:
2253
// gen_op_mtc0_mvpconf0(); /* MT ASE */
2435
// gen_op_mtc0_mvpconf0(); /* MT ASE */
2254
2436
rn = "MVPConf0";
2255
// break;
2437
// break;
2256
2438
case 3:
2257
// gen_op_mtc0_mvpconf1(); /* MT ASE */
2439
// gen_op_mtc0_mvpconf1(); /* MT ASE */
2258
2440
rn = "MVPConf1";
2259
// break;
2441
// break;
2260
2442
default:
2261
2443
goto die;
2262
2444
}
2264
2446
case 1:
2265
2447
switch (sel) {
2266
2448
case 0:
2267
/* ignored */
2449
/* ignored */
2268
2450
rn = "Random";
2269
break;
2451
break;
2270
2452
case 1:
2271
// gen_op_mtc0_vpecontrol(); /* MT ASE */
2453
// gen_op_mtc0_vpecontrol(); /* MT ASE */
2272
2454
rn = "VPEControl";
2273
// break;
2455
// break;
2274
2456
case 2:
2275
// gen_op_mtc0_vpeconf0(); /* MT ASE */
2457
// gen_op_mtc0_vpeconf0(); /* MT ASE */
2276
2458
rn = "VPEConf0";
2277
// break;
2459
// break;
2278
2460
case 3:
2279
// gen_op_mtc0_vpeconf1(); /* MT ASE */
2461
// gen_op_mtc0_vpeconf1(); /* MT ASE */
2280
2462
rn = "VPEConf1";
2281
// break;
2463
// break;
2282
2464
case 4:
2283
// gen_op_mtc0_YQMask(); /* MT ASE */
2465
// gen_op_mtc0_YQMask(); /* MT ASE */
2284
2466
rn = "YQMask";
2285
// break;
2467
// break;
2286
2468
case 5:
2287
// gen_op_mtc0_vpeschedule(); /* MT ASE */
2469
// gen_op_mtc0_vpeschedule(); /* MT ASE */
2288
2470
rn = "VPESchedule";
2289
// break;
2471
// break;
2290
2472
case 6:
2291
// gen_op_mtc0_vpeschefback(); /* MT ASE */
2473
// gen_op_mtc0_vpeschefback(); /* MT ASE */
2292
2474
rn = "VPEScheFBack";
2293
// break;
2475
// break;
2294
2476
case 7:
2295
// gen_op_mtc0_vpeopt(); /* MT ASE */
2477
// gen_op_mtc0_vpeopt(); /* MT ASE */
2296
2478
rn = "VPEOpt";
2297
// break;
2479
// break;
2298
2480
default:
2299
2481
goto die;
2300
2482
}
2302
2484
case 2:
2303
2485
switch (sel) {
2304
2486
case 0:
2305
gen_op_mtc0_entrylo0();
2306
rn = "EntryLo0";
2307
break;
2487
gen_op_mtc0_entrylo0();
2488
rn = "EntryLo0";
2489
break;
2308
2490
case 1:
2309
// gen_op_mtc0_tcstatus(); /* MT ASE */
2310
rn = "TCStatus";
2311
// break;
2491
// gen_op_mtc0_tcstatus(); /* MT ASE */
2492
rn = "TCStatus";
2493
// break;
2312
2494
case 2:
2313
// gen_op_mtc0_tcbind(); /* MT ASE */
2314
rn = "TCBind";
2315
// break;
2495
// gen_op_mtc0_tcbind(); /* MT ASE */
2496
rn = "TCBind";
2497
// break;
2316
2498
case 3:
2317
// gen_op_mtc0_tcrestart(); /* MT ASE */
2318
rn = "TCRestart";
2319
// break;
2499
// gen_op_mtc0_tcrestart(); /* MT ASE */
2500
rn = "TCRestart";
2501
// break;
2320
2502
case 4:
2321
// gen_op_mtc0_tchalt(); /* MT ASE */
2322
rn = "TCHalt";
2323
// break;
2503
// gen_op_mtc0_tchalt(); /* MT ASE */
2504
rn = "TCHalt";
2505
// break;
2324
2506
case 5:
2325
// gen_op_mtc0_tccontext(); /* MT ASE */
2326
rn = "TCContext";
2327
// break;
2507
// gen_op_mtc0_tccontext(); /* MT ASE */
2508
rn = "TCContext";
2509
// break;
2328
2510
case 6:
2329
// gen_op_mtc0_tcschedule(); /* MT ASE */
2330
rn = "TCSchedule";
2331
// break;
2511
// gen_op_mtc0_tcschedule(); /* MT ASE */
2512
rn = "TCSchedule";
2513
// break;
2332
2514
case 7:
2333
// gen_op_mtc0_tcschefback(); /* MT ASE */
2334
rn = "TCScheFBack";
2335
// break;
2515
// gen_op_mtc0_tcschefback(); /* MT ASE */
2516
rn = "TCScheFBack";
2517
// break;
2336
2518
default:
2337
2519
goto die;
2338
2520
}
2340
2522
case 3:
2341
2523
switch (sel) {
2342
2524
case 0:
2343
gen_op_mtc0_entrylo1();
2344
rn = "EntryLo1";
2345
break;
2525
gen_op_mtc0_entrylo1();
2526
rn = "EntryLo1";
2527
break;
2346
2528
default:
2347
2529
goto die;
2348
}
2530
}
2349
2531
break;
2350
2532
case 4:
2351
2533
switch (sel) {
2352
2534
case 0:
2353
gen_op_mtc0_context();
2354
rn = "Context";
2355
break;
2535
gen_op_mtc0_context();
2536
rn = "Context";
2537
break;
2356
2538
case 1:
2357
// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2358
rn = "ContextConfig";
2359
// break;
2539
// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2540
rn = "ContextConfig";
2541
// break;
2360
2542
default:
2361
2543
goto die;
2362
}
2544
}
2363
2545
break;
2364
2546
case 5:
2365
2547
switch (sel) {
2366
2548
case 0:
2367
gen_op_mtc0_pagemask();
2368
rn = "PageMask";
2369
break;
2549
gen_op_mtc0_pagemask();
2550
rn = "PageMask";
2551
break;
2370
2552
case 1:
2371
gen_op_mtc0_pagegrain();
2372
rn = "PageGrain";
2373
break;
2553
check_mips_r2(env, ctx);
2554
gen_op_mtc0_pagegrain();
2555
rn = "PageGrain";
2556
break;
2374
2557
default:
2375
2558
goto die;
2376
}
2559
}
2377
2560
break;
2378
2561
case 6:
2379
2562
switch (sel) {
2380
2563
case 0:
2381
gen_op_mtc0_wired();
2382
rn = "Wired";
2383
break;
2564
gen_op_mtc0_wired();
2565
rn = "Wired";
2566
break;
2384
2567
case 1:
2385
// gen_op_mtc0_srsconf0(); /* shadow registers */
2386
rn = "SRSConf0";
2387
// break;
2568
// gen_op_mtc0_srsconf0(); /* shadow registers */
2569
rn = "SRSConf0";
2570
// break;
2388
2571
case 2:
2389
// gen_op_mtc0_srsconf1(); /* shadow registers */
2390
rn = "SRSConf1";
2391
// break;
2572
// gen_op_mtc0_srsconf1(); /* shadow registers */
2573
rn = "SRSConf1";
2574
// break;
2392
2575
case 3:
2393
// gen_op_mtc0_srsconf2(); /* shadow registers */
2394
rn = "SRSConf2";
2395
// break;
2576
// gen_op_mtc0_srsconf2(); /* shadow registers */
2577
rn = "SRSConf2";
2578
// break;
2396
2579
case 4:
2397
// gen_op_mtc0_srsconf3(); /* shadow registers */
2398
rn = "SRSConf3";
2399
// break;
2580
// gen_op_mtc0_srsconf3(); /* shadow registers */
2581
rn = "SRSConf3";
2582
// break;
2400
2583
case 5:
2401
// gen_op_mtc0_srsconf4(); /* shadow registers */
2402
rn = "SRSConf4";
2403
// break;
2584
// gen_op_mtc0_srsconf4(); /* shadow registers */
2585
rn = "SRSConf4";
2586
// break;
2404
2587
default:
2405
2588
goto die;
2406
}
2589
}
2407
2590
break;
2408
2591
case 7:
2409
2592
switch (sel) {
2410
2593
case 0:
2411
gen_op_mtc0_hwrena();
2412
rn = "HWREna";
2413
break;
2594
check_mips_r2(env, ctx);
2595
gen_op_mtc0_hwrena();
2596
rn = "HWREna";
2597
break;
2414
2598
default:
2415
2599
goto die;
2416
}
2600
}
2417
2601
break;
2418
2602
case 8:
2419
2603
/* ignored */
2422
2606
case 9:
2423
2607
switch (sel) {
2424
2608
case 0:
2425
gen_op_mtc0_count();
2426
rn = "Count";
2427
break;
2428
/* 6,7 are implementation dependent */
2609
gen_op_mtc0_count();
2610
rn = "Count";
2611
break;
2612
/* 6,7 are implementation dependent */
2429
2613
default:
2430
2614
goto die;
2431
}
2432
/* Stop translation as we may have switched the execution mode */
2433
ctx->bstate = BS_STOP;
2615
}
2616
/* Stop translation as we may have switched the execution mode */
2617
ctx->bstate = BS_STOP;
2434
2618
break;
2435
2619
case 10:
2436
2620
switch (sel) {
2437
2621
case 0:
2438
gen_op_mtc0_entryhi();
2439
rn = "EntryHi";
2440
break;
2622
gen_op_mtc0_entryhi();
2623
rn = "EntryHi";
2624
break;
2441
2625
default:
2442
2626
goto die;
2443
}
2627
}
2444
2628
break;
2445
2629
case 11:
2446
2630
switch (sel) {
2447
2631
case 0:
2448
gen_op_mtc0_compare();
2449
rn = "Compare";
2450
break;
2451
/* 6,7 are implementation dependent */
2632
gen_op_mtc0_compare();
2633
rn = "Compare";
2634
break;
2635
/* 6,7 are implementation dependent */
2452
2636
default:
2453
2637
goto die;
2454
}
2455
/* Stop translation as we may have switched the execution mode */
2456
ctx->bstate = BS_STOP;
2638
}
2639
/* Stop translation as we may have switched the execution mode */
2640
ctx->bstate = BS_STOP;
2457
2641
break;
2458
2642
case 12:
2459
2643
switch (sel) {
2460
2644
case 0:
2461
gen_op_mtc0_status();
2462
rn = "Status";
2463
break;
2645
gen_op_mtc0_status();
2646
/* BS_STOP isn't good enough here, hflags may have changed. */
2647
gen_save_pc(ctx->pc + 4);
2648
ctx->bstate = BS_EXCP;
2649
rn = "Status";
2650
break;
2464
2651
case 1:
2465
gen_op_mtc0_intctl();
2466
rn = "IntCtl";
2467
break;
2652
check_mips_r2(env, ctx);
2653
gen_op_mtc0_intctl();
2654
/* Stop translation as we may have switched the execution mode */
2655
ctx->bstate = BS_STOP;
2656
rn = "IntCtl";
2657
break;
2468
2658
case 2:
2469
gen_op_mtc0_srsctl();
2470
rn = "SRSCtl";
2471
break;
2659
check_mips_r2(env, ctx);
2660
gen_op_mtc0_srsctl();
2661
/* Stop translation as we may have switched the execution mode */
2662
ctx->bstate = BS_STOP;
2663
rn = "SRSCtl";
2664
break;
2472
2665
case 3:
2473
// gen_op_mtc0_srsmap(); /* shadow registers */
2474
rn = "SRSMap";
2475
// break;
2666
check_mips_r2(env, ctx);
2667
gen_op_mtc0_srsmap();
2668
/* Stop translation as we may have switched the execution mode */
2669
ctx->bstate = BS_STOP;
2670
rn = "SRSMap";
2671
break;
2476
2672
default:
2477
2673
goto die;
2478
}
2479
/* Stop translation as we may have switched the execution mode */
2480
ctx->bstate = BS_STOP;
2674
}
2481
2675
break;
2482
2676
case 13:
2483
2677
switch (sel) {
2484
2678
case 0:
2485
gen_op_mtc0_cause();
2486
rn = "Cause";
2487
break;
2679
gen_op_mtc0_cause();
2680
rn = "Cause";
2681
break;
2488
2682
default:
2489
2683
goto die;
2490
}
2491
/* Stop translation as we may have switched the execution mode */
2492
ctx->bstate = BS_STOP;
2684
}
2685
/* Stop translation as we may have switched the execution mode */
2686
ctx->bstate = BS_STOP;
2493
2687
break;
2494
2688
case 14:
2495
2689
switch (sel) {
2496
2690
case 0:
2497
gen_op_mtc0_epc();
2498
rn = "EPC";
2499
break;
2691
gen_op_mtc0_epc();
2692
rn = "EPC";
2693
break;
2500
2694
default:
2501
2695
goto die;
2502
}
2696
}
2503
2697
break;
2504
2698
case 15:
2505
2699
switch (sel) {
2506
2700
case 0:
2507
/* ignored */
2508
rn = "PRid";
2509
break;
2701
/* ignored */
2702
rn = "PRid";
2703
break;
2510
2704
case 1:
2511
gen_op_mtc0_ebase();
2512
rn = "EBase";
2513
break;
2705
check_mips_r2(env, ctx);
2706
gen_op_mtc0_ebase();
2707
rn = "EBase";
2708
break;
2514
2709
default:
2515
2710
goto die;
2516
}
2711
}
2517
2712
break;
2518
2713
case 16:
2519
2714
switch (sel) {
2520
2715
case 0:
2521
gen_op_mtc0_config0();
2716
gen_op_mtc0_config0();
2522
2717
rn = "Config";
2718
/* Stop translation as we may have switched the execution mode */
2719
ctx->bstate = BS_STOP;
2523
2720
break;
2524
2721
case 1:
2525
/* ignored */
2722
/* ignored, read only */
2526
2723
rn = "Config1";
2527
2724
break;
2528
2725
case 2:
2529
gen_op_mtc0_config2();
2726
gen_op_mtc0_config2();
2530
2727
rn = "Config2";
2728
/* Stop translation as we may have switched the execution mode */
2729
ctx->bstate = BS_STOP;
2531
2730
break;
2532
2731
case 3:
2533
/* ignored */
2732
/* ignored, read only */
2534
2733
rn = "Config3";
2535
2734
break;
2536
/* 6,7 are implementation dependent */
2735
/* 4,5 are reserved */
2736
/* 6,7 are implementation dependent */
2737
case 6:
2738
/* ignored */
2739
rn = "Config6";
2740
break;
2741
case 7:
2742
/* ignored */
2743
rn = "Config7";
2744
break;
2537
2745
default:
2538
2746
rn = "Invalid config selector";
2539
2747
goto die;
2540
2748
}
2541
/* Stop translation as we may have switched the execution mode */
2542
ctx->bstate = BS_STOP;
2543
2749
break;
2544
2750
case 17:
2545
2751
switch (sel) {
2546
2752
case 0:
2547
/* ignored */
2548
rn = "LLAddr";
2549
break;
2753
/* ignored */
2754
rn = "LLAddr";
2755
break;
2550
2756
default:
2551
2757
goto die;
2552
2758
}
2553
2759
break;
2554
2760
case 18:
2555
2761
switch (sel) {
2556
case 0:
2557
gen_op_mtc0_watchlo0();
2558
rn = "WatchLo";
2559
break;
2560
case 1:
2561
// gen_op_mtc0_watchlo1();
2562
rn = "WatchLo1";
2563
// break;
2564
case 2:
2565
// gen_op_mtc0_watchlo2();
2566
rn = "WatchLo2";
2567
// break;
2568
case 3:
2569
// gen_op_mtc0_watchlo3();
2570
rn = "WatchLo3";
2571
// break;
2572
case 4:
2573
// gen_op_mtc0_watchlo4();
2574
rn = "WatchLo4";
2575
// break;
2576
case 5:
2577
// gen_op_mtc0_watchlo5();
2578
rn = "WatchLo5";
2579
// break;
2580
case 6:
2581
// gen_op_mtc0_watchlo6();
2582
rn = "WatchLo6";
2583
// break;
2584
case 7:
2585
// gen_op_mtc0_watchlo7();
2586
rn = "WatchLo7";
2587
// break;
2762
case 0 ... 7:
2763
gen_op_mtc0_watchlo(sel);
2764
rn = "WatchLo";
2765
break;
2588
2766
default:
2589
2767
goto die;
2590
2768
}
2591
2769
break;
2592
2770
case 19:
2593
2771
switch (sel) {
2594
case 0:
2595
gen_op_mtc0_watchhi0();
2596
rn = "WatchHi";
2597
break;
2598
case 1:
2599
// gen_op_mtc0_watchhi1();
2600
rn = "WatchHi1";
2601
// break;
2602
case 2:
2603
// gen_op_mtc0_watchhi2();
2604
rn = "WatchHi2";
2605
// break;
2606
case 3:
2607
// gen_op_mtc0_watchhi3();
2608
rn = "WatchHi3";
2609
// break;
2610
case 4:
2611
// gen_op_mtc0_watchhi4();
2612
rn = "WatchHi4";
2613
// break;
2614
case 5:
2615
// gen_op_mtc0_watchhi5();
2616
rn = "WatchHi5";
2617
// break;
2618
case 6:
2619
// gen_op_mtc0_watchhi6();
2620
rn = "WatchHi6";
2621
// break;
2622
case 7:
2623
// gen_op_mtc0_watchhi7();
2624
rn = "WatchHi7";
2625
// break;
2772
case 0 ... 7:
2773
gen_op_mtc0_watchhi(sel);
2774
rn = "WatchHi";
2775
break;
2626
2776
default:
2627
2777
goto die;
2628
2778
}
2630
2780
case 20:
2631
2781
switch (sel) {
2632
2782
case 0:
2633
/* 64 bit MMU only */
2634
gen_op_mtc0_xcontext();
2635
rn = "XContext";
2636
break;
2783
#ifdef TARGET_MIPS64
2784
gen_op_mtc0_xcontext();
2785
rn = "XContext";
2786
break;
2787
#endif
2637
2788
default:
2638
2789
goto die;
2639
2790
}
2642
2793
/* Officially reserved, but sel 0 is used for R1x000 framemask */
2643
2794
switch (sel) {
2644
2795
case 0:
2645
gen_op_mtc0_framemask();
2646
rn = "Framemask";
2647
break;
2796
gen_op_mtc0_framemask();
2797
rn = "Framemask";
2798
break;
2648
2799
default:
2649
2800
goto die;
2650
2801
}
2652
2803
case 22:
2653
2804
/* ignored */
2654
2805
rn = "Diagnostic"; /* implementation dependent */
2655
break;
2806
break;
2656
2807
case 23:
2657
2808
switch (sel) {
2658
2809
case 0:
2659
gen_op_mtc0_debug(); /* EJTAG support */
2660
rn = "Debug";
2661
break;
2810
gen_op_mtc0_debug(); /* EJTAG support */
2811
/* BS_STOP isn't good enough here, hflags may have changed. */
2812
gen_save_pc(ctx->pc + 4);
2813
ctx->bstate = BS_EXCP;
2814
rn = "Debug";
2815
break;
2662
2816
case 1:
2663
// gen_op_mtc0_tracecontrol(); /* PDtrace support */
2664
rn = "TraceControl";
2665
// break;
2817
// gen_op_mtc0_tracecontrol(); /* PDtrace support */
2818
rn = "TraceControl";
2819
/* Stop translation as we may have switched the execution mode */
2820
ctx->bstate = BS_STOP;
2821
// break;
2666
2822
case 2:
2667
// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2668
rn = "TraceControl2";
2669
// break;
2823
// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2824
rn = "TraceControl2";
2825
/* Stop translation as we may have switched the execution mode */
2826
ctx->bstate = BS_STOP;
2827
// break;
2670
2828
case 3:
2671
// gen_op_mtc0_usertracedata(); /* PDtrace support */
2672
rn = "UserTraceData";
2673
// break;
2829
/* Stop translation as we may have switched the execution mode */
2830
ctx->bstate = BS_STOP;
2831
// gen_op_mtc0_usertracedata(); /* PDtrace support */
2832
rn = "UserTraceData";
2833
/* Stop translation as we may have switched the execution mode */
2834
ctx->bstate = BS_STOP;
2835
// break;
2674
2836
case 4:
2675
// gen_op_mtc0_debug(); /* PDtrace support */
2676
rn = "TraceBPC";
2677
// break;
2837
// gen_op_mtc0_debug(); /* PDtrace support */
2838
/* Stop translation as we may have switched the execution mode */
2839
ctx->bstate = BS_STOP;
2840
rn = "TraceBPC";
2841
// break;
2678
2842
default:
2679
2843
goto die;
2680
2844
}
2681
/* Stop translation as we may have switched the execution mode */
2682
ctx->bstate = BS_STOP;
2683
2845
break;
2684
2846
case 24:
2685
2847
switch (sel) {
2686
2848
case 0:
2687
gen_op_mtc0_depc(); /* EJTAG support */
2688
rn = "DEPC";
2689
break;
2849
gen_op_mtc0_depc(); /* EJTAG support */
2850
rn = "DEPC";
2851
break;
2690
2852
default:
2691
2853
goto die;
2692
2854
}
2694
2856
case 25:
2695
2857
switch (sel) {
2696
2858
case 0:
2697
gen_op_mtc0_performance0();
2698
rn = "Performance0";
2699
break;
2859
gen_op_mtc0_performance0();
2860
rn = "Performance0";
2861
break;
2700
2862
case 1:
2701
// gen_op_mtc0_performance1();
2702
rn = "Performance1";
2703
// break;
2863
// gen_op_mtc0_performance1();
2864
rn = "Performance1";
2865
// break;
2704
2866
case 2:
2705
// gen_op_mtc0_performance2();
2706
rn = "Performance2";
2707
// break;
2867
// gen_op_mtc0_performance2();
2868
rn = "Performance2";
2869
// break;
2708
2870
case 3:
2709
// gen_op_mtc0_performance3();
2710
rn = "Performance3";
2711
// break;
2871
// gen_op_mtc0_performance3();
2872
rn = "Performance3";
2873
// break;
2712
2874
case 4:
2713
// gen_op_mtc0_performance4();
2714
rn = "Performance4";
2715
// break;
2875
// gen_op_mtc0_performance4();
2876
rn = "Performance4";
2877
// break;
2716
2878
case 5:
2717
// gen_op_mtc0_performance5();
2718
rn = "Performance5";
2719
// break;
2879
// gen_op_mtc0_performance5();
2880
rn = "Performance5";
2881
// break;
2720
2882
case 6:
2721
// gen_op_mtc0_performance6();
2722
rn = "Performance6";
2723
// break;
2883
// gen_op_mtc0_performance6();
2884
rn = "Performance6";
2885
// break;
2724
2886
case 7:
2725
// gen_op_mtc0_performance7();
2726
rn = "Performance7";
2727
// break;
2887
// gen_op_mtc0_performance7();
2888
rn = "Performance7";
2889
// break;
2728
2890
default:
2729
2891
goto die;
2730
2892
}
2731
2893
break;
2732
2894
case 26:
2733
/* ignored */
2895
/* ignored */
2734
2896
rn = "ECC";
2735
break;
2897
break;
2736
2898
case 27:
2737
2899
switch (sel) {
2738
2900
case 0 ... 3:
2739
/* ignored */
2740
rn = "CacheErr";
2741
break;
2901
/* ignored */
2902
rn = "CacheErr";
2903
break;
2742
2904
default:
2743
2905
goto die;
2744
2906
}
2756
2918
case 3:
2757
2919
case 5:
2758
2920
case 7:
2759
gen_op_mtc0_datalo();
2921
gen_op_mtc0_datalo();
2760
2922
rn = "DataLo";
2761
2923
break;
2762
2924
default:
2776
2938
case 3:
2777
2939
case 5:
2778
2940
case 7:
2779
gen_op_mtc0_datahi();
2941
gen_op_mtc0_datahi();
2780
2942
rn = "DataHi";
2781
2943
break;
2782
2944
default:
2787
2949
case 30:
2788
2950
switch (sel) {
2789
2951
case 0:
2790
gen_op_mtc0_errorepc();
2791
rn = "ErrorEPC";
2792
break;
2952
gen_op_mtc0_errorepc();
2953
rn = "ErrorEPC";
2954
break;
2793
2955
default:
2794
2956
goto die;
2795
2957
}
2797
2959
case 31:
2798
2960
switch (sel) {
2799
2961
case 0:
2800
gen_op_mtc0_desave(); /* EJTAG support */
2801
rn = "DESAVE";
2802
break;
2962
gen_op_mtc0_desave(); /* EJTAG support */
2963
rn = "DESAVE";
2964
break;
2803
2965
default:
2804
2966
goto die;
2805
2967
}
2806
/* Stop translation as we may have switched the execution mode */
2807
ctx->bstate = BS_STOP;
2968
/* Stop translation as we may have switched the execution mode */
2969
ctx->bstate = BS_STOP;
2808
2970
break;
2809
2971
default:
2810
2972
goto die;
2827
2989
generate_exception(ctx, EXCP_RI);
2828
2990
}
2829
2991
2830
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
2992
#ifdef TARGET_MIPS64
2993
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2831
2994
{
2832
2995
const char *rn = "invalid";
2833
2996
2835
2998
case 0:
2836
2999
switch (sel) {
2837
3000
case 0:
2838
gen_op_mfc0_index();
3001
gen_op_mfc0_index();
2839
3002
rn = "Index";
2840
3003
break;
2841
3004
case 1:
2842
// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
3005
// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
2843
3006
rn = "MVPControl";
2844
// break;
3007
// break;
2845
3008
case 2:
2846
// gen_op_dmfc0_mvpconf0(); /* MT ASE */
3009
// gen_op_dmfc0_mvpconf0(); /* MT ASE */
2847
3010
rn = "MVPConf0";
2848
// break;
3011
// break;
2849
3012
case 3:
2850
// gen_op_dmfc0_mvpconf1(); /* MT ASE */
3013
// gen_op_dmfc0_mvpconf1(); /* MT ASE */
2851
3014
rn = "MVPConf1";
2852
// break;
3015
// break;
2853
3016
default:
2854
3017
goto die;
2855
3018
}
2859
3022
case 0:
2860
3023
gen_op_mfc0_random();
2861
3024
rn = "Random";
2862
break;
3025
break;
2863
3026
case 1:
2864
// gen_op_dmfc0_vpecontrol(); /* MT ASE */
3027
// gen_op_dmfc0_vpecontrol(); /* MT ASE */
2865
3028
rn = "VPEControl";
2866
// break;
3029
// break;
2867
3030
case 2:
2868
// gen_op_dmfc0_vpeconf0(); /* MT ASE */
3031
// gen_op_dmfc0_vpeconf0(); /* MT ASE */
2869
3032
rn = "VPEConf0";
2870
// break;
3033
// break;
2871
3034
case 3:
2872
// gen_op_dmfc0_vpeconf1(); /* MT ASE */
3035
// gen_op_dmfc0_vpeconf1(); /* MT ASE */
2873
3036
rn = "VPEConf1";
2874
// break;
3037
// break;
2875
3038
case 4:
2876
// gen_op_dmfc0_YQMask(); /* MT ASE */
3039
// gen_op_dmfc0_YQMask(); /* MT ASE */
2877
3040
rn = "YQMask";
2878
// break;
3041
// break;
2879
3042
case 5:
2880
// gen_op_dmfc0_vpeschedule(); /* MT ASE */
3043
// gen_op_dmfc0_vpeschedule(); /* MT ASE */
2881
3044
rn = "VPESchedule";
2882
// break;
3045
// break;
2883
3046
case 6:
2884
// gen_op_dmfc0_vpeschefback(); /* MT ASE */
3047
// gen_op_dmfc0_vpeschefback(); /* MT ASE */
2885
3048
rn = "VPEScheFBack";
2886
// break;
3049
// break;
2887
3050
case 7:
2888
// gen_op_dmfc0_vpeopt(); /* MT ASE */
3051
// gen_op_dmfc0_vpeopt(); /* MT ASE */
2889
3052
rn = "VPEOpt";
2890
// break;
3053
// break;
2891
3054
default:
2892
3055
goto die;
2893
3056
}
2895
3058
case 2:
2896
3059
switch (sel) {
2897
3060
case 0:
2898
gen_op_dmfc0_entrylo0();
2899
rn = "EntryLo0";
2900
break;
3061
gen_op_dmfc0_entrylo0();
3062
rn = "EntryLo0";
3063
break;
2901
3064
case 1:
2902
// gen_op_dmfc0_tcstatus(); /* MT ASE */
2903
rn = "TCStatus";
2904
// break;
3065
// gen_op_dmfc0_tcstatus(); /* MT ASE */
3066
rn = "TCStatus";
3067
// break;
2905
3068
case 2:
2906
// gen_op_dmfc0_tcbind(); /* MT ASE */
2907
rn = "TCBind";
2908
// break;
3069
// gen_op_dmfc0_tcbind(); /* MT ASE */
3070
rn = "TCBind";
3071
// break;
2909
3072
case 3:
2910
// gen_op_dmfc0_tcrestart(); /* MT ASE */
2911
rn = "TCRestart";
2912
// break;
3073
// gen_op_dmfc0_tcrestart(); /* MT ASE */
3074
rn = "TCRestart";
3075
// break;
2913
3076
case 4:
2914
// gen_op_dmfc0_tchalt(); /* MT ASE */
2915
rn = "TCHalt";
2916
// break;
3077
// gen_op_dmfc0_tchalt(); /* MT ASE */
3078
rn = "TCHalt";
3079
// break;
2917
3080
case 5:
2918
// gen_op_dmfc0_tccontext(); /* MT ASE */
2919
rn = "TCContext";
2920
// break;
3081
// gen_op_dmfc0_tccontext(); /* MT ASE */
3082
rn = "TCContext";
3083
// break;
2921
3084
case 6:
2922
// gen_op_dmfc0_tcschedule(); /* MT ASE */
2923
rn = "TCSchedule";
2924
// break;
3085
// gen_op_dmfc0_tcschedule(); /* MT ASE */
3086
rn = "TCSchedule";
3087
// break;
2925
3088
case 7:
2926
// gen_op_dmfc0_tcschefback(); /* MT ASE */
2927
rn = "TCScheFBack";
2928
// break;
3089
// gen_op_dmfc0_tcschefback(); /* MT ASE */
3090
rn = "TCScheFBack";
3091
// break;
2929
3092
default:
2930
3093
goto die;
2931
3094
}
2933
3096
case 3:
2934
3097
switch (sel) {
2935
3098
case 0:
2936
gen_op_dmfc0_entrylo1();
2937
rn = "EntryLo1";
2938
break;
3099
gen_op_dmfc0_entrylo1();
3100
rn = "EntryLo1";
3101
break;
2939
3102
default:
2940
3103
goto die;
2941
}
3104
}
2942
3105
break;
2943
3106
case 4:
2944
3107
switch (sel) {
2945
3108
case 0:
2946
gen_op_dmfc0_context();
2947
rn = "Context";
2948
break;
3109
gen_op_dmfc0_context();
3110
rn = "Context";
3111
break;
2949
3112
case 1:
2950
// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
2951
rn = "ContextConfig";
2952
// break;
3113
// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3114
rn = "ContextConfig";
3115
// break;
2953
3116
default:
2954
3117
goto die;
2955
}
3118
}
2956
3119
break;
2957
3120
case 5:
2958
3121
switch (sel) {
2959
3122
case 0:
2960
gen_op_mfc0_pagemask();
2961
rn = "PageMask";
2962
break;
3123
gen_op_mfc0_pagemask();
3124
rn = "PageMask";
3125
break;
2963
3126
case 1:
2964
gen_op_mfc0_pagegrain();
2965
rn = "PageGrain";
2966
break;
3127
check_mips_r2(env, ctx);
3128
gen_op_mfc0_pagegrain();
3129
rn = "PageGrain";
3130
break;
2967
3131
default:
2968
3132
goto die;
2969
}
3133
}
2970
3134
break;
2971
3135
case 6:
2972
3136
switch (sel) {
2973
3137
case 0:
2974
gen_op_mfc0_wired();
2975
rn = "Wired";
2976
break;
3138
gen_op_mfc0_wired();
3139
rn = "Wired";
3140
break;
2977
3141
case 1:
2978
// gen_op_dmfc0_srsconf0(); /* shadow registers */
2979
rn = "SRSConf0";
2980
// break;
3142
// gen_op_dmfc0_srsconf0(); /* shadow registers */
3143
rn = "SRSConf0";
3144
// break;
2981
3145
case 2:
2982
// gen_op_dmfc0_srsconf1(); /* shadow registers */
2983
rn = "SRSConf1";
2984
// break;
3146
// gen_op_dmfc0_srsconf1(); /* shadow registers */
3147
rn = "SRSConf1";
3148
// break;
2985
3149
case 3:
2986
// gen_op_dmfc0_srsconf2(); /* shadow registers */
2987
rn = "SRSConf2";
2988
// break;
3150
// gen_op_dmfc0_srsconf2(); /* shadow registers */
3151
rn = "SRSConf2";
3152
// break;
2989
3153
case 4:
2990
// gen_op_dmfc0_srsconf3(); /* shadow registers */
2991
rn = "SRSConf3";
2992
// break;
3154
// gen_op_dmfc0_srsconf3(); /* shadow registers */
3155
rn = "SRSConf3";
3156
// break;
2993
3157
case 5:
2994
// gen_op_dmfc0_srsconf4(); /* shadow registers */
2995
rn = "SRSConf4";
2996
// break;
3158
// gen_op_dmfc0_srsconf4(); /* shadow registers */
3159
rn = "SRSConf4";
3160
// break;
2997
3161
default:
2998
3162
goto die;
2999
}
3163
}
3000
3164
break;
3001
3165
case 7:
3002
3166
switch (sel) {
3003
3167
case 0:
3004
gen_op_mfc0_hwrena();
3005
rn = "HWREna";
3006
break;
3168
check_mips_r2(env, ctx);
3169
gen_op_mfc0_hwrena();
3170
rn = "HWREna";
3171
break;
3007
3172
default:
3008
3173
goto die;
3009
}
3174
}
3010
3175
break;
3011
3176
case 8:
3012
3177
switch (sel) {
3013
3178
case 0:
3014
gen_op_dmfc0_badvaddr();
3015
rn = "BadVaddr";
3016
break;
3179
gen_op_dmfc0_badvaddr();
3180
rn = "BadVaddr";
3181
break;
3017
3182
default:
3018
3183
goto die;
3019
}
3184
}
3020
3185
break;
3021
3186
case 9:
3022
3187
switch (sel) {
3023
3188
case 0:
3024
gen_op_mfc0_count();
3025
rn = "Count";
3026
break;
3027
/* 6,7 are implementation dependent */
3189
gen_op_mfc0_count();
3190
rn = "Count";
3191
break;
3192
/* 6,7 are implementation dependent */
3028
3193
default:
3029
3194
goto die;
3030
}
3195
}
3031
3196
break;
3032
3197
case 10:
3033
3198
switch (sel) {
3034
3199
case 0:
3035
gen_op_dmfc0_entryhi();
3036
rn = "EntryHi";
3037
break;
3200
gen_op_dmfc0_entryhi();
3201
rn = "EntryHi";
3202
break;
3038
3203
default:
3039
3204
goto die;
3040
}
3205
}
3041
3206
break;
3042
3207
case 11:
3043
3208
switch (sel) {
3044
3209
case 0:
3045
gen_op_mfc0_compare();
3046
rn = "Compare";
3047
break;
3048
/* 6,7 are implementation dependent */
3210
gen_op_mfc0_compare();
3211
rn = "Compare";
3212
break;
3213
/* 6,7 are implementation dependent */
3049
3214
default:
3050
3215
goto die;
3051
}
3216
}
3052
3217
break;
3053
3218
case 12:
3054
3219
switch (sel) {
3055
3220
case 0:
3056
gen_op_mfc0_status();
3057
rn = "Status";
3058
break;
3221
gen_op_mfc0_status();
3222
rn = "Status";
3223
break;
3059
3224
case 1:
3060
gen_op_mfc0_intctl();
3061
rn = "IntCtl";
3062
break;
3225
check_mips_r2(env, ctx);
3226
gen_op_mfc0_intctl();
3227
rn = "IntCtl";
3228
break;
3063
3229
case 2:
3064
gen_op_mfc0_srsctl();
3065
rn = "SRSCtl";
3066
break;
3230
check_mips_r2(env, ctx);
3231
gen_op_mfc0_srsctl();
3232
rn = "SRSCtl";
3233
break;
3067
3234
case 3:
3068
gen_op_mfc0_srsmap(); /* shadow registers */
3069
rn = "SRSMap";
3070
break;
3235
check_mips_r2(env, ctx);
3236
gen_op_mfc0_srsmap(); /* shadow registers */
3237
rn = "SRSMap";
3238
break;
3071
3239
default:
3072
3240
goto die;
3073
}
3241
}
3074
3242
break;
3075
3243
case 13:
3076
3244
switch (sel) {
3077
3245
case 0:
3078
gen_op_mfc0_cause();
3079
rn = "Cause";
3080
break;
3246
gen_op_mfc0_cause();
3247
rn = "Cause";
3248
break;
3081
3249
default:
3082
3250
goto die;
3083
}
3251
}
3084
3252
break;
3085
3253
case 14:
3086
3254
switch (sel) {
3087
3255
case 0:
3088
gen_op_dmfc0_epc();
3089
rn = "EPC";
3090
break;
3256
gen_op_dmfc0_epc();
3257
rn = "EPC";
3258
break;
3091
3259
default:
3092
3260
goto die;
3093
}
3261
}
3094
3262
break;
3095
3263
case 15:
3096
3264
switch (sel) {
3097
3265
case 0:
3098
gen_op_mfc0_prid();
3099
rn = "PRid";
3100
break;
3266
gen_op_mfc0_prid();
3267
rn = "PRid";
3268
break;
3101
3269
case 1:
3102
gen_op_mfc0_ebase();
3103
rn = "EBase";
3104
break;
3270
check_mips_r2(env, ctx);
3271
gen_op_mfc0_ebase();
3272
rn = "EBase";
3273
break;
3105
3274
default:
3106
3275
goto die;
3107
}
3276
}
3108
3277
break;
3109
3278
case 16:
3110
3279
switch (sel) {
3111
3280
case 0:
3112
gen_op_mfc0_config0();
3281
gen_op_mfc0_config0();
3113
3282
rn = "Config";
3114
3283
break;
3115
3284
case 1:
3116
gen_op_mfc0_config1();
3285
gen_op_mfc0_config1();
3117
3286
rn = "Config1";
3118
3287
break;
3119
3288
case 2:
3120
gen_op_mfc0_config2();
3289
gen_op_mfc0_config2();
3121
3290
rn = "Config2";
3122
3291
break;
3123
3292
case 3:
3124
gen_op_mfc0_config3();
3293
gen_op_mfc0_config3();
3125
3294
rn = "Config3";
3126
3295
break;
3127
3296
/* 6,7 are implementation dependent */
3132
3301
case 17:
3133
3302
switch (sel) {
3134
3303
case 0:
3135
gen_op_dmfc0_lladdr();
3136
rn = "LLAddr";
3137
break;
3304
gen_op_dmfc0_lladdr();
3305
rn = "LLAddr";
3306
break;
3138
3307
default:
3139
3308
goto die;
3140
3309
}
3141
3310
break;
3142
3311
case 18:
3143
3312
switch (sel) {
3144
case 0:
3145
gen_op_dmfc0_watchlo0();
3146
rn = "WatchLo";
3147
break;
3148
case 1:
3149
// gen_op_dmfc0_watchlo1();
3150
rn = "WatchLo1";
3151
// break;
3152
case 2:
3153
// gen_op_dmfc0_watchlo2();
3154
rn = "WatchLo2";
3155
// break;
3156
case 3:
3157
// gen_op_dmfc0_watchlo3();
3158
rn = "WatchLo3";
3159
// break;
3160
case 4:
3161
// gen_op_dmfc0_watchlo4();
3162
rn = "WatchLo4";
3163
// break;
3164
case 5:
3165
// gen_op_dmfc0_watchlo5();
3166
rn = "WatchLo5";
3167
// break;
3168
case 6:
3169
// gen_op_dmfc0_watchlo6();
3170
rn = "WatchLo6";
3171
// break;
3172
case 7:
3173
// gen_op_dmfc0_watchlo7();
3174
rn = "WatchLo7";
3175
// break;
3313
case 0 ... 7:
3314
gen_op_dmfc0_watchlo(sel);
3315
rn = "WatchLo";
3316
break;
3176
3317
default:
3177
3318
goto die;
3178
3319
}
3179
3320
break;
3180
3321
case 19:
3181
3322
switch (sel) {
3182
case 0:
3183
gen_op_mfc0_watchhi0();
3184
rn = "WatchHi";
3185
break;
3186
case 1:
3187
// gen_op_mfc0_watchhi1();
3188
rn = "WatchHi1";
3189
// break;
3190
case 2:
3191
// gen_op_mfc0_watchhi2();
3192
rn = "WatchHi2";
3193
// break;
3194
case 3:
3195
// gen_op_mfc0_watchhi3();
3196
rn = "WatchHi3";
3197
// break;
3198
case 4:
3199
// gen_op_mfc0_watchhi4();
3200
rn = "WatchHi4";
3201
// break;
3202
case 5:
3203
// gen_op_mfc0_watchhi5();
3204
rn = "WatchHi5";
3205
// break;
3206
case 6:
3207
// gen_op_mfc0_watchhi6();
3208
rn = "WatchHi6";
3209
// break;
3210
case 7:
3211
// gen_op_mfc0_watchhi7();
3212
rn = "WatchHi7";
3213
// break;
3323
case 0 ... 7:
3324
gen_op_mfc0_watchhi(sel);
3325
rn = "WatchHi";
3326
break;
3214
3327
default:
3215
3328
goto die;
3216
3329
}
3218
3331
case 20:
3219
3332
switch (sel) {
3220
3333
case 0:
3221
/* 64 bit MMU only */
3222
gen_op_dmfc0_xcontext();
3223
rn = "XContext";
3224
break;
3334
#ifdef TARGET_MIPS64
3335
gen_op_dmfc0_xcontext();
3336
rn = "XContext";
3337
break;
3338
#endif
3225
3339
default:
3226
3340
goto die;
3227
3341
}
3230
3344
/* Officially reserved, but sel 0 is used for R1x000 framemask */
3231
3345
switch (sel) {
3232
3346
case 0:
3233
gen_op_mfc0_framemask();
3234
rn = "Framemask";
3235
break;
3347
gen_op_mfc0_framemask();
3348
rn = "Framemask";
3349
break;
3236
3350
default:
3237
3351
goto die;
3238
3352
}
3239
3353
break;
3240
3354
case 22:
3241
/* ignored */
3242
rn = "'Diagnostic"; /* implementation dependent */
3243
break;
3355
/* ignored */
3356
rn = "'Diagnostic"; /* implementation dependent */
3357
break;
3244
3358
case 23:
3245
3359
switch (sel) {
3246
3360
case 0:
3247
gen_op_mfc0_debug(); /* EJTAG support */
3248
rn = "Debug";
3249
break;
3361
gen_op_mfc0_debug(); /* EJTAG support */
3362
rn = "Debug";
3363
break;
3250
3364
case 1:
3251
// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3252
rn = "TraceControl";
3253
// break;
3365
// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3366
rn = "TraceControl";
3367
// break;
3254
3368
case 2:
3255
// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3256
rn = "TraceControl2";
3257
// break;
3369
// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3370
rn = "TraceControl2";
3371
// break;
3258
3372
case 3:
3259
// gen_op_dmfc0_usertracedata(); /* PDtrace support */
3260
rn = "UserTraceData";
3261
// break;
3373
// gen_op_dmfc0_usertracedata(); /* PDtrace support */
3374
rn = "UserTraceData";
3375
// break;
3262
3376
case 4:
3263
// gen_op_dmfc0_debug(); /* PDtrace support */
3264
rn = "TraceBPC";
3265
// break;
3377
// gen_op_dmfc0_debug(); /* PDtrace support */
3378
rn = "TraceBPC";
3379
// break;
3266
3380
default:
3267
3381
goto die;
3268
3382
}
3270
3384
case 24:
3271
3385
switch (sel) {
3272
3386
case 0:
3273
gen_op_dmfc0_depc(); /* EJTAG support */
3274
rn = "DEPC";
3275
break;
3387
gen_op_dmfc0_depc(); /* EJTAG support */
3388
rn = "DEPC";
3389
break;
3276
3390
default:
3277
3391
goto die;
3278
3392
}
3280
3394
case 25:
3281
3395
switch (sel) {
3282
3396
case 0:
3283
gen_op_mfc0_performance0();
3284
rn = "Performance0";
3397
gen_op_mfc0_performance0();
3398
rn = "Performance0";
3285
3399
break;
3286
3400
case 1:
3287
// gen_op_dmfc0_performance1();
3288
rn = "Performance1";
3289
// break;
3401
// gen_op_dmfc0_performance1();
3402
rn = "Performance1";
3403
// break;
3290
3404
case 2:
3291
// gen_op_dmfc0_performance2();
3292
rn = "Performance2";
3293
// break;
3405
// gen_op_dmfc0_performance2();
3406
rn = "Performance2";
3407
// break;
3294
3408
case 3:
3295
// gen_op_dmfc0_performance3();
3296
rn = "Performance3";
3297
// break;
3409
// gen_op_dmfc0_performance3();
3410
rn = "Performance3";
3411
// break;
3298
3412
case 4:
3299
// gen_op_dmfc0_performance4();
3300
rn = "Performance4";
3301
// break;
3413
// gen_op_dmfc0_performance4();
3414
rn = "Performance4";
3415
// break;
3302
3416
case 5:
3303
// gen_op_dmfc0_performance5();
3304
rn = "Performance5";
3305
// break;
3417
// gen_op_dmfc0_performance5();
3418
rn = "Performance5";
3419
// break;
3306
3420
case 6:
3307
// gen_op_dmfc0_performance6();
3308
rn = "Performance6";
3309
// break;
3421
// gen_op_dmfc0_performance6();
3422
rn = "Performance6";
3423
// break;
3310
3424
case 7:
3311
// gen_op_dmfc0_performance7();
3312
rn = "Performance7";
3313
// break;
3425
// gen_op_dmfc0_performance7();
3426
rn = "Performance7";
3427
// break;
3314
3428
default:
3315
3429
goto die;
3316
3430
}
3322
3436
switch (sel) {
3323
3437
/* ignored */
3324
3438
case 0 ... 3:
3325
rn = "CacheErr";
3326
break;
3439
rn = "CacheErr";
3440
break;
3327
3441
default:
3328
3442
goto die;
3329
3443
}
3371
3485
case 30:
3372
3486
switch (sel) {
3373
3487
case 0:
3374
gen_op_dmfc0_errorepc();
3375
rn = "ErrorEPC";
3376
break;
3488
gen_op_dmfc0_errorepc();
3489
rn = "ErrorEPC";
3490
break;
3377
3491
default:
3378
3492
goto die;
3379
3493
}
3381
3495
case 31:
3382
3496
switch (sel) {
3383
3497
case 0:
3384
gen_op_mfc0_desave(); /* EJTAG support */
3385
rn = "DESAVE";
3386
break;
3498
gen_op_mfc0_desave(); /* EJTAG support */
3499
rn = "DESAVE";
3500
break;
3387
3501
default:
3388
3502
goto die;
3389
3503
}
3390
3504
break;
3391
3505
default:
3392
goto die;
3506
goto die;
3393
3507
}
3394
3508
#if defined MIPS_DEBUG_DISAS
3395
3509
if (loglevel & CPU_LOG_TB_IN_ASM) {
3409
3523
generate_exception(ctx, EXCP_RI);
3410
3524
}
3411
3525
3412
static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3526
static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3413
3527
{
3414
3528
const char *rn = "invalid";
3415
3529
3421
3535
rn = "Index";
3422
3536
break;
3423
3537
case 1:
3424
// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
3538
// gen_op_mtc0_mvpcontrol(); /* MT ASE */
3425
3539
rn = "MVPControl";
3426
// break;
3540
// break;
3427
3541
case 2:
3428
// gen_op_dmtc0_mvpconf0(); /* MT ASE */
3542
// gen_op_mtc0_mvpconf0(); /* MT ASE */
3429
3543
rn = "MVPConf0";
3430
// break;
3544
// break;
3431
3545
case 3:
3432
// gen_op_dmtc0_mvpconf1(); /* MT ASE */
3546
// gen_op_mtc0_mvpconf1(); /* MT ASE */
3433
3547
rn = "MVPConf1";
3434
// break;
3548
// break;
3435
3549
default:
3436
3550
goto die;
3437
3551
}
3439
3553
case 1:
3440
3554
switch (sel) {
3441
3555
case 0:
3442
/* ignored */
3556
/* ignored */
3443
3557
rn = "Random";
3444
break;
3558
break;
3445
3559
case 1:
3446
// gen_op_dmtc0_vpecontrol(); /* MT ASE */
3560
// gen_op_mtc0_vpecontrol(); /* MT ASE */
3447
3561
rn = "VPEControl";
3448
// break;
3562
// break;
3449
3563
case 2:
3450
// gen_op_dmtc0_vpeconf0(); /* MT ASE */
3564
// gen_op_mtc0_vpeconf0(); /* MT ASE */
3451
3565
rn = "VPEConf0";
3452
// break;
3566
// break;
3453
3567
case 3:
3454
// gen_op_dmtc0_vpeconf1(); /* MT ASE */
3568
// gen_op_mtc0_vpeconf1(); /* MT ASE */
3455
3569
rn = "VPEConf1";
3456
// break;
3570
// break;
3457
3571
case 4:
3458
// gen_op_dmtc0_YQMask(); /* MT ASE */
3572
// gen_op_mtc0_YQMask(); /* MT ASE */
3459
3573
rn = "YQMask";
3460
// break;
3574
// break;
3461
3575
case 5:
3462
// gen_op_dmtc0_vpeschedule(); /* MT ASE */
3576
// gen_op_mtc0_vpeschedule(); /* MT ASE */
3463
3577
rn = "VPESchedule";
3464
// break;
3578
// break;
3465
3579
case 6:
3466
// gen_op_dmtc0_vpeschefback(); /* MT ASE */
3580
// gen_op_mtc0_vpeschefback(); /* MT ASE */
3467
3581
rn = "VPEScheFBack";
3468
// break;
3582
// break;
3469
3583
case 7:
3470
// gen_op_dmtc0_vpeopt(); /* MT ASE */
3584
// gen_op_mtc0_vpeopt(); /* MT ASE */
3471
3585
rn = "VPEOpt";
3472
// break;
3586
// break;
3473
3587
default:
3474
3588
goto die;
3475
3589
}
3477
3591
case 2:
3478
3592
switch (sel) {
3479
3593
case 0:
3480
gen_op_dmtc0_entrylo0();
3481
rn = "EntryLo0";
3482
break;
3594
gen_op_mtc0_entrylo0();
3595
rn = "EntryLo0";
3596
break;
3483
3597
case 1:
3484
// gen_op_dmtc0_tcstatus(); /* MT ASE */
3485
rn = "TCStatus";
3486
// break;
3598
// gen_op_mtc0_tcstatus(); /* MT ASE */
3599
rn = "TCStatus";
3600
// break;
3487
3601
case 2:
3488
// gen_op_dmtc0_tcbind(); /* MT ASE */
3489
rn = "TCBind";
3490
// break;
3602
// gen_op_mtc0_tcbind(); /* MT ASE */
3603
rn = "TCBind";
3604
// break;
3491
3605
case 3:
3492
// gen_op_dmtc0_tcrestart(); /* MT ASE */
3493
rn = "TCRestart";
3494
// break;
3606
// gen_op_mtc0_tcrestart(); /* MT ASE */
3607
rn = "TCRestart";
3608
// break;
3495
3609
case 4:
3496
// gen_op_dmtc0_tchalt(); /* MT ASE */
3497
rn = "TCHalt";
3498
// break;
3610
// gen_op_mtc0_tchalt(); /* MT ASE */
3611
rn = "TCHalt";
3612
// break;
3499
3613
case 5:
3500
// gen_op_dmtc0_tccontext(); /* MT ASE */
3501
rn = "TCContext";
3502
// break;
3614
// gen_op_mtc0_tccontext(); /* MT ASE */
3615
rn = "TCContext";
3616
// break;
3503
3617
case 6:
3504
// gen_op_dmtc0_tcschedule(); /* MT ASE */
3505
rn = "TCSchedule";
3506
// break;
3618
// gen_op_mtc0_tcschedule(); /* MT ASE */
3619
rn = "TCSchedule";
3620
// break;
3507
3621
case 7:
3508
// gen_op_dmtc0_tcschefback(); /* MT ASE */
3509
rn = "TCScheFBack";
3510
// break;
3622
// gen_op_mtc0_tcschefback(); /* MT ASE */
3623
rn = "TCScheFBack";
3624
// break;
3511
3625
default:
3512
3626
goto die;
3513
3627
}
3515
3629
case 3:
3516
3630
switch (sel) {
3517
3631
case 0:
3518
gen_op_dmtc0_entrylo1();
3519
rn = "EntryLo1";
3520
break;
3632
gen_op_mtc0_entrylo1();
3633
rn = "EntryLo1";
3634
break;
3521
3635
default:
3522
3636
goto die;
3523
}
3637
}
3524
3638
break;
3525
3639
case 4:
3526
3640
switch (sel) {
3527
3641
case 0:
3528
gen_op_dmtc0_context();
3529
rn = "Context";
3530
break;
3642
gen_op_mtc0_context();
3643
rn = "Context";
3644
break;
3531
3645
case 1:
3532
// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
3533
rn = "ContextConfig";
3534
// break;
3646
// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3647
rn = "ContextConfig";
3648
// break;
3535
3649
default:
3536
3650
goto die;
3537
}
3651
}
3538
3652
break;
3539
3653
case 5:
3540
3654
switch (sel) {
3541
3655
case 0:
3542
gen_op_mtc0_pagemask();
3543
rn = "PageMask";
3544
break;
3656
gen_op_mtc0_pagemask();
3657
rn = "PageMask";
3658
break;
3545
3659
case 1:
3546
gen_op_mtc0_pagegrain();
3547
rn = "PageGrain";
3548
break;
3660
check_mips_r2(env, ctx);
3661
gen_op_mtc0_pagegrain();
3662
rn = "PageGrain";
3663
break;
3549
3664
default:
3550
3665
goto die;
3551
}
3666
}
3552
3667
break;
3553
3668
case 6:
3554
3669
switch (sel) {
3555
3670
case 0:
3556
gen_op_mtc0_wired();
3557
rn = "Wired";
3558
break;
3671
gen_op_mtc0_wired();
3672
rn = "Wired";
3673
break;
3559
3674
case 1:
3560
// gen_op_dmtc0_srsconf0(); /* shadow registers */
3561
rn = "SRSConf0";
3562
// break;
3675
// gen_op_mtc0_srsconf0(); /* shadow registers */
3676
rn = "SRSConf0";
3677
// break;
3563
3678
case 2:
3564
// gen_op_dmtc0_srsconf1(); /* shadow registers */
3565
rn = "SRSConf1";
3566
// break;
3679
// gen_op_mtc0_srsconf1(); /* shadow registers */
3680
rn = "SRSConf1";
3681
// break;
3567
3682
case 3:
3568
// gen_op_dmtc0_srsconf2(); /* shadow registers */
3569
rn = "SRSConf2";
3570
// break;
3683
// gen_op_mtc0_srsconf2(); /* shadow registers */
3684
rn = "SRSConf2";
3685
// break;
3571
3686
case 4:
3572
// gen_op_dmtc0_srsconf3(); /* shadow registers */
3573
rn = "SRSConf3";
3574
// break;
3687
// gen_op_mtc0_srsconf3(); /* shadow registers */
3688
rn = "SRSConf3";
3689
// break;
3575
3690
case 5:
3576
// gen_op_dmtc0_srsconf4(); /* shadow registers */
3577
rn = "SRSConf4";
3578
// break;
3691
// gen_op_mtc0_srsconf4(); /* shadow registers */
3692
rn = "SRSConf4";
3693
// break;
3579
3694
default:
3580
3695
goto die;
3581
}
3696
}
3582
3697
break;
3583
3698
case 7:
3584
3699
switch (sel) {
3585
3700
case 0:
3586
gen_op_mtc0_hwrena();
3587
rn = "HWREna";
3588
break;
3701
check_mips_r2(env, ctx);
3702
gen_op_mtc0_hwrena();
3703
rn = "HWREna";
3704
break;
3589
3705
default:
3590
3706
goto die;
3591
}
3707
}
3592
3708
break;
3593
3709
case 8:
3594
3710
/* ignored */
3597
3713
case 9:
3598
3714
switch (sel) {
3599
3715
case 0:
3600
gen_op_mtc0_count();
3601
rn = "Count";
3602
break;
3603
/* 6,7 are implementation dependent */
3716
gen_op_mtc0_count();
3717
rn = "Count";
3718
break;
3719
/* 6,7 are implementation dependent */
3604
3720
default:
3605
3721
goto die;
3606
}
3607
/* Stop translation as we may have switched the execution mode */
3608
ctx->bstate = BS_STOP;
3722
}
3723
/* Stop translation as we may have switched the execution mode */
3724
ctx->bstate = BS_STOP;
3609
3725
break;
3610
3726
case 10:
3611
3727
switch (sel) {
3612
3728
case 0:
3613
gen_op_mtc0_entryhi();
3614
rn = "EntryHi";
3615
break;
3729
gen_op_mtc0_entryhi();
3730
rn = "EntryHi";
3731
break;
3616
3732
default:
3617
3733
goto die;
3618
}
3734
}
3619
3735
break;
3620
3736
case 11:
3621
3737
switch (sel) {
3622
3738
case 0:
3623
gen_op_mtc0_compare();
3624
rn = "Compare";
3625
break;
3626
/* 6,7 are implementation dependent */
3739
gen_op_mtc0_compare();
3740
rn = "Compare";
3741
break;
3742
/* 6,7 are implementation dependent */
3627
3743
default:
3628
3744
goto die;
3629
}
3630
/* Stop translation as we may have switched the execution mode */
3631
ctx->bstate = BS_STOP;
3745
}
3746
/* Stop translation as we may have switched the execution mode */
3747
ctx->bstate = BS_STOP;
3632
3748
break;
3633
3749
case 12:
3634
3750
switch (sel) {
3635
3751
case 0:
3636
gen_op_mtc0_status();
3637
rn = "Status";
3638
break;
3752
gen_op_mtc0_status();
3753
/* BS_STOP isn't good enough here, hflags may have changed. */
3754
gen_save_pc(ctx->pc + 4);
3755
ctx->bstate = BS_EXCP;
3756
rn = "Status";
3757
break;
3639
3758
case 1:
3640
gen_op_mtc0_intctl();
3641
rn = "IntCtl";
3642
break;
3759
check_mips_r2(env, ctx);
3760
gen_op_mtc0_intctl();
3761
/* Stop translation as we may have switched the execution mode */
3762
ctx->bstate = BS_STOP;
3763
rn = "IntCtl";
3764
break;
3643
3765
case 2:
3644
gen_op_mtc0_srsctl();
3645
rn = "SRSCtl";
3646
break;
3766
check_mips_r2(env, ctx);
3767
gen_op_mtc0_srsctl();
3768
/* Stop translation as we may have switched the execution mode */
3769
ctx->bstate = BS_STOP;
3770
rn = "SRSCtl";
3771
break;
3647
3772
case 3:
3648
gen_op_mtc0_srsmap(); /* shadow registers */
3649
rn = "SRSMap";
3650
break;
3773
check_mips_r2(env, ctx);
3774
gen_op_mtc0_srsmap();
3775
/* Stop translation as we may have switched the execution mode */
3776
ctx->bstate = BS_STOP;
3777
rn = "SRSMap";
3778
break;
3651
3779
default:
3652
3780
goto die;
3653
}
3654
/* Stop translation as we may have switched the execution mode */
3655
ctx->bstate = BS_STOP;
3781
}
3656
3782
break;
3657
3783
case 13:
3658
3784
switch (sel) {
3659
3785
case 0:
3660
gen_op_mtc0_cause();
3661
rn = "Cause";
3662
break;
3786
gen_op_mtc0_cause();
3787
rn = "Cause";
3788
break;
3663
3789
default:
3664
3790
goto die;
3665
}
3666
/* Stop translation as we may have switched the execution mode */
3667
ctx->bstate = BS_STOP;
3791
}
3792
/* Stop translation as we may have switched the execution mode */
3793
ctx->bstate = BS_STOP;
3668
3794
break;
3669
3795
case 14:
3670
3796
switch (sel) {
3671
3797
case 0:
3672
gen_op_dmtc0_epc();
3673
rn = "EPC";
3674
break;
3798
gen_op_mtc0_epc();
3799
rn = "EPC";
3800
break;
3675
3801
default:
3676
3802
goto die;
3677
}
3803
}
3678
3804
break;
3679
3805
case 15:
3680
3806
switch (sel) {
3681
3807
case 0:
3682
/* ignored */
3683
rn = "PRid";
3684
break;
3808
/* ignored */
3809
rn = "PRid";
3810
break;
3685
3811
case 1:
3686
gen_op_mtc0_ebase();
3687
rn = "EBase";
3688
break;
3812
check_mips_r2(env, ctx);
3813
gen_op_mtc0_ebase();
3814
rn = "EBase";
3815
break;
3689
3816
default:
3690
3817
goto die;
3691
}
3818
}
3692
3819
break;
3693
3820
case 16:
3694
3821
switch (sel) {
3695
3822
case 0:
3696
3823
gen_op_mtc0_config0();
3697
3824
rn = "Config";
3825
/* Stop translation as we may have switched the execution mode */
3826
ctx->bstate = BS_STOP;
3698
3827
break;
3699
3828
case 1:
3700
/* ignored */
3829
/* ignored */
3701
3830
rn = "Config1";
3702
3831
break;
3703
3832
case 2:
3704
3833
gen_op_mtc0_config2();
3705
3834
rn = "Config2";
3835
/* Stop translation as we may have switched the execution mode */
3836
ctx->bstate = BS_STOP;
3706
3837
break;
3707
3838
case 3:
3708
/* ignored */
3839
/* ignored */
3709
3840
rn = "Config3";
3710
3841
break;
3711
3842
/* 6,7 are implementation dependent */
3713
3844
rn = "Invalid config selector";
3714
3845
goto die;
3715
3846
}
3716
/* Stop translation as we may have switched the execution mode */
3717
ctx->bstate = BS_STOP;
3718
3847
break;
3719
3848
case 17:
3720
3849
switch (sel) {
3721
3850
case 0:
3722
/* ignored */
3723
rn = "LLAddr";
3724
break;
3851
/* ignored */
3852
rn = "LLAddr";
3853
break;
3725
3854
default:
3726
3855
goto die;
3727
3856
}
3728
3857
break;
3729
3858
case 18:
3730
3859
switch (sel) {
3731
case 0:
3732
gen_op_dmtc0_watchlo0();
3733
rn = "WatchLo";
3734
break;
3735
case 1:
3736
// gen_op_dmtc0_watchlo1();
3737
rn = "WatchLo1";
3738
// break;
3739
case 2:
3740
// gen_op_dmtc0_watchlo2();
3741
rn = "WatchLo2";
3742
// break;
3743
case 3:
3744
// gen_op_dmtc0_watchlo3();
3745
rn = "WatchLo3";
3746
// break;
3747
case 4:
3748
// gen_op_dmtc0_watchlo4();
3749
rn = "WatchLo4";
3750
// break;
3751
case 5:
3752
// gen_op_dmtc0_watchlo5();
3753
rn = "WatchLo5";
3754
// break;
3755
case 6:
3756
// gen_op_dmtc0_watchlo6();
3757
rn = "WatchLo6";
3758
// break;
3759
case 7:
3760
// gen_op_dmtc0_watchlo7();
3761
rn = "WatchLo7";
3762
// break;
3860
case 0 ... 7:
3861
gen_op_mtc0_watchlo(sel);
3862
rn = "WatchLo";
3863
break;
3763
3864
default:
3764
3865
goto die;
3765
3866
}
3766
3867
break;
3767
3868
case 19:
3768
3869
switch (sel) {
3769
case 0:
3770
gen_op_mtc0_watchhi0();
3771
rn = "WatchHi";
3772
break;
3773
case 1:
3774
// gen_op_dmtc0_watchhi1();
3775
rn = "WatchHi1";
3776
// break;
3777
case 2:
3778
// gen_op_dmtc0_watchhi2();
3779
rn = "WatchHi2";
3780
// break;
3781
case 3:
3782
// gen_op_dmtc0_watchhi3();
3783
rn = "WatchHi3";
3784
// break;
3785
case 4:
3786
// gen_op_dmtc0_watchhi4();
3787
rn = "WatchHi4";
3788
// break;
3789
case 5:
3790
// gen_op_dmtc0_watchhi5();
3791
rn = "WatchHi5";
3792
// break;
3793
case 6:
3794
// gen_op_dmtc0_watchhi6();
3795
rn = "WatchHi6";
3796
// break;
3797
case 7:
3798
// gen_op_dmtc0_watchhi7();
3799
rn = "WatchHi7";
3800
// break;
3870
case 0 ... 7:
3871
gen_op_mtc0_watchhi(sel);
3872
rn = "WatchHi";
3873
break;
3801
3874
default:
3802
3875
goto die;
3803
3876
}
3805
3878
case 20:
3806
3879
switch (sel) {
3807
3880
case 0:
3808
/* 64 bit MMU only */
3809
gen_op_dmtc0_xcontext();
3810
rn = "XContext";
3811
break;
3881
#ifdef TARGET_MIPS64
3882
gen_op_mtc0_xcontext();
3883
rn = "XContext";
3884
break;
3885
#endif
3812
3886
default:
3813
3887
goto die;
3814
3888
}
3817
3891
/* Officially reserved, but sel 0 is used for R1x000 framemask */
3818
3892
switch (sel) {
3819
3893
case 0:
3820
gen_op_mtc0_framemask();
3821
rn = "Framemask";
3822
break;
3894
gen_op_mtc0_framemask();
3895
rn = "Framemask";
3896
break;
3823
3897
default:
3824
3898
goto die;
3825
3899
}
3827
3901
case 22:
3828
3902
/* ignored */
3829
3903
rn = "Diagnostic"; /* implementation dependent */
3830
break;
3904
break;
3831
3905
case 23:
3832
3906
switch (sel) {
3833
3907
case 0:
3834
gen_op_mtc0_debug(); /* EJTAG support */
3835
rn = "Debug";
3836
break;
3908
gen_op_mtc0_debug(); /* EJTAG support */
3909
/* BS_STOP isn't good enough here, hflags may have changed. */
3910
gen_save_pc(ctx->pc + 4);
3911
ctx->bstate = BS_EXCP;
3912
rn = "Debug";
3913
break;
3837
3914
case 1:
3838
// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
3839
rn = "TraceControl";
3840
// break;
3915
// gen_op_mtc0_tracecontrol(); /* PDtrace support */
3916
/* Stop translation as we may have switched the execution mode */
3917
ctx->bstate = BS_STOP;
3918
rn = "TraceControl";
3919
// break;
3841
3920
case 2:
3842
// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
3843
rn = "TraceControl2";
3844
// break;
3921
// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
3922
/* Stop translation as we may have switched the execution mode */
3923
ctx->bstate = BS_STOP;
3924
rn = "TraceControl2";
3925
// break;
3845
3926
case 3:
3846
// gen_op_dmtc0_usertracedata(); /* PDtrace support */
3847
rn = "UserTraceData";
3848
// break;
3927
// gen_op_mtc0_usertracedata(); /* PDtrace support */
3928
/* Stop translation as we may have switched the execution mode */
3929
ctx->bstate = BS_STOP;
3930
rn = "UserTraceData";
3931
// break;
3849
3932
case 4:
3850
// gen_op_dmtc0_debug(); /* PDtrace support */
3851
rn = "TraceBPC";
3852
// break;
3933
// gen_op_mtc0_debug(); /* PDtrace support */
3934
/* Stop translation as we may have switched the execution mode */
3935
ctx->bstate = BS_STOP;
3936
rn = "TraceBPC";
3937
// break;
3853
3938
default:
3854
3939
goto die;
3855
3940
}
3856
/* Stop translation as we may have switched the execution mode */
3857
ctx->bstate = BS_STOP;
3858
3941
break;
3859
3942
case 24:
3860
3943
switch (sel) {
3861
3944
case 0:
3862
gen_op_dmtc0_depc(); /* EJTAG support */
3863
rn = "DEPC";
3864
break;
3945
gen_op_mtc0_depc(); /* EJTAG support */
3946
rn = "DEPC";
3947
break;
3865
3948
default:
3866
3949
goto die;
3867
3950
}
3869
3952
case 25:
3870
3953
switch (sel) {
3871
3954
case 0:
3872
gen_op_mtc0_performance0();
3873
rn = "Performance0";
3874
break;
3955
gen_op_mtc0_performance0();
3956
rn = "Performance0";
3957
break;
3875
3958
case 1:
3876
// gen_op_dmtc0_performance1();
3877
rn = "Performance1";
3878
// break;
3959
// gen_op_mtc0_performance1();
3960
rn = "Performance1";
3961
// break;
3879
3962
case 2:
3880
// gen_op_dmtc0_performance2();
3881
rn = "Performance2";
3882
// break;
3963
// gen_op_mtc0_performance2();
3964
rn = "Performance2";
3965
// break;
3883
3966
case 3:
3884
// gen_op_dmtc0_performance3();
3885
rn = "Performance3";
3886
// break;
3967
// gen_op_mtc0_performance3();
3968
rn = "Performance3";
3969
// break;
3887
3970
case 4:
3888
// gen_op_dmtc0_performance4();
3889
rn = "Performance4";
3890
// break;
3971
// gen_op_mtc0_performance4();
3972
rn = "Performance4";
3973
// break;
3891
3974
case 5:
3892
// gen_op_dmtc0_performance5();
3893
rn = "Performance5";
3894
// break;
3975
// gen_op_mtc0_performance5();
3976
rn = "Performance5";
3977
// break;
3895
3978
case 6:
3896
// gen_op_dmtc0_performance6();
3897
rn = "Performance6";
3898
// break;
3979
// gen_op_mtc0_performance6();
3980
rn = "Performance6";
3981
// break;
3899
3982
case 7:
3900
// gen_op_dmtc0_performance7();
3901
rn = "Performance7";
3902
// break;
3983
// gen_op_mtc0_performance7();
3984
rn = "Performance7";
3985
// break;
3903
3986
default:
3904
3987
goto die;
3905
3988
}
3906
break;
3989
break;
3907
3990
case 26:
3908
/* ignored */
3991
/* ignored */
3909
3992
rn = "ECC";
3910
break;
3993
break;
3911
3994
case 27:
3912
3995
switch (sel) {
3913
3996
case 0 ... 3:
3914
/* ignored */
3915
rn = "CacheErr";
3916
break;
3997
/* ignored */
3998
rn = "CacheErr";
3999
break;
3917
4000
default:
3918
4001
goto die;
3919
4002
}
3920
break;
4003
break;
3921
4004
case 28:
3922
4005
switch (sel) {
3923
4006
case 0:
3931
4014
case 3:
3932
4015
case 5:
3933
4016
case 7:
3934
gen_op_mtc0_datalo();
4017
gen_op_mtc0_datalo();
3935
4018
rn = "DataLo";
3936
4019
break;
3937
4020
default:
3951
4034
case 3:
3952
4035
case 5:
3953
4036
case 7:
3954
gen_op_mtc0_datahi();
4037
gen_op_mtc0_datahi();
3955
4038
rn = "DataHi";
3956
4039
break;
3957
4040
default:
3958
4041
rn = "invalid sel";
3959
4042
goto die;
3960
4043
}
3961
break;
4044
break;
3962
4045
case 30:
3963
4046
switch (sel) {
3964
4047
case 0:
3965
gen_op_dmtc0_errorepc();
3966
rn = "ErrorEPC";
3967
break;
4048
gen_op_mtc0_errorepc();
4049
rn = "ErrorEPC";
4050
break;
3968
4051
default:
3969
4052
goto die;
3970
4053
}
3972
4055
case 31:
3973
4056
switch (sel) {
3974
4057
case 0:
3975
gen_op_mtc0_desave(); /* EJTAG support */
3976
rn = "DESAVE";
3977
break;
4058
gen_op_mtc0_desave(); /* EJTAG support */
4059
rn = "DESAVE";
4060
break;
3978
4061
default:
3979
4062
goto die;
3980
4063
}
3981
/* Stop translation as we may have switched the execution mode */
3982
ctx->bstate = BS_STOP;
4064
/* Stop translation as we may have switched the execution mode */
4065
ctx->bstate = BS_STOP;
3983
4066
break;
3984
4067
default:
3985
goto die;
4068
goto die;
3986
4069
}
3987
4070
#if defined MIPS_DEBUG_DISAS
3988
4071
if (loglevel & CPU_LOG_TB_IN_ASM) {
4001
4084
#endif
4002
4085
generate_exception(ctx, EXCP_RI);
4003
4086
}
4087
#endif /* TARGET_MIPS64 */
4004
4088
4005
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4089
static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
4006
4090
{
4007
const char *opn = "unk";
4008
4009
if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
4010
(ctx->hflags & MIPS_HFLAG_UM)) &&
4011
!(ctx->hflags & MIPS_HFLAG_ERL) &&
4012
!(ctx->hflags & MIPS_HFLAG_EXL)) {
4013
if (loglevel & CPU_LOG_TB_IN_ASM) {
4014
fprintf(logfile, "CP0 is not usable\n");
4015
}
4016
generate_exception (ctx, EXCP_CpU);
4017
return;
4018
}
4091
const char *opn = "ldst";
4019
4092
4020
4093
switch (opc) {
4021
4094
case OPC_MFC0:
4023
4096
/* Treat as NOP */
4024
4097
return;
4025
4098
}
4026
gen_mfc0(ctx, rd, ctx->opcode & 0x7);
4099
gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);
4027
4100
gen_op_store_T0_gpr(rt);
4028
4101
opn = "mfc0";
4029
4102
break;
4030
4103
case OPC_MTC0:
4031
/* If we get an exception, we want to restart at next instruction */
4032
/* XXX: breaks for mtc in delay slot */
4033
ctx->pc += 4;
4034
save_cpu_state(ctx, 1);
4035
ctx->pc -= 4;
4036
4104
GEN_LOAD_REG_TN(T0, rt);
4037
gen_mtc0(ctx, rd, ctx->opcode & 0x7);
4105
gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
4038
4106
opn = "mtc0";
4039
4107
break;
4108
#ifdef TARGET_MIPS64
4040
4109
case OPC_DMFC0:
4041
4110
if (rt == 0) {
4042
4111
/* Treat as NOP */
4043
4112
return;
4044
4113
}
4045
gen_dmfc0(ctx, rd, ctx->opcode & 0x7);
4114
gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);
4046
4115
gen_op_store_T0_gpr(rt);
4047
4116
opn = "dmfc0";
4048
4117
break;
4049
4118
case OPC_DMTC0:
4050
/* If we get an exception, we want to restart at next instruction */
4051
/* XXX: breaks for dmtc in delay slot */
4052
ctx->pc += 4;
4053
save_cpu_state(ctx, 1);
4054
ctx->pc -= 4;
4055
4119
GEN_LOAD_REG_TN(T0, rt);
4056
gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
4120
gen_dmtc0(env,ctx, rd, ctx->opcode & 0x7);
4057
4121
opn = "dmtc0";
4058
4122
break;
4059
#if defined(MIPS_USES_R4K_TLB)
4123
#endif
4060
4124
case OPC_TLBWI:
4125
opn = "tlbwi";
4126
if (!env->do_tlbwi)
4127
goto die;
4061
4128
gen_op_tlbwi();
4062
opn = "tlbwi";
4063
4129
break;
4064
4130
case OPC_TLBWR:
4131
opn = "tlbwr";
4132
if (!env->do_tlbwr)
4133
goto die;
4065
4134
gen_op_tlbwr();
4066
opn = "tlbwr";
4067
4135
break;
4068
4136
case OPC_TLBP:
4137
opn = "tlbp";
4138
if (!env->do_tlbp)
4139
goto die;
4069
4140
gen_op_tlbp();
4070
opn = "tlbp";
4071
4141
break;
4072
4142
case OPC_TLBR:
4143
opn = "tlbr";
4144
if (!env->do_tlbr)
4145
goto die;
4073
4146
gen_op_tlbr();
4074
opn = "tlbr";
4075
4147
break;
4076
#endif
4077
4148
case OPC_ERET:
4078
4149
opn = "eret";
4079
save_cpu_state(ctx, 0);
4080
4150
gen_op_eret();
4081
4151
ctx->bstate = BS_EXCP;
4082
4152
break;
4083
4153
case OPC_DERET:
4084
4154
opn = "deret";
4085
4155
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
4156
MIPS_INVAL(opn);
4086
4157
generate_exception(ctx, EXCP_RI);
4087
4158
} else {
4088
save_cpu_state(ctx, 0);
4089
4159
gen_op_deret();
4090
4160
ctx->bstate = BS_EXCP;
4091
4161
}
4100
4170
ctx->bstate = BS_EXCP;
4101
4171
break;
4102
4172
default:
4103
if (loglevel & CPU_LOG_TB_IN_ASM) {
4104
fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
4105
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4106
((ctx->opcode >> 16) & 0x1F));
4107
}
4173
die:
4174
MIPS_INVAL(opn);
4108
4175
generate_exception(ctx, EXCP_RI);
4109
4176
return;
4110
4177
}
4111
4178
MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
4112
4179
}
4113
4180
4114
#ifdef MIPS_USES_FPU
4115
4116
4181
/* CP1 Branches (before delay slot) */
4117
4182
static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4118
int32_t offset)
4183
int32_t cc, int32_t offset)
4119
4184
{
4120
4185
target_ulong btarget;
4186
const char *opn = "cp1 cond branch";
4121
4187
4122
4188
btarget = ctx->pc + 4 + offset;
4123
4189
4124
4190
switch (op) {
4125
4191
case OPC_BC1F:
4126
gen_op_bc1f();
4127
MIPS_DEBUG("bc1f " TLSZ, btarget);
4192
gen_op_bc1f(cc);
4193
opn = "bc1f";
4128
4194
goto not_likely;
4129
4195
case OPC_BC1FL:
4130
gen_op_bc1f();
4131
MIPS_DEBUG("bc1fl " TLSZ, btarget);
4196
gen_op_bc1f(cc);
4197
opn = "bc1fl";
4132
4198
goto likely;
4133
4199
case OPC_BC1T:
4134
gen_op_bc1t();
4135
MIPS_DEBUG("bc1t " TLSZ, btarget);
4136
not_likely:
4137
ctx->hflags |= MIPS_HFLAG_BC;
4138
break;
4200
gen_op_bc1t(cc);
4201
opn = "bc1t";
4202
goto not_likely;
4139
4203
case OPC_BC1TL:
4140
gen_op_bc1t();
4141
MIPS_DEBUG("bc1tl " TLSZ, btarget);
4204
gen_op_bc1t(cc);
4205
opn = "bc1tl";
4142
4206
likely:
4143
4207
ctx->hflags |= MIPS_HFLAG_BL;
4144
break;
4145
default:
4146
MIPS_INVAL("cp1 branch/jump");
4147
generate_exception_err (ctx, EXCP_RI, 1);
4208
gen_op_set_bcond();
4209
gen_op_save_bcond();
4210
break;
4211
case OPC_BC1FANY2:
4212
gen_op_bc1any2f(cc);
4213
opn = "bc1any2f";
4214
goto not_likely;
4215
case OPC_BC1TANY2:
4216
gen_op_bc1any2t(cc);
4217
opn = "bc1any2t";
4218
goto not_likely;
4219
case OPC_BC1FANY4:
4220
gen_op_bc1any4f(cc);
4221
opn = "bc1any4f";
4222
goto not_likely;
4223
case OPC_BC1TANY4:
4224
gen_op_bc1any4t(cc);
4225
opn = "bc1any4t";
4226
not_likely:
4227
ctx->hflags |= MIPS_HFLAG_BC;
4228
gen_op_set_bcond();
4229
break;
4230
default:
4231
MIPS_INVAL(opn);
4232
generate_exception (ctx, EXCP_RI);
4148
4233
return;
4149
4234
}
4150
gen_op_set_bcond();
4151
4152
MIPS_DEBUG("enter ds: cond %02x target " TLSZ,
4235
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
4153
4236
ctx->hflags, btarget);
4154
4237
ctx->btarget = btarget;
4155
4156
return;
4157
4238
}
4158
4239
4159
4240
/* Coprocessor 1 (FPU) */
4241
4242
#define FOP(func, fmt) (((fmt) << 21) | (func))
4243
4160
4244
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4161
4245
{
4162
const char *opn = "unk";
4246
const char *opn = "cp1 move";
4163
4247
4164
4248
switch (opc) {
4165
4249
case OPC_MFC1:
4175
4259
opn = "mtc1";
4176
4260
break;
4177
4261
case OPC_CFC1:
4178
if (fs != 0 && fs != 31) {
4179
MIPS_INVAL("cfc1 freg");
4180
generate_exception_err (ctx, EXCP_RI, 1);
4181
return;
4182
}
4183
4262
GEN_LOAD_IMM_TN(T1, fs);
4184
4263
gen_op_cfc1();
4185
4264
GEN_STORE_TN_REG(rt, T0);
4186
4265
opn = "cfc1";
4187
4266
break;
4188
4267
case OPC_CTC1:
4189
if (fs != 0 && fs != 31) {
4190
MIPS_INVAL("ctc1 freg");
4191
generate_exception_err (ctx, EXCP_RI, 1);
4192
return;
4193
}
4194
4268
GEN_LOAD_IMM_TN(T1, fs);
4195
4269
GEN_LOAD_REG_TN(T0, rt);
4196
4270
gen_op_ctc1();
4197
4271
opn = "ctc1";
4198
4272
break;
4199
4273
case OPC_DMFC1:
4274
GEN_LOAD_FREG_FTN(DT0, fs);
4275
gen_op_dmfc1();
4276
GEN_STORE_TN_REG(rt, T0);
4277
opn = "dmfc1";
4278
break;
4200
4279
case OPC_DMTC1:
4201
/* Not implemented, fallthrough. */
4280
GEN_LOAD_REG_TN(T0, rt);
4281
gen_op_dmtc1();
4282
GEN_STORE_FTN_FREG(fs, DT0);
4283
opn = "dmtc1";
4284
break;
4285
case OPC_MFHC1:
4286
GEN_LOAD_FREG_FTN(WTH0, fs);
4287
gen_op_mfhc1();
4288
GEN_STORE_TN_REG(rt, T0);
4289
opn = "mfhc1";
4290
break;
4291
case OPC_MTHC1:
4292
GEN_LOAD_REG_TN(T0, rt);
4293
gen_op_mthc1();
4294
GEN_STORE_FTN_FREG(fs, WTH0);
4295
opn = "mthc1";
4296
break;
4202
4297
default:
4203
if (loglevel & CPU_LOG_TB_IN_ASM) {
4204
fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
4205
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4206
((ctx->opcode >> 16) & 0x1F));
4207
}
4208
generate_exception_err (ctx, EXCP_RI, 1);
4298
MIPS_INVAL(opn);
4299
generate_exception (ctx, EXCP_RI);
4209
4300
return;
4210
4301
}
4211
4302
MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
4212
4303
}
4213
4304
4214
/* verify if floating point register is valid; an operation is not defined
4215
* if bit 0 of any register specification is set and the FR bit in the
4216
* Status register equals zero, since the register numbers specify an
4217
* even-odd pair of adjacent coprocessor general registers. When the FR bit
4218
* in the Status register equals one, both even and odd register numbers
4219
* are valid.
4220
*
4221
* Multiple float registers can be checked by calling
4222
* CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
4223
*/
4224
#define CHECK_FR(ctx, freg) do { \
4225
if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
4226
generate_exception_err (ctx, EXCP_RI, 1); \
4227
return; \
4228
} \
4229
} while(0)
4230
4231
#define FOP(func, fmt) (((fmt) << 21) | (func))
4232
4233
static void gen_farith (DisasContext *ctx, uint32_t op1, int ft, int fs, int fd)
4234
{
4235
const char *opn = "unk";
4305
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
4306
{
4307
uint32_t ccbit;
4308
4309
GEN_LOAD_REG_TN(T0, rd);
4310
GEN_LOAD_REG_TN(T1, rs);
4311
if (cc) {
4312
ccbit = 1 << (24 + cc);
4313
} else
4314
ccbit = 1 << 23;
4315
if (!tf)
4316
gen_op_movf(ccbit);
4317
else
4318
gen_op_movt(ccbit);
4319
GEN_STORE_TN_REG(rd, T0);
4320
}
4321
4322
#define GEN_MOVCF(fmt) \
4323
static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
4324
{ \
4325
uint32_t ccbit; \
4326
\
4327
if (cc) { \
4328
ccbit = 1 << (24 + cc); \
4329
} else \
4330
ccbit = 1 << 23; \
4331
if (!tf) \
4332
glue(gen_op_float_movf_, fmt)(ccbit); \
4333
else \
4334
glue(gen_op_float_movt_, fmt)(ccbit); \
4335
}
4336
GEN_MOVCF(d);
4337
GEN_MOVCF(s);
4338
GEN_MOVCF(ps);
4339
#undef GEN_MOVCF
4340
4341
static void gen_farith (DisasContext *ctx, uint32_t op1,
4342
int ft, int fs, int fd, int cc)
4343
{
4344
const char *opn = "farith";
4236
4345
const char *condnames[] = {
4237
4346
"c.f",
4238
4347
"c.un",
4251
4360
"c.le",
4252
4361
"c.ngt",
4253
4362
};
4254
int binary = 0;
4363
const char *condnames_abs[] = {
4364
"cabs.f",
4365
"cabs.un",
4366
"cabs.eq",
4367
"cabs.ueq",
4368
"cabs.olt",
4369
"cabs.ult",
4370
"cabs.ole",
4371
"cabs.ule",
4372
"cabs.sf",
4373
"cabs.ngle",
4374
"cabs.seq",
4375
"cabs.ngl",
4376
"cabs.lt",
4377
"cabs.nge",
4378
"cabs.le",
4379
"cabs.ngt",
4380
};
4381
enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
4255
4382
uint32_t func = ctx->opcode & 0x3f;
4256
4383
4257
4384
switch (ctx->opcode & FOP(0x3f, 0x1f)) {
4385
case FOP(0, 16):
4386
GEN_LOAD_FREG_FTN(WT0, fs);
4387
GEN_LOAD_FREG_FTN(WT1, ft);
4388
gen_op_float_add_s();
4389
GEN_STORE_FTN_FREG(fd, WT2);
4390
opn = "add.s";
4391
optype = BINOP;
4392
break;
4393
case FOP(1, 16):
4394
GEN_LOAD_FREG_FTN(WT0, fs);
4395
GEN_LOAD_FREG_FTN(WT1, ft);
4396
gen_op_float_sub_s();
4397
GEN_STORE_FTN_FREG(fd, WT2);
4398
opn = "sub.s";
4399
optype = BINOP;
4400
break;
4401
case FOP(2, 16):
4402
GEN_LOAD_FREG_FTN(WT0, fs);
4403
GEN_LOAD_FREG_FTN(WT1, ft);
4404
gen_op_float_mul_s();
4405
GEN_STORE_FTN_FREG(fd, WT2);
4406
opn = "mul.s";
4407
optype = BINOP;
4408
break;
4409
case FOP(3, 16):
4410
GEN_LOAD_FREG_FTN(WT0, fs);
4411
GEN_LOAD_FREG_FTN(WT1, ft);
4412
gen_op_float_div_s();
4413
GEN_STORE_FTN_FREG(fd, WT2);
4414
opn = "div.s";
4415
optype = BINOP;
4416
break;
4417
case FOP(4, 16):
4418
GEN_LOAD_FREG_FTN(WT0, fs);
4419
gen_op_float_sqrt_s();
4420
GEN_STORE_FTN_FREG(fd, WT2);
4421
opn = "sqrt.s";
4422
break;
4423
case FOP(5, 16):
4424
GEN_LOAD_FREG_FTN(WT0, fs);
4425
gen_op_float_abs_s();
4426
GEN_STORE_FTN_FREG(fd, WT2);
4427
opn = "abs.s";
4428
break;
4429
case FOP(6, 16):
4430
GEN_LOAD_FREG_FTN(WT0, fs);
4431
gen_op_float_mov_s();
4432
GEN_STORE_FTN_FREG(fd, WT2);
4433
opn = "mov.s";
4434
break;
4435
case FOP(7, 16):
4436
GEN_LOAD_FREG_FTN(WT0, fs);
4437
gen_op_float_chs_s();
4438
GEN_STORE_FTN_FREG(fd, WT2);
4439
opn = "neg.s";
4440
break;
4441
case FOP(8, 16):
4442
check_cp1_64bitmode(ctx);
4443
GEN_LOAD_FREG_FTN(WT0, fs);
4444
gen_op_float_roundl_s();
4445
GEN_STORE_FTN_FREG(fd, DT2);
4446
opn = "round.l.s";
4447
break;
4448
case FOP(9, 16):
4449
check_cp1_64bitmode(ctx);
4450
GEN_LOAD_FREG_FTN(WT0, fs);
4451
gen_op_float_truncl_s();
4452
GEN_STORE_FTN_FREG(fd, DT2);
4453
opn = "trunc.l.s";
4454
break;
4455
case FOP(10, 16):
4456
check_cp1_64bitmode(ctx);
4457
GEN_LOAD_FREG_FTN(WT0, fs);
4458
gen_op_float_ceill_s();
4459
GEN_STORE_FTN_FREG(fd, DT2);
4460
opn = "ceil.l.s";
4461
break;
4462
case FOP(11, 16):
4463
check_cp1_64bitmode(ctx);
4464
GEN_LOAD_FREG_FTN(WT0, fs);
4465
gen_op_float_floorl_s();
4466
GEN_STORE_FTN_FREG(fd, DT2);
4467
opn = "floor.l.s";
4468
break;
4469
case FOP(12, 16):
4470
GEN_LOAD_FREG_FTN(WT0, fs);
4471
gen_op_float_roundw_s();
4472
GEN_STORE_FTN_FREG(fd, WT2);
4473
opn = "round.w.s";
4474
break;
4475
case FOP(13, 16):
4476
GEN_LOAD_FREG_FTN(WT0, fs);
4477
gen_op_float_truncw_s();
4478
GEN_STORE_FTN_FREG(fd, WT2);
4479
opn = "trunc.w.s";
4480
break;
4481
case FOP(14, 16):
4482
GEN_LOAD_FREG_FTN(WT0, fs);
4483
gen_op_float_ceilw_s();
4484
GEN_STORE_FTN_FREG(fd, WT2);
4485
opn = "ceil.w.s";
4486
break;
4487
case FOP(15, 16):
4488
GEN_LOAD_FREG_FTN(WT0, fs);
4489
gen_op_float_floorw_s();
4490
GEN_STORE_FTN_FREG(fd, WT2);
4491
opn = "floor.w.s";
4492
break;
4493
case FOP(17, 16):
4494
GEN_LOAD_REG_TN(T0, ft);
4495
GEN_LOAD_FREG_FTN(WT0, fs);
4496
GEN_LOAD_FREG_FTN(WT2, fd);
4497
gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1);
4498
GEN_STORE_FTN_FREG(fd, WT2);
4499
opn = "movcf.s";
4500
break;
4501
case FOP(18, 16):
4502
GEN_LOAD_REG_TN(T0, ft);
4503
GEN_LOAD_FREG_FTN(WT0, fs);
4504
GEN_LOAD_FREG_FTN(WT2, fd);
4505
gen_op_float_movz_s();
4506
GEN_STORE_FTN_FREG(fd, WT2);
4507
opn = "movz.s";
4508
break;
4509
case FOP(19, 16):
4510
GEN_LOAD_REG_TN(T0, ft);
4511
GEN_LOAD_FREG_FTN(WT0, fs);
4512
GEN_LOAD_FREG_FTN(WT2, fd);
4513
gen_op_float_movn_s();
4514
GEN_STORE_FTN_FREG(fd, WT2);
4515
opn = "movn.s";
4516
break;
4517
case FOP(21, 16):
4518
GEN_LOAD_FREG_FTN(WT0, fs);
4519
gen_op_float_recip_s();
4520
GEN_STORE_FTN_FREG(fd, WT2);
4521
opn = "recip.s";
4522
break;
4523
case FOP(22, 16):
4524
GEN_LOAD_FREG_FTN(WT0, fs);
4525
gen_op_float_rsqrt_s();
4526
GEN_STORE_FTN_FREG(fd, WT2);
4527
opn = "rsqrt.s";
4528
break;
4529
case FOP(28, 16):
4530
check_cp1_64bitmode(ctx);
4531
GEN_LOAD_FREG_FTN(WT0, fs);
4532
GEN_LOAD_FREG_FTN(WT2, fd);
4533
gen_op_float_recip2_s();
4534
GEN_STORE_FTN_FREG(fd, WT2);
4535
opn = "recip2.s";
4536
break;
4537
case FOP(29, 16):
4538
check_cp1_64bitmode(ctx);
4539
GEN_LOAD_FREG_FTN(WT0, fs);
4540
gen_op_float_recip1_s();
4541
GEN_STORE_FTN_FREG(fd, WT2);
4542
opn = "recip1.s";
4543
break;
4544
case FOP(30, 16):
4545
check_cp1_64bitmode(ctx);
4546
GEN_LOAD_FREG_FTN(WT0, fs);
4547
gen_op_float_rsqrt1_s();
4548
GEN_STORE_FTN_FREG(fd, WT2);
4549
opn = "rsqrt1.s";
4550
break;
4551
case FOP(31, 16):
4552
check_cp1_64bitmode(ctx);
4553
GEN_LOAD_FREG_FTN(WT0, fs);
4554
GEN_LOAD_FREG_FTN(WT2, ft);
4555
gen_op_float_rsqrt2_s();
4556
GEN_STORE_FTN_FREG(fd, WT2);
4557
opn = "rsqrt2.s";
4558
break;
4559
case FOP(33, 16):
4560
check_cp1_registers(ctx, fd);
4561
GEN_LOAD_FREG_FTN(WT0, fs);
4562
gen_op_float_cvtd_s();
4563
GEN_STORE_FTN_FREG(fd, DT2);
4564
opn = "cvt.d.s";
4565
break;
4566
case FOP(36, 16):
4567
GEN_LOAD_FREG_FTN(WT0, fs);
4568
gen_op_float_cvtw_s();
4569
GEN_STORE_FTN_FREG(fd, WT2);
4570
opn = "cvt.w.s";
4571
break;
4572
case FOP(37, 16):
4573
check_cp1_64bitmode(ctx);
4574
GEN_LOAD_FREG_FTN(WT0, fs);
4575
gen_op_float_cvtl_s();
4576
GEN_STORE_FTN_FREG(fd, DT2);
4577
opn = "cvt.l.s";
4578
break;
4579
case FOP(38, 16):
4580
check_cp1_64bitmode(ctx);
4581
GEN_LOAD_FREG_FTN(WT1, fs);
4582
GEN_LOAD_FREG_FTN(WT0, ft);
4583
gen_op_float_cvtps_s();
4584
GEN_STORE_FTN_FREG(fd, DT2);
4585
opn = "cvt.ps.s";
4586
break;
4587
case FOP(48, 16):
4588
case FOP(49, 16):
4589
case FOP(50, 16):
4590
case FOP(51, 16):
4591
case FOP(52, 16):
4592
case FOP(53, 16):
4593
case FOP(54, 16):
4594
case FOP(55, 16):
4595
case FOP(56, 16):
4596
case FOP(57, 16):
4597
case FOP(58, 16):
4598
case FOP(59, 16):
4599
case FOP(60, 16):
4600
case FOP(61, 16):
4601
case FOP(62, 16):
4602
case FOP(63, 16):
4603
GEN_LOAD_FREG_FTN(WT0, fs);
4604
GEN_LOAD_FREG_FTN(WT1, ft);
4605
if (ctx->opcode & (1 << 6)) {
4606
check_cp1_64bitmode(ctx);
4607
gen_cmpabs_s(func-48, cc);
4608
opn = condnames_abs[func-48];
4609
} else {
4610
gen_cmp_s(func-48, cc);
4611
opn = condnames[func-48];
4612
}
4613
break;
4258
4614
case FOP(0, 17):
4259
CHECK_FR(ctx, fs | ft | fd);
4615
check_cp1_registers(ctx, fs | ft | fd);
4260
4616
GEN_LOAD_FREG_FTN(DT0, fs);
4261
4617
GEN_LOAD_FREG_FTN(DT1, ft);
4262
4618
gen_op_float_add_d();
4263
4619
GEN_STORE_FTN_FREG(fd, DT2);
4264
4620
opn = "add.d";
4265
binary = 1;
4621
optype = BINOP;
4266
4622
break;
4267
4623
case FOP(1, 17):
4268
CHECK_FR(ctx, fs | ft | fd);
4624
check_cp1_registers(ctx, fs | ft | fd);
4269
4625
GEN_LOAD_FREG_FTN(DT0, fs);
4270
4626
GEN_LOAD_FREG_FTN(DT1, ft);
4271
4627
gen_op_float_sub_d();
4272
4628
GEN_STORE_FTN_FREG(fd, DT2);
4273
4629
opn = "sub.d";
4274
binary = 1;
4630
optype = BINOP;
4275
4631
break;
4276
4632
case FOP(2, 17):
4277
CHECK_FR(ctx, fs | ft | fd);
4633
check_cp1_registers(ctx, fs | ft | fd);
4278
4634
GEN_LOAD_FREG_FTN(DT0, fs);
4279
4635
GEN_LOAD_FREG_FTN(DT1, ft);
4280
4636
gen_op_float_mul_d();
4281
4637
GEN_STORE_FTN_FREG(fd, DT2);
4282
4638
opn = "mul.d";
4283
binary = 1;
4639
optype = BINOP;
4284
4640
break;
4285
4641
case FOP(3, 17):
4286
CHECK_FR(ctx, fs | ft | fd);
4642
check_cp1_registers(ctx, fs | ft | fd);
4287
4643
GEN_LOAD_FREG_FTN(DT0, fs);
4288
4644
GEN_LOAD_FREG_FTN(DT1, ft);
4289
4645
gen_op_float_div_d();
4290
4646
GEN_STORE_FTN_FREG(fd, DT2);
4291
4647
opn = "div.d";
4292
binary = 1;
4648
optype = BINOP;
4293
4649
break;
4294
4650
case FOP(4, 17):
4295
CHECK_FR(ctx, fs | fd);
4651
check_cp1_registers(ctx, fs | fd);
4296
4652
GEN_LOAD_FREG_FTN(DT0, fs);
4297
4653
gen_op_float_sqrt_d();
4298
4654
GEN_STORE_FTN_FREG(fd, DT2);
4299
4655
opn = "sqrt.d";
4300
4656
break;
4301
4657
case FOP(5, 17):
4302
CHECK_FR(ctx, fs | fd);
4658
check_cp1_registers(ctx, fs | fd);
4303
4659
GEN_LOAD_FREG_FTN(DT0, fs);
4304
4660
gen_op_float_abs_d();
4305
4661
GEN_STORE_FTN_FREG(fd, DT2);
4306
4662
opn = "abs.d";
4307
4663
break;
4308
4664
case FOP(6, 17):
4309
CHECK_FR(ctx, fs | fd);
4665
check_cp1_registers(ctx, fs | fd);
4310
4666
GEN_LOAD_FREG_FTN(DT0, fs);
4311
4667
gen_op_float_mov_d();
4312
4668
GEN_STORE_FTN_FREG(fd, DT2);
4313
4669
opn = "mov.d";
4314
4670
break;
4315
4671
case FOP(7, 17):
4316
CHECK_FR(ctx, fs | fd);
4672
check_cp1_registers(ctx, fs | fd);
4317
4673
GEN_LOAD_FREG_FTN(DT0, fs);
4318
4674
gen_op_float_chs_d();
4319
4675
GEN_STORE_FTN_FREG(fd, DT2);
4320
4676
opn = "neg.d";
4321
4677
break;
4322
/* 8 - round.l */
4323
/* 9 - trunc.l */
4324
/* 10 - ceil.l */
4325
/* 11 - floor.l */
4678
case FOP(8, 17):
4679
check_cp1_64bitmode(ctx);
4680
GEN_LOAD_FREG_FTN(DT0, fs);
4681
gen_op_float_roundl_d();
4682
GEN_STORE_FTN_FREG(fd, DT2);
4683
opn = "round.l.d";
4684
break;
4685
case FOP(9, 17):
4686
check_cp1_64bitmode(ctx);
4687
GEN_LOAD_FREG_FTN(DT0, fs);
4688
gen_op_float_truncl_d();
4689
GEN_STORE_FTN_FREG(fd, DT2);
4690
opn = "trunc.l.d";
4691
break;
4692
case FOP(10, 17):
4693
check_cp1_64bitmode(ctx);
4694
GEN_LOAD_FREG_FTN(DT0, fs);
4695
gen_op_float_ceill_d();
4696
GEN_STORE_FTN_FREG(fd, DT2);
4697
opn = "ceil.l.d";
4698
break;
4699
case FOP(11, 17):
4700
check_cp1_64bitmode(ctx);
4701
GEN_LOAD_FREG_FTN(DT0, fs);
4702
gen_op_float_floorl_d();
4703
GEN_STORE_FTN_FREG(fd, DT2);
4704
opn = "floor.l.d";
4705
break;
4326
4706
case FOP(12, 17):
4327
CHECK_FR(ctx, fs | fd);
4707
check_cp1_registers(ctx, fs);
4328
4708
GEN_LOAD_FREG_FTN(DT0, fs);
4329
4709
gen_op_float_roundw_d();
4330
4710
GEN_STORE_FTN_FREG(fd, WT2);
4331
4711
opn = "round.w.d";
4332
4712
break;
4333
4713
case FOP(13, 17):
4334
CHECK_FR(ctx, fs | fd);
4714
check_cp1_registers(ctx, fs);
4335
4715
GEN_LOAD_FREG_FTN(DT0, fs);
4336
4716
gen_op_float_truncw_d();
4337
4717
GEN_STORE_FTN_FREG(fd, WT2);
4338
4718
opn = "trunc.w.d";
4339
4719
break;
4340
4720
case FOP(14, 17):
4341
CHECK_FR(ctx, fs | fd);
4721
check_cp1_registers(ctx, fs);
4342
4722
GEN_LOAD_FREG_FTN(DT0, fs);
4343
4723
gen_op_float_ceilw_d();
4344
4724
GEN_STORE_FTN_FREG(fd, WT2);
4345
4725
opn = "ceil.w.d";
4346
4726
break;
4347
4727
case FOP(15, 17):
4348
CHECK_FR(ctx, fs | fd);
4728
check_cp1_registers(ctx, fs);
4349
4729
GEN_LOAD_FREG_FTN(DT0, fs);
4350
4730
gen_op_float_floorw_d();
4351
4731
GEN_STORE_FTN_FREG(fd, WT2);
4352
4732
opn = "floor.w.d";
4353
4733
break;
4354
case FOP(33, 16): /* cvt.d.s */
4355
CHECK_FR(ctx, fs | fd);
4356
GEN_LOAD_FREG_FTN(WT0, fs);
4357
gen_op_float_cvtd_s();
4358
GEN_STORE_FTN_FREG(fd, DT2);
4359
opn = "cvt.d.s";
4360
break;
4361
case FOP(33, 20): /* cvt.d.w */
4362
CHECK_FR(ctx, fs | fd);
4363
GEN_LOAD_FREG_FTN(WT0, fs);
4364
gen_op_float_cvtd_w();
4365
GEN_STORE_FTN_FREG(fd, DT2);
4366
opn = "cvt.d.w";
4734
case FOP(17, 17):
4735
GEN_LOAD_REG_TN(T0, ft);
4736
GEN_LOAD_FREG_FTN(DT0, fs);
4737
GEN_LOAD_FREG_FTN(DT2, fd);
4738
gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1);
4739
GEN_STORE_FTN_FREG(fd, DT2);
4740
opn = "movcf.d";
4741
break;
4742
case FOP(18, 17):
4743
GEN_LOAD_REG_TN(T0, ft);
4744
GEN_LOAD_FREG_FTN(DT0, fs);
4745
GEN_LOAD_FREG_FTN(DT2, fd);
4746
gen_op_float_movz_d();
4747
GEN_STORE_FTN_FREG(fd, DT2);
4748
opn = "movz.d";
4749
break;
4750
case FOP(19, 17):
4751
GEN_LOAD_REG_TN(T0, ft);
4752
GEN_LOAD_FREG_FTN(DT0, fs);
4753
GEN_LOAD_FREG_FTN(DT2, fd);
4754
gen_op_float_movn_d();
4755
GEN_STORE_FTN_FREG(fd, DT2);
4756
opn = "movn.d";
4757
break;
4758
case FOP(21, 17):
4759
check_cp1_registers(ctx, fs | fd);
4760
GEN_LOAD_FREG_FTN(DT0, fs);
4761
gen_op_float_recip_d();
4762
GEN_STORE_FTN_FREG(fd, DT2);
4763
opn = "recip.d";
4764
break;
4765
case FOP(22, 17):
4766
check_cp1_registers(ctx, fs | fd);
4767
GEN_LOAD_FREG_FTN(DT0, fs);
4768
gen_op_float_rsqrt_d();
4769
GEN_STORE_FTN_FREG(fd, DT2);
4770
opn = "rsqrt.d";
4771
break;
4772
case FOP(28, 17):
4773
check_cp1_64bitmode(ctx);
4774
GEN_LOAD_FREG_FTN(DT0, fs);
4775
GEN_LOAD_FREG_FTN(DT2, ft);
4776
gen_op_float_recip2_d();
4777
GEN_STORE_FTN_FREG(fd, DT2);
4778
opn = "recip2.d";
4779
break;
4780
case FOP(29, 17):
4781
check_cp1_64bitmode(ctx);
4782
GEN_LOAD_FREG_FTN(DT0, fs);
4783
gen_op_float_recip1_d();
4784
GEN_STORE_FTN_FREG(fd, DT2);
4785
opn = "recip1.d";
4786
break;
4787
case FOP(30, 17):
4788
check_cp1_64bitmode(ctx);
4789
GEN_LOAD_FREG_FTN(DT0, fs);
4790
gen_op_float_rsqrt1_d();
4791
GEN_STORE_FTN_FREG(fd, DT2);
4792
opn = "rsqrt1.d";
4793
break;
4794
case FOP(31, 17):
4795
check_cp1_64bitmode(ctx);
4796
GEN_LOAD_FREG_FTN(DT0, fs);
4797
GEN_LOAD_FREG_FTN(DT2, ft);
4798
gen_op_float_rsqrt2_d();
4799
GEN_STORE_FTN_FREG(fd, DT2);
4800
opn = "rsqrt2.d";
4367
4801
break;
4368
4802
case FOP(48, 17):
4369
4803
case FOP(49, 17):
4381
4815
case FOP(61, 17):
4382
4816
case FOP(62, 17):
4383
4817
case FOP(63, 17):
4384
CHECK_FR(ctx, fs | ft);
4385
4818
GEN_LOAD_FREG_FTN(DT0, fs);
4386
4819
GEN_LOAD_FREG_FTN(DT1, ft);
4387
gen_cmp_d(func-48);
4388
opn = condnames[func-48];
4389
break;
4390
case FOP(0, 16):
4391
CHECK_FR(ctx, fs | ft | fd);
4392
GEN_LOAD_FREG_FTN(WT0, fs);
4393
GEN_LOAD_FREG_FTN(WT1, ft);
4394
gen_op_float_add_s();
4395
GEN_STORE_FTN_FREG(fd, WT2);
4396
opn = "add.s";
4397
binary = 1;
4398
break;
4399
case FOP(1, 16):
4400
CHECK_FR(ctx, fs | ft | fd);
4401
GEN_LOAD_FREG_FTN(WT0, fs);
4402
GEN_LOAD_FREG_FTN(WT1, ft);
4403
gen_op_float_sub_s();
4404
GEN_STORE_FTN_FREG(fd, WT2);
4405
opn = "sub.s";
4406
binary = 1;
4407
break;
4408
case FOP(2, 16):
4409
CHECK_FR(ctx, fs | ft | fd);
4410
GEN_LOAD_FREG_FTN(WT0, fs);
4411
GEN_LOAD_FREG_FTN(WT1, ft);
4412
gen_op_float_mul_s();
4413
GEN_STORE_FTN_FREG(fd, WT2);
4414
opn = "mul.s";
4415
binary = 1;
4416
break;
4417
case FOP(3, 16):
4418
CHECK_FR(ctx, fs | ft | fd);
4419
GEN_LOAD_FREG_FTN(WT0, fs);
4420
GEN_LOAD_FREG_FTN(WT1, ft);
4421
gen_op_float_div_s();
4422
GEN_STORE_FTN_FREG(fd, WT2);
4423
opn = "div.s";
4424
binary = 1;
4425
break;
4426
case FOP(4, 16):
4427
CHECK_FR(ctx, fs | fd);
4428
GEN_LOAD_FREG_FTN(WT0, fs);
4429
gen_op_float_sqrt_s();
4430
GEN_STORE_FTN_FREG(fd, WT2);
4431
opn = "sqrt.s";
4432
break;
4433
case FOP(5, 16):
4434
CHECK_FR(ctx, fs | fd);
4435
GEN_LOAD_FREG_FTN(WT0, fs);
4436
gen_op_float_abs_s();
4437
GEN_STORE_FTN_FREG(fd, WT2);
4438
opn = "abs.s";
4439
break;
4440
case FOP(6, 16):
4441
CHECK_FR(ctx, fs | fd);
4442
GEN_LOAD_FREG_FTN(WT0, fs);
4443
gen_op_float_mov_s();
4444
GEN_STORE_FTN_FREG(fd, WT2);
4445
opn = "mov.s";
4446
break;
4447
case FOP(7, 16):
4448
CHECK_FR(ctx, fs | fd);
4449
GEN_LOAD_FREG_FTN(WT0, fs);
4450
gen_op_float_chs_s();
4451
GEN_STORE_FTN_FREG(fd, WT2);
4452
opn = "neg.s";
4453
break;
4454
case FOP(12, 16):
4455
CHECK_FR(ctx, fs | fd);
4456
GEN_LOAD_FREG_FTN(WT0, fs);
4457
gen_op_float_roundw_s();
4458
GEN_STORE_FTN_FREG(fd, WT2);
4459
opn = "round.w.s";
4460
break;
4461
case FOP(13, 16):
4462
CHECK_FR(ctx, fs | fd);
4463
GEN_LOAD_FREG_FTN(WT0, fs);
4464
gen_op_float_truncw_s();
4465
GEN_STORE_FTN_FREG(fd, WT2);
4466
opn = "trunc.w.s";
4467
break;
4468
case FOP(32, 17): /* cvt.s.d */
4469
CHECK_FR(ctx, fs | fd);
4820
if (ctx->opcode & (1 << 6)) {
4821
check_cp1_64bitmode(ctx);
4822
gen_cmpabs_d(func-48, cc);
4823
opn = condnames_abs[func-48];
4824
} else {
4825
check_cp1_registers(ctx, fs | ft);
4826
gen_cmp_d(func-48, cc);
4827
opn = condnames[func-48];
4828
}
4829
break;
4830
case FOP(32, 17):
4831
check_cp1_registers(ctx, fs);
4470
4832
GEN_LOAD_FREG_FTN(DT0, fs);
4471
4833
gen_op_float_cvts_d();
4472
4834
GEN_STORE_FTN_FREG(fd, WT2);
4473
4835
opn = "cvt.s.d";
4474
4836
break;
4475
case FOP(32, 20): /* cvt.s.w */
4476
CHECK_FR(ctx, fs | fd);
4837
case FOP(36, 17):
4838
check_cp1_registers(ctx, fs);
4839
GEN_LOAD_FREG_FTN(DT0, fs);
4840
gen_op_float_cvtw_d();
4841
GEN_STORE_FTN_FREG(fd, WT2);
4842
opn = "cvt.w.d";
4843
break;
4844
case FOP(37, 17):
4845
check_cp1_64bitmode(ctx);
4846
GEN_LOAD_FREG_FTN(DT0, fs);
4847
gen_op_float_cvtl_d();
4848
GEN_STORE_FTN_FREG(fd, DT2);
4849
opn = "cvt.l.d";
4850
break;
4851
case FOP(32, 20):
4477
4852
GEN_LOAD_FREG_FTN(WT0, fs);
4478
4853
gen_op_float_cvts_w();
4479
4854
GEN_STORE_FTN_FREG(fd, WT2);
4480
4855
opn = "cvt.s.w";
4481
4856
break;
4482
case FOP(36, 16): /* cvt.w.s */
4483
CHECK_FR(ctx, fs | fd);
4484
GEN_LOAD_FREG_FTN(WT0, fs);
4485
gen_op_float_cvtw_s();
4486
GEN_STORE_FTN_FREG(fd, WT2);
4487
opn = "cvt.w.s";
4488
break;
4489
case FOP(36, 17): /* cvt.w.d */
4490
CHECK_FR(ctx, fs | fd);
4491
GEN_LOAD_FREG_FTN(DT0, fs);
4492
gen_op_float_cvtw_d();
4493
GEN_STORE_FTN_FREG(fd, WT2);
4494
opn = "cvt.w.d";
4495
break;
4496
case FOP(48, 16):
4497
case FOP(49, 16):
4498
case FOP(50, 16):
4499
case FOP(51, 16):
4500
case FOP(52, 16):
4501
case FOP(53, 16):
4502
case FOP(54, 16):
4503
case FOP(55, 16):
4504
case FOP(56, 16):
4505
case FOP(57, 16):
4506
case FOP(58, 16):
4507
case FOP(59, 16):
4508
case FOP(60, 16):
4509
case FOP(61, 16):
4510
case FOP(62, 16):
4511
case FOP(63, 16):
4512
CHECK_FR(ctx, fs | ft);
4513
GEN_LOAD_FREG_FTN(WT0, fs);
4514
GEN_LOAD_FREG_FTN(WT1, ft);
4515
gen_cmp_s(func-48);
4516
opn = condnames[func-48];
4517
break;
4518
default:
4519
if (loglevel & CPU_LOG_TB_IN_ASM) {
4520
fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
4521
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4522
((ctx->opcode >> 16) & 0x1F));
4857
case FOP(33, 20):
4858
check_cp1_registers(ctx, fd);
4859
GEN_LOAD_FREG_FTN(WT0, fs);
4860
gen_op_float_cvtd_w();
4861
GEN_STORE_FTN_FREG(fd, DT2);
4862
opn = "cvt.d.w";
4863
break;
4864
case FOP(32, 21):
4865
check_cp1_64bitmode(ctx);
4866
GEN_LOAD_FREG_FTN(DT0, fs);
4867
gen_op_float_cvts_l();
4868
GEN_STORE_FTN_FREG(fd, WT2);
4869
opn = "cvt.s.l";
4870
break;
4871
case FOP(33, 21):
4872
check_cp1_64bitmode(ctx);
4873
GEN_LOAD_FREG_FTN(DT0, fs);
4874
gen_op_float_cvtd_l();
4875
GEN_STORE_FTN_FREG(fd, DT2);
4876
opn = "cvt.d.l";
4877
break;
4878
case FOP(38, 20):
4879
case FOP(38, 21):
4880
check_cp1_64bitmode(ctx);
4881
GEN_LOAD_FREG_FTN(WT0, fs);
4882
GEN_LOAD_FREG_FTN(WTH0, fs);
4883
gen_op_float_cvtps_pw();
4884
GEN_STORE_FTN_FREG(fd, WT2);
4885
GEN_STORE_FTN_FREG(fd, WTH2);
4886
opn = "cvt.ps.pw";
4887
break;
4888
case FOP(0, 22):
4889
check_cp1_64bitmode(ctx);
4890
GEN_LOAD_FREG_FTN(WT0, fs);
4891
GEN_LOAD_FREG_FTN(WTH0, fs);
4892
GEN_LOAD_FREG_FTN(WT1, ft);
4893
GEN_LOAD_FREG_FTN(WTH1, ft);
4894
gen_op_float_add_ps();
4895
GEN_STORE_FTN_FREG(fd, WT2);
4896
GEN_STORE_FTN_FREG(fd, WTH2);
4897
opn = "add.ps";
4898
break;
4899
case FOP(1, 22):
4900
check_cp1_64bitmode(ctx);
4901
GEN_LOAD_FREG_FTN(WT0, fs);
4902
GEN_LOAD_FREG_FTN(WTH0, fs);
4903
GEN_LOAD_FREG_FTN(WT1, ft);
4904
GEN_LOAD_FREG_FTN(WTH1, ft);
4905
gen_op_float_sub_ps();
4906
GEN_STORE_FTN_FREG(fd, WT2);
4907
GEN_STORE_FTN_FREG(fd, WTH2);
4908
opn = "sub.ps";
4909
break;
4910
case FOP(2, 22):
4911
check_cp1_64bitmode(ctx);
4912
GEN_LOAD_FREG_FTN(WT0, fs);
4913
GEN_LOAD_FREG_FTN(WTH0, fs);
4914
GEN_LOAD_FREG_FTN(WT1, ft);
4915
GEN_LOAD_FREG_FTN(WTH1, ft);
4916
gen_op_float_mul_ps();
4917
GEN_STORE_FTN_FREG(fd, WT2);
4918
GEN_STORE_FTN_FREG(fd, WTH2);
4919
opn = "mul.ps";
4920
break;
4921
case FOP(5, 22):
4922
check_cp1_64bitmode(ctx);
4923
GEN_LOAD_FREG_FTN(WT0, fs);
4924
GEN_LOAD_FREG_FTN(WTH0, fs);
4925
gen_op_float_abs_ps();
4926
GEN_STORE_FTN_FREG(fd, WT2);
4927
GEN_STORE_FTN_FREG(fd, WTH2);
4928
opn = "abs.ps";
4929
break;
4930
case FOP(6, 22):
4931
check_cp1_64bitmode(ctx);
4932
GEN_LOAD_FREG_FTN(WT0, fs);
4933
GEN_LOAD_FREG_FTN(WTH0, fs);
4934
gen_op_float_mov_ps();
4935
GEN_STORE_FTN_FREG(fd, WT2);
4936
GEN_STORE_FTN_FREG(fd, WTH2);
4937
opn = "mov.ps";
4938
break;
4939
case FOP(7, 22):
4940
check_cp1_64bitmode(ctx);
4941
GEN_LOAD_FREG_FTN(WT0, fs);
4942
GEN_LOAD_FREG_FTN(WTH0, fs);
4943
gen_op_float_chs_ps();
4944
GEN_STORE_FTN_FREG(fd, WT2);
4945
GEN_STORE_FTN_FREG(fd, WTH2);
4946
opn = "neg.ps";
4947
break;
4948
case FOP(17, 22):
4949
check_cp1_64bitmode(ctx);
4950
GEN_LOAD_REG_TN(T0, ft);
4951
GEN_LOAD_FREG_FTN(WT0, fs);
4952
GEN_LOAD_FREG_FTN(WTH0, fs);
4953
GEN_LOAD_FREG_FTN(WT2, fd);
4954
GEN_LOAD_FREG_FTN(WTH2, fd);
4955
gen_movcf_ps(ctx, (ft >> 2) & 0x7, ft & 0x1);
4956
GEN_STORE_FTN_FREG(fd, WT2);
4957
GEN_STORE_FTN_FREG(fd, WTH2);
4958
opn = "movcf.ps";
4959
break;
4960
case FOP(18, 22):
4961
check_cp1_64bitmode(ctx);
4962
GEN_LOAD_REG_TN(T0, ft);
4963
GEN_LOAD_FREG_FTN(WT0, fs);
4964
GEN_LOAD_FREG_FTN(WTH0, fs);
4965
GEN_LOAD_FREG_FTN(WT2, fd);
4966
GEN_LOAD_FREG_FTN(WTH2, fd);
4967
gen_op_float_movz_ps();
4968
GEN_STORE_FTN_FREG(fd, WT2);
4969
GEN_STORE_FTN_FREG(fd, WTH2);
4970
opn = "movz.ps";
4971
break;
4972
case FOP(19, 22):
4973
check_cp1_64bitmode(ctx);
4974
GEN_LOAD_REG_TN(T0, ft);
4975
GEN_LOAD_FREG_FTN(WT0, fs);
4976
GEN_LOAD_FREG_FTN(WTH0, fs);
4977
GEN_LOAD_FREG_FTN(WT2, fd);
4978
GEN_LOAD_FREG_FTN(WTH2, fd);
4979
gen_op_float_movn_ps();
4980
GEN_STORE_FTN_FREG(fd, WT2);
4981
GEN_STORE_FTN_FREG(fd, WTH2);
4982
opn = "movn.ps";
4983
break;
4984
case FOP(24, 22):
4985
check_cp1_64bitmode(ctx);
4986
GEN_LOAD_FREG_FTN(WT0, ft);
4987
GEN_LOAD_FREG_FTN(WTH0, ft);
4988
GEN_LOAD_FREG_FTN(WT1, fs);
4989
GEN_LOAD_FREG_FTN(WTH1, fs);
4990
gen_op_float_addr_ps();
4991
GEN_STORE_FTN_FREG(fd, WT2);
4992
GEN_STORE_FTN_FREG(fd, WTH2);
4993
opn = "addr.ps";
4994
break;
4995
case FOP(26, 22):
4996
check_cp1_64bitmode(ctx);
4997
GEN_LOAD_FREG_FTN(WT0, ft);
4998
GEN_LOAD_FREG_FTN(WTH0, ft);
4999
GEN_LOAD_FREG_FTN(WT1, fs);
5000
GEN_LOAD_FREG_FTN(WTH1, fs);
5001
gen_op_float_mulr_ps();
5002
GEN_STORE_FTN_FREG(fd, WT2);
5003
GEN_STORE_FTN_FREG(fd, WTH2);
5004
opn = "mulr.ps";
5005
break;
5006
case FOP(28, 22):
5007
check_cp1_64bitmode(ctx);
5008
GEN_LOAD_FREG_FTN(WT0, fs);
5009
GEN_LOAD_FREG_FTN(WTH0, fs);
5010
GEN_LOAD_FREG_FTN(WT2, fd);
5011
GEN_LOAD_FREG_FTN(WTH2, fd);
5012
gen_op_float_recip2_ps();
5013
GEN_STORE_FTN_FREG(fd, WT2);
5014
GEN_STORE_FTN_FREG(fd, WTH2);
5015
opn = "recip2.ps";
5016
break;
5017
case FOP(29, 22):
5018
check_cp1_64bitmode(ctx);
5019
GEN_LOAD_FREG_FTN(WT0, fs);
5020
GEN_LOAD_FREG_FTN(WTH0, fs);
5021
gen_op_float_recip1_ps();
5022
GEN_STORE_FTN_FREG(fd, WT2);
5023
GEN_STORE_FTN_FREG(fd, WTH2);
5024
opn = "recip1.ps";
5025
break;
5026
case FOP(30, 22):
5027
check_cp1_64bitmode(ctx);
5028
GEN_LOAD_FREG_FTN(WT0, fs);
5029
GEN_LOAD_FREG_FTN(WTH0, fs);
5030
gen_op_float_rsqrt1_ps();
5031
GEN_STORE_FTN_FREG(fd, WT2);
5032
GEN_STORE_FTN_FREG(fd, WTH2);
5033
opn = "rsqrt1.ps";
5034
break;
5035
case FOP(31, 22):
5036
check_cp1_64bitmode(ctx);
5037
GEN_LOAD_FREG_FTN(WT0, fs);
5038
GEN_LOAD_FREG_FTN(WTH0, fs);
5039
GEN_LOAD_FREG_FTN(WT2, ft);
5040
GEN_LOAD_FREG_FTN(WTH2, ft);
5041
gen_op_float_rsqrt2_ps();
5042
GEN_STORE_FTN_FREG(fd, WT2);
5043
GEN_STORE_FTN_FREG(fd, WTH2);
5044
opn = "rsqrt2.ps";
5045
break;
5046
case FOP(32, 22):
5047
check_cp1_64bitmode(ctx);
5048
GEN_LOAD_FREG_FTN(WTH0, fs);
5049
gen_op_float_cvts_pu();
5050
GEN_STORE_FTN_FREG(fd, WT2);
5051
opn = "cvt.s.pu";
5052
break;
5053
case FOP(36, 22):
5054
check_cp1_64bitmode(ctx);
5055
GEN_LOAD_FREG_FTN(WT0, fs);
5056
GEN_LOAD_FREG_FTN(WTH0, fs);
5057
gen_op_float_cvtpw_ps();
5058
GEN_STORE_FTN_FREG(fd, WT2);
5059
GEN_STORE_FTN_FREG(fd, WTH2);
5060
opn = "cvt.pw.ps";
5061
break;
5062
case FOP(40, 22):
5063
check_cp1_64bitmode(ctx);
5064
GEN_LOAD_FREG_FTN(WT0, fs);
5065
gen_op_float_cvts_pl();
5066
GEN_STORE_FTN_FREG(fd, WT2);
5067
opn = "cvt.s.pl";
5068
break;
5069
case FOP(44, 22):
5070
check_cp1_64bitmode(ctx);
5071
GEN_LOAD_FREG_FTN(WT0, fs);
5072
GEN_LOAD_FREG_FTN(WT1, ft);
5073
gen_op_float_pll_ps();
5074
GEN_STORE_FTN_FREG(fd, DT2);
5075
opn = "pll.ps";
5076
break;
5077
case FOP(45, 22):
5078
check_cp1_64bitmode(ctx);
5079
GEN_LOAD_FREG_FTN(WT0, fs);
5080
GEN_LOAD_FREG_FTN(WTH1, ft);
5081
gen_op_float_plu_ps();
5082
GEN_STORE_FTN_FREG(fd, DT2);
5083
opn = "plu.ps";
5084
break;
5085
case FOP(46, 22):
5086
check_cp1_64bitmode(ctx);
5087
GEN_LOAD_FREG_FTN(WTH0, fs);
5088
GEN_LOAD_FREG_FTN(WT1, ft);
5089
gen_op_float_pul_ps();
5090
GEN_STORE_FTN_FREG(fd, DT2);
5091
opn = "pul.ps";
5092
break;
5093
case FOP(47, 22):
5094
check_cp1_64bitmode(ctx);
5095
GEN_LOAD_FREG_FTN(WTH0, fs);
5096
GEN_LOAD_FREG_FTN(WTH1, ft);
5097
gen_op_float_puu_ps();
5098
GEN_STORE_FTN_FREG(fd, DT2);
5099
opn = "puu.ps";
5100
break;
5101
case FOP(48, 22):
5102
case FOP(49, 22):
5103
case FOP(50, 22):
5104
case FOP(51, 22):
5105
case FOP(52, 22):
5106
case FOP(53, 22):
5107
case FOP(54, 22):
5108
case FOP(55, 22):
5109
case FOP(56, 22):
5110
case FOP(57, 22):
5111
case FOP(58, 22):
5112
case FOP(59, 22):
5113
case FOP(60, 22):
5114
case FOP(61, 22):
5115
case FOP(62, 22):
5116
case FOP(63, 22):
5117
check_cp1_64bitmode(ctx);
5118
GEN_LOAD_FREG_FTN(WT0, fs);
5119
GEN_LOAD_FREG_FTN(WTH0, fs);
5120
GEN_LOAD_FREG_FTN(WT1, ft);
5121
GEN_LOAD_FREG_FTN(WTH1, ft);
5122
if (ctx->opcode & (1 << 6)) {
5123
gen_cmpabs_ps(func-48, cc);
5124
opn = condnames_abs[func-48];
5125
} else {
5126
gen_cmp_ps(func-48, cc);
5127
opn = condnames[func-48];
4523
5128
}
4524
generate_exception_err (ctx, EXCP_RI, 1);
5129
break;
5130
default:
5131
MIPS_INVAL(opn);
5132
generate_exception (ctx, EXCP_RI);
4525
5133
return;
4526
5134
}
4527
if (binary)
5135
switch (optype) {
5136
case BINOP:
4528
5137
MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
4529
else
5138
break;
5139
case CMPOP:
5140
MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]);
5141
break;
5142
default:
4530
5143
MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
4531
}
4532
4533
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
4534
{
4535
uint32_t ccbit;
4536
4537
if (cc)
4538
ccbit = 1 << (24 + cc);
4539
else
4540
ccbit = 1 << 23;
4541
if (!tf)
4542
gen_op_movf(ccbit, rd, rs);
4543
else
4544
gen_op_movt(ccbit, rd, rs);
4545
}
4546
4547
#endif /* MIPS_USES_FPU */
5144
break;
5145
}
5146
}
5147
5148
/* Coprocessor 3 (FPU) */
5149
static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
5150
int fd, int fs, int base, int index)
5151
{
5152
const char *opn = "extended float load/store";
5153
int store = 0;
5154
5155
/* All of those work only on 64bit FPUs. */
5156
check_cp1_64bitmode(ctx);
5157
if (base == 0) {
5158
if (index == 0)
5159
gen_op_reset_T0();
5160
else
5161
GEN_LOAD_REG_TN(T0, index);
5162
} else if (index == 0) {
5163
GEN_LOAD_REG_TN(T0, base);
5164
} else {
5165
GEN_LOAD_REG_TN(T0, base);
5166
GEN_LOAD_REG_TN(T1, index);
5167
gen_op_addr_add();
5168
}
5169
/* Don't do NOP if destination is zero: we must perform the actual
5170
* memory access
5171
*/
5172
switch (opc) {
5173
case OPC_LWXC1:
5174
op_ldst(lwc1);
5175
GEN_STORE_FTN_FREG(fd, WT0);
5176
opn = "lwxc1";
5177
break;
5178
case OPC_LDXC1:
5179
op_ldst(ldc1);
5180
GEN_STORE_FTN_FREG(fd, DT0);
5181
opn = "ldxc1";
5182
break;
5183
case OPC_LUXC1:
5184
op_ldst(luxc1);
5185
GEN_STORE_FTN_FREG(fd, DT0);
5186
opn = "luxc1";
5187
break;
5188
case OPC_SWXC1:
5189
GEN_LOAD_FREG_FTN(WT0, fs);
5190
op_ldst(swc1);
5191
opn = "swxc1";
5192
store = 1;
5193
break;
5194
case OPC_SDXC1:
5195
GEN_LOAD_FREG_FTN(DT0, fs);
5196
op_ldst(sdc1);
5197
opn = "sdxc1";
5198
store = 1;
5199
break;
5200
case OPC_SUXC1:
5201
GEN_LOAD_FREG_FTN(DT0, fs);
5202
op_ldst(suxc1);
5203
opn = "suxc1";
5204
store = 1;
5205
break;
5206
default:
5207
MIPS_INVAL(opn);
5208
generate_exception(ctx, EXCP_RI);
5209
return;
5210
}
5211
MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
5212
regnames[index], regnames[base]);
5213
}
5214
5215
static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
5216
int fd, int fr, int fs, int ft)
5217
{
5218
const char *opn = "flt3_arith";
5219
5220
/* All of those work only on 64bit FPUs. */
5221
check_cp1_64bitmode(ctx);
5222
switch (opc) {
5223
case OPC_ALNV_PS:
5224
GEN_LOAD_REG_TN(T0, fr);
5225
GEN_LOAD_FREG_FTN(DT0, fs);
5226
GEN_LOAD_FREG_FTN(DT1, ft);
5227
gen_op_float_alnv_ps();
5228
GEN_STORE_FTN_FREG(fd, DT2);
5229
opn = "alnv.ps";
5230
break;
5231
case OPC_MADD_S:
5232
GEN_LOAD_FREG_FTN(WT0, fs);
5233
GEN_LOAD_FREG_FTN(WT1, ft);
5234
GEN_LOAD_FREG_FTN(WT2, fr);
5235
gen_op_float_muladd_s();
5236
GEN_STORE_FTN_FREG(fd, WT2);
5237
opn = "madd.s";
5238
break;
5239
case OPC_MADD_D:
5240
GEN_LOAD_FREG_FTN(DT0, fs);
5241
GEN_LOAD_FREG_FTN(DT1, ft);
5242
GEN_LOAD_FREG_FTN(DT2, fr);
5243
gen_op_float_muladd_d();
5244
GEN_STORE_FTN_FREG(fd, DT2);
5245
opn = "madd.d";
5246
break;
5247
case OPC_MADD_PS:
5248
GEN_LOAD_FREG_FTN(WT0, fs);
5249
GEN_LOAD_FREG_FTN(WTH0, fs);
5250
GEN_LOAD_FREG_FTN(WT1, ft);
5251
GEN_LOAD_FREG_FTN(WTH1, ft);
5252
GEN_LOAD_FREG_FTN(WT2, fr);
5253
GEN_LOAD_FREG_FTN(WTH2, fr);
5254
gen_op_float_muladd_ps();
5255
GEN_STORE_FTN_FREG(fd, WT2);
5256
GEN_STORE_FTN_FREG(fd, WTH2);
5257
opn = "madd.ps";
5258
break;
5259
case OPC_MSUB_S:
5260
GEN_LOAD_FREG_FTN(WT0, fs);
5261
GEN_LOAD_FREG_FTN(WT1, ft);
5262
GEN_LOAD_FREG_FTN(WT2, fr);
5263
gen_op_float_mulsub_s();
5264
GEN_STORE_FTN_FREG(fd, WT2);
5265
opn = "msub.s";
5266
break;
5267
case OPC_MSUB_D:
5268
GEN_LOAD_FREG_FTN(DT0, fs);
5269
GEN_LOAD_FREG_FTN(DT1, ft);
5270
GEN_LOAD_FREG_FTN(DT2, fr);
5271
gen_op_float_mulsub_d();
5272
GEN_STORE_FTN_FREG(fd, DT2);
5273
opn = "msub.d";
5274
break;
5275
case OPC_MSUB_PS:
5276
GEN_LOAD_FREG_FTN(WT0, fs);
5277
GEN_LOAD_FREG_FTN(WTH0, fs);
5278
GEN_LOAD_FREG_FTN(WT1, ft);
5279
GEN_LOAD_FREG_FTN(WTH1, ft);
5280
GEN_LOAD_FREG_FTN(WT2, fr);
5281
GEN_LOAD_FREG_FTN(WTH2, fr);
5282
gen_op_float_mulsub_ps();
5283
GEN_STORE_FTN_FREG(fd, WT2);
5284
GEN_STORE_FTN_FREG(fd, WTH2);
5285
opn = "msub.ps";
5286
break;
5287
case OPC_NMADD_S:
5288
GEN_LOAD_FREG_FTN(WT0, fs);
5289
GEN_LOAD_FREG_FTN(WT1, ft);
5290
GEN_LOAD_FREG_FTN(WT2, fr);
5291
gen_op_float_nmuladd_s();
5292
GEN_STORE_FTN_FREG(fd, WT2);
5293
opn = "nmadd.s";
5294
break;
5295
case OPC_NMADD_D:
5296
GEN_LOAD_FREG_FTN(DT0, fs);
5297
GEN_LOAD_FREG_FTN(DT1, ft);
5298
GEN_LOAD_FREG_FTN(DT2, fr);
5299
gen_op_float_nmuladd_d();
5300
GEN_STORE_FTN_FREG(fd, DT2);
5301
opn = "nmadd.d";
5302
break;
5303
case OPC_NMADD_PS:
5304
GEN_LOAD_FREG_FTN(WT0, fs);
5305
GEN_LOAD_FREG_FTN(WTH0, fs);
5306
GEN_LOAD_FREG_FTN(WT1, ft);
5307
GEN_LOAD_FREG_FTN(WTH1, ft);
5308
GEN_LOAD_FREG_FTN(WT2, fr);
5309
GEN_LOAD_FREG_FTN(WTH2, fr);
5310
gen_op_float_nmuladd_ps();
5311
GEN_STORE_FTN_FREG(fd, WT2);
5312
GEN_STORE_FTN_FREG(fd, WTH2);
5313
opn = "nmadd.ps";
5314
break;
5315
case OPC_NMSUB_S:
5316
GEN_LOAD_FREG_FTN(WT0, fs);
5317
GEN_LOAD_FREG_FTN(WT1, ft);
5318
GEN_LOAD_FREG_FTN(WT2, fr);
5319
gen_op_float_nmulsub_s();
5320
GEN_STORE_FTN_FREG(fd, WT2);
5321
opn = "nmsub.s";
5322
break;
5323
case OPC_NMSUB_D:
5324
GEN_LOAD_FREG_FTN(DT0, fs);
5325
GEN_LOAD_FREG_FTN(DT1, ft);
5326
GEN_LOAD_FREG_FTN(DT2, fr);
5327
gen_op_float_nmulsub_d();
5328
GEN_STORE_FTN_FREG(fd, DT2);
5329
opn = "nmsub.d";
5330
break;
5331
case OPC_NMSUB_PS:
5332
GEN_LOAD_FREG_FTN(WT0, fs);
5333
GEN_LOAD_FREG_FTN(WTH0, fs);
5334
GEN_LOAD_FREG_FTN(WT1, ft);
5335
GEN_LOAD_FREG_FTN(WTH1, ft);
5336
GEN_LOAD_FREG_FTN(WT2, fr);
5337
GEN_LOAD_FREG_FTN(WTH2, fr);
5338
gen_op_float_nmulsub_ps();
5339
GEN_STORE_FTN_FREG(fd, WT2);
5340
GEN_STORE_FTN_FREG(fd, WTH2);
5341
opn = "nmsub.ps";
5342
break;
5343
default:
5344
MIPS_INVAL(opn);
5345
generate_exception (ctx, EXCP_RI);
5346
return;
5347
}
5348
MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],
5349
fregnames[fs], fregnames[ft]);
5350
}
4548
5351
4549
5352
/* ISA extensions (ASEs) */
4550
5353
/* MIPS16 extension to MIPS32 */
4551
5354
/* SmartMIPS extension to MIPS32 */
4552
5355
4553
#ifdef MIPS_HAS_MIPS64
4554
/* Coprocessor 3 (FPU) */
5356
#ifdef TARGET_MIPS64
4555
5357
4556
5358
/* MDMX extension to MIPS64 */
4557
5359
/* MIPS-3D extension to MIPS64 */
4558
5360
4559
5361
#endif
4560
5362
4561
static void gen_blikely(DisasContext *ctx)
4562
{
4563
int l1;
4564
l1 = gen_new_label();
4565
gen_op_jnz_T2(l1);
4566
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
4567
gen_goto_tb(ctx, 1, ctx->pc + 4);
4568
gen_set_label(l1);
4569
}
4570
4571
static void decode_opc (DisasContext *ctx)
5363
static void decode_opc (CPUState *env, DisasContext *ctx)
4572
5364
{
4573
5365
int32_t offset;
4574
5366
int rs, rt, rd, sa;
4577
5369
4578
5370
/* make sure instructions are on a word boundary */
4579
5371
if (ctx->pc & 0x3) {
5372
env->CP0_BadVAddr = ctx->pc;
4580
5373
generate_exception(ctx, EXCP_AdEL);
4581
5374
return;
4582
5375
}
4583
5376
4584
5377
if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
5378
int l1;
4585
5379
/* Handle blikely not taken case */
4586
MIPS_DEBUG("blikely condition (" TLSZ ")", ctx->pc + 4);
4587
gen_blikely(ctx);
5380
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
5381
l1 = gen_new_label();
5382
gen_op_jnz_T2(l1);
5383
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
5384
gen_goto_tb(ctx, 1, ctx->pc + 4);
5385
gen_set_label(l1);
4588
5386
}
4589
5387
op = MASK_OP_MAJOR(ctx->opcode);
4590
5388
rs = (ctx->opcode >> 21) & 0x1f;
4625
5423
case OPC_MTLO: /* Move to HI/LO */
4626
5424
gen_HILO(ctx, op1, rs);
4627
5425
break;
4628
case OPC_PMON: /* Pmon entry point */
5426
case OPC_PMON: /* Pmon entry point, also R4010 selsl */
5427
#ifdef MIPS_STRICT_STANDARD
5428
MIPS_INVAL("PMON / selsl");
5429
generate_exception(ctx, EXCP_RI);
5430
#else
4629
5431
gen_op_pmon(sa);
5432
#endif
4630
5433
break;
4631
5434
case OPC_SYSCALL:
4632
5435
generate_exception(ctx, EXCP_SYSCALL);
4633
ctx->bstate = BS_EXCP;
4634
5436
break;
4635
5437
case OPC_BREAK:
5438
/* XXX: Hack to work around wrong handling of self-modifying code. */
5439
ctx->pc += 4;
5440
save_cpu_state(ctx, 1);
5441
ctx->pc -= 4;
4636
5442
generate_exception(ctx, EXCP_BREAK);
4637
5443
break;
4638
case OPC_SPIM: /* SPIM ? */
5444
case OPC_SPIM:
5445
#ifdef MIPS_STRICT_STANDARD
5446
MIPS_INVAL("SPIM");
5447
generate_exception(ctx, EXCP_RI);
5448
#else
4639
5449
/* Implemented as RI exception for now. */
4640
5450
MIPS_INVAL("spim (unofficial)");
4641
5451
generate_exception(ctx, EXCP_RI);
5452
#endif
4642
5453
break;
4643
5454
case OPC_SYNC:
4644
5455
/* Treat as a noop. */
4645
5456
break;
4646
5457
4647
#ifdef MIPS_USES_FPU
4648
5458
case OPC_MOVCI:
4649
gen_op_cp1_enabled();
4650
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
4651
(ctx->opcode >> 16) & 1);
5459
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
5460
save_cpu_state(ctx, 1);
5461
check_cp1_enabled(ctx);
5462
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
5463
(ctx->opcode >> 16) & 1);
5464
} else {
5465
generate_exception_err(ctx, EXCP_CpU, 1);
5466
}
4652
5467
break;
4653
#endif
4654
5468
4655
#ifdef MIPS_HAS_MIPS64
5469
#ifdef TARGET_MIPS64
4656
5470
/* MIPS64 specific opcodes */
4657
5471
case OPC_DSLL:
4658
5472
case OPC_DSRL ... OPC_DSRA:
4659
5473
case OPC_DSLL32:
4660
5474
case OPC_DSRL32 ... OPC_DSRA32:
5475
if (!(ctx->hflags & MIPS_HFLAG_64))
5476
generate_exception(ctx, EXCP_RI);
4661
5477
gen_arith_imm(ctx, op1, rd, rt, sa);
4662
5478
break;
4663
5479
case OPC_DSLLV:
4664
5480
case OPC_DSRLV ... OPC_DSRAV:
4665
5481
case OPC_DADD ... OPC_DSUBU:
5482
if (!(ctx->hflags & MIPS_HFLAG_64))
5483
generate_exception(ctx, EXCP_RI);
4666
5484
gen_arith(ctx, op1, rd, rs, rt);
4667
5485
break;
4668
5486
case OPC_DMULT ... OPC_DDIVU:
5487
if (!(ctx->hflags & MIPS_HFLAG_64))
5488
generate_exception(ctx, EXCP_RI);
4669
5489
gen_muldiv(ctx, op1, rs, rt);
4670
5490
break;
4671
5491
#endif
4699
5519
}
4700
5520
/* Treat as a noop */
4701
5521
break;
4702
#ifdef MIPS_HAS_MIPS64
5522
#ifdef TARGET_MIPS64
4703
5523
case OPC_DCLZ ... OPC_DCLO:
5524
if (!(ctx->hflags & MIPS_HFLAG_64))
5525
generate_exception(ctx, EXCP_RI);
4704
5526
gen_cl(ctx, op1, rd, rs);
4705
5527
break;
4706
5528
#endif
4711
5533
}
4712
5534
break;
4713
5535
case OPC_SPECIAL3:
4714
op1 = MASK_SPECIAL3(ctx->opcode);
4715
switch (op1) {
4716
case OPC_EXT:
4717
case OPC_INS:
5536
check_mips_r2(env, ctx);
5537
op1 = MASK_SPECIAL3(ctx->opcode);
5538
switch (op1) {
5539
case OPC_EXT:
5540
case OPC_INS:
5541
gen_bitops(ctx, op1, rt, rs, sa, rd);
5542
break;
5543
case OPC_BSHFL:
5544
op2 = MASK_BSHFL(ctx->opcode);
5545
switch (op2) {
5546
case OPC_WSBH:
5547
GEN_LOAD_REG_TN(T1, rt);
5548
gen_op_wsbh();
5549
break;
5550
case OPC_SEB:
5551
GEN_LOAD_REG_TN(T1, rt);
5552
gen_op_seb();
5553
break;
5554
case OPC_SEH:
5555
GEN_LOAD_REG_TN(T1, rt);
5556
gen_op_seh();
5557
break;
5558
default: /* Invalid */
5559
MIPS_INVAL("bshfl");
5560
generate_exception(ctx, EXCP_RI);
5561
break;
5562
}
5563
GEN_STORE_TN_REG(rd, T0);
5564
break;
5565
case OPC_RDHWR:
5566
switch (rd) {
5567
case 0:
5568
save_cpu_state(ctx, 1);
5569
gen_op_rdhwr_cpunum();
5570
break;
5571
case 1:
5572
save_cpu_state(ctx, 1);
5573
gen_op_rdhwr_synci_step();
5574
break;
5575
case 2:
5576
save_cpu_state(ctx, 1);
5577
gen_op_rdhwr_cc();
5578
break;
5579
case 3:
5580
save_cpu_state(ctx, 1);
5581
gen_op_rdhwr_ccres();
5582
break;
5583
case 29:
5584
#if defined (CONFIG_USER_ONLY)
5585
gen_op_tls_value ();
5586
break;
5587
#endif
5588
default: /* Invalid */
5589
MIPS_INVAL("rdhwr");
5590
generate_exception(ctx, EXCP_RI);
5591
break;
5592
}
5593
GEN_STORE_TN_REG(rt, T0);
5594
break;
5595
#ifdef TARGET_MIPS64
5596
case OPC_DEXTM ... OPC_DEXT:
5597
case OPC_DINSM ... OPC_DINS:
5598
if (!(ctx->hflags & MIPS_HFLAG_64))
5599
generate_exception(ctx, EXCP_RI);
4718
5600
gen_bitops(ctx, op1, rt, rs, sa, rd);
4719
5601
break;
4720
case OPC_BSHFL:
4721
op2 = MASK_BSHFL(ctx->opcode);
5602
case OPC_DBSHFL:
5603
if (!(ctx->hflags & MIPS_HFLAG_64))
5604
generate_exception(ctx, EXCP_RI);
5605
op2 = MASK_DBSHFL(ctx->opcode);
4722
5606
switch (op2) {
4723
case OPC_WSBH:
4724
GEN_LOAD_REG_TN(T1, rt);
4725
gen_op_wsbh();
4726
break;
4727
case OPC_SEB:
4728
GEN_LOAD_REG_TN(T1, rt);
4729
gen_op_seb();
4730
break;
4731
case OPC_SEH:
4732
GEN_LOAD_REG_TN(T1, rt);
4733
gen_op_seh();
4734
break;
4735
default: /* Invalid */
4736
MIPS_INVAL("bshfl");
4737
generate_exception(ctx, EXCP_RI);
4738
break;
4739
}
4740
GEN_STORE_TN_REG(rd, T0);
4741
break;
4742
case OPC_RDHWR:
4743
switch (rd) {
4744
case 0:
4745
gen_op_rdhwr_cpunum();
4746
break;
4747
case 1:
4748
gen_op_rdhwr_synci_step();
4749
break;
4750
case 2:
4751
gen_op_rdhwr_cc();
4752
break;
4753
case 3:
4754
gen_op_rdhwr_ccres();
4755
break;
4756
default: /* Invalid */
4757
MIPS_INVAL("rdhwr");
4758
generate_exception(ctx, EXCP_RI);
4759
break;
4760
}
4761
GEN_STORE_TN_REG(rt, T0);
4762
break;
4763
#ifdef MIPS_HAS_MIPS64
4764
case OPC_DEXTM ... OPC_DEXT:
4765
case OPC_DINSM ... OPC_DINS:
4766
gen_bitops(ctx, op1, rt, rs, sa, rd);
4767
break;
4768
case OPC_DBSHFL:
4769
op2 = MASK_DBSHFL(ctx->opcode);
4770
switch (op2) {
4771
case OPC_DSBH:
4772
GEN_LOAD_REG_TN(T1, rt);
4773
gen_op_dsbh();
4774
break;
4775
case OPC_DSHD:
4776
GEN_LOAD_REG_TN(T1, rt);
4777
gen_op_dshd();
4778
break;
5607
case OPC_DSBH:
5608
GEN_LOAD_REG_TN(T1, rt);
5609
gen_op_dsbh();
5610
break;
5611
case OPC_DSHD:
5612
GEN_LOAD_REG_TN(T1, rt);
5613
gen_op_dshd();
5614
break;
4779
5615
default: /* Invalid */
4780
5616
MIPS_INVAL("dbshfl");
4781
5617
generate_exception(ctx, EXCP_RI);
4782
5618
break;
4783
}
4784
GEN_STORE_TN_REG(rd, T0);
5619
}
5620
GEN_STORE_TN_REG(rd, T0);
4785
5621
#endif
4786
5622
default: /* Invalid */
4787
5623
MIPS_INVAL("special3");
4801
5637
gen_trap(ctx, op1, rs, -1, imm);
4802
5638
break;
4803
5639
case OPC_SYNCI:
4804
/* treat as noop */
5640
check_mips_r2(env, ctx);
5641
/* treat as noop */
4805
5642
break;
4806
5643
default: /* Invalid */
4807
MIPS_INVAL("REGIMM");
5644
MIPS_INVAL("regimm");
4808
5645
generate_exception(ctx, EXCP_RI);
4809
5646
break;
4810
5647
}
4811
5648
break;
4812
5649
case OPC_CP0:
5650
save_cpu_state(ctx, 1);
5651
gen_op_cp0_enabled();
4813
5652
op1 = MASK_CP0(ctx->opcode);
4814
5653
switch (op1) {
4815
5654
case OPC_MFC0:
4816
5655
case OPC_MTC0:
4817
#ifdef MIPS_HAS_MIPS64
5656
#ifdef TARGET_MIPS64
4818
5657
case OPC_DMFC0:
4819
5658
case OPC_DMTC0:
4820
5659
#endif
4821
gen_cp0(ctx, op1, rt, rd);
5660
gen_cp0(env, ctx, op1, rt, rd);
4822
5661
break;
4823
5662
case OPC_C0_FIRST ... OPC_C0_LAST:
4824
gen_cp0(ctx, MASK_C0(ctx->opcode), rt, rd);
5663
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
4825
5664
break;
4826
5665
case OPC_MFMC0:
5666
check_mips_r2(env, ctx);
4827
5667
op2 = MASK_MFMC0(ctx->opcode);
4828
5668
switch (op2) {
4829
5669
case OPC_DI:
4837
5677
ctx->bstate = BS_STOP;
4838
5678
break;
4839
5679
default: /* Invalid */
4840
MIPS_INVAL("MFMC0");
5680
MIPS_INVAL("mfmc0");
4841
5681
generate_exception(ctx, EXCP_RI);
4842
5682
break;
4843
5683
}
4844
5684
GEN_STORE_TN_REG(rt, T0);
4845
5685
break;
4846
/* Shadow registers (not implemented). */
4847
5686
case OPC_RDPGPR:
4848
5687
case OPC_WRPGPR:
5688
check_mips_r2(env, ctx);
5689
/* Shadow registers not implemented. */
5690
GEN_LOAD_REG_TN(T0, rt);
5691
GEN_STORE_TN_REG(rd, T0);
5692
break;
4849
5693
default:
5694
MIPS_INVAL("cp0");
4850
5695
generate_exception(ctx, EXCP_RI);
4851
5696
break;
4852
5697
}
4870
5715
gen_ldst(ctx, op, rt, rs, imm);
4871
5716
break;
4872
5717
case OPC_CACHE:
4873
/* Treat as a noop */
4874
break;
5718
/* Treat as a noop */
5719
break;
4875
5720
case OPC_PREF:
4876
5721
/* Treat as a noop */
4877
5722
break;
4878
5723
4879
/* Floating point. */
5724
/* Floating point (COP1). */
4880
5725
case OPC_LWC1:
4881
5726
case OPC_LDC1:
4882
5727
case OPC_SWC1:
4883
5728
case OPC_SDC1:
4884
#if defined(MIPS_USES_FPU)
4885
save_cpu_state(ctx, 1);
4886
gen_op_cp1_enabled();
4887
gen_flt_ldst(ctx, op, rt, rs, imm);
4888
#else
4889
generate_exception_err(ctx, EXCP_CpU, 1);
4890
#endif
5729
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
5730
save_cpu_state(ctx, 1);
5731
check_cp1_enabled(ctx);
5732
gen_flt_ldst(ctx, op, rt, rs, imm);
5733
} else {
5734
generate_exception_err(ctx, EXCP_CpU, 1);
5735
}
4891
5736
break;
4892
5737
4893
5738
case OPC_CP1:
4894
#if defined(MIPS_USES_FPU)
4895
save_cpu_state(ctx, 1);
4896
gen_op_cp1_enabled();
4897
op1 = MASK_CP1(ctx->opcode);
4898
switch (op1) {
4899
case OPC_MFC1:
4900
case OPC_CFC1:
4901
case OPC_MTC1:
4902
case OPC_CTC1:
4903
#ifdef MIPS_HAS_MIPS64
4904
case OPC_DMFC1:
4905
case OPC_DMTC1:
5739
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
5740
save_cpu_state(ctx, 1);
5741
check_cp1_enabled(ctx);
5742
op1 = MASK_CP1(ctx->opcode);
5743
switch (op1) {
5744
case OPC_MFHC1:
5745
case OPC_MTHC1:
5746
check_mips_r2(env, ctx);
5747
case OPC_MFC1:
5748
case OPC_CFC1:
5749
case OPC_MTC1:
5750
case OPC_CTC1:
5751
#ifdef TARGET_MIPS64
5752
case OPC_DMFC1:
5753
case OPC_DMTC1:
4906
5754
#endif
4907
gen_cp1(ctx, op1, rt, rd);
4908
break;
4909
case OPC_BC1:
4910
gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
4911
return;
4912
case OPC_S_FMT:
4913
case OPC_D_FMT:
4914
case OPC_W_FMT:
4915
case OPC_L_FMT:
4916
gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
4917
break;
4918
default:
4919
generate_exception_err(ctx, EXCP_RI, 1);
4920
break;
5755
gen_cp1(ctx, op1, rt, rd);
5756
break;
5757
case OPC_BC1:
5758
case OPC_BC1ANY2:
5759
case OPC_BC1ANY4:
5760
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
5761
(rt >> 2) & 0x7, imm << 2);
5762
return;
5763
case OPC_S_FMT:
5764
case OPC_D_FMT:
5765
case OPC_W_FMT:
5766
case OPC_L_FMT:
5767
case OPC_PS_FMT:
5768
gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
5769
(imm >> 8) & 0x7);
5770
break;
5771
default:
5772
MIPS_INVAL("cp1");
5773
generate_exception (ctx, EXCP_RI);
5774
break;
5775
}
5776
} else {
5777
generate_exception_err(ctx, EXCP_CpU, 1);
4921
5778
}
4922
#else
4923
generate_exception_err(ctx, EXCP_CpU, 1);
4924
#endif
4925
5779
break;
4926
5780
4927
5781
/* COP2. */
4934
5788
generate_exception_err(ctx, EXCP_CpU, 2);
4935
5789
break;
4936
5790
4937
#ifdef MIPS_USES_FPU
4938
5791
case OPC_CP3:
4939
gen_op_cp1_enabled();
4940
op1 = MASK_CP3(ctx->opcode);
4941
switch (op1) {
4942
/* Not implemented */
4943
default:
4944
generate_exception_err(ctx, EXCP_RI, 1);
4945
break;
5792
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
5793
save_cpu_state(ctx, 1);
5794
check_cp1_enabled(ctx);
5795
op1 = MASK_CP3(ctx->opcode);
5796
switch (op1) {
5797
case OPC_LWXC1:
5798
case OPC_LDXC1:
5799
case OPC_LUXC1:
5800
case OPC_SWXC1:
5801
case OPC_SDXC1:
5802
case OPC_SUXC1:
5803
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
5804
break;
5805
case OPC_PREFX:
5806
/* treat as noop */
5807
break;
5808
case OPC_ALNV_PS:
5809
case OPC_MADD_S:
5810
case OPC_MADD_D:
5811
case OPC_MADD_PS:
5812
case OPC_MSUB_S:
5813
case OPC_MSUB_D:
5814
case OPC_MSUB_PS:
5815
case OPC_NMADD_S:
5816
case OPC_NMADD_D:
5817
case OPC_NMADD_PS:
5818
case OPC_NMSUB_S:
5819
case OPC_NMSUB_D:
5820
case OPC_NMSUB_PS:
5821
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
5822
break;
5823
default:
5824
MIPS_INVAL("cp3");
5825
generate_exception (ctx, EXCP_RI);
5826
break;
5827
}
5828
} else {
5829
generate_exception_err(ctx, EXCP_CpU, 1);
4946
5830
}
4947
5831
break;
4948
#endif
4949
5832
4950
#ifdef MIPS_HAS_MIPS64
5833
#ifdef TARGET_MIPS64
4951
5834
/* MIPS64 opcodes */
4952
5835
case OPC_LWU:
4953
5836
case OPC_LDL ... OPC_LDR:
4956
5839
case OPC_LD:
4957
5840
case OPC_SCD:
4958
5841
case OPC_SD:
5842
if (!(ctx->hflags & MIPS_HFLAG_64))
5843
generate_exception(ctx, EXCP_RI);
4959
5844
gen_ldst(ctx, op, rt, rs, imm);
4960
5845
break;
4961
5846
case OPC_DADDI ... OPC_DADDIU:
5847
if (!(ctx->hflags & MIPS_HFLAG_64))
5848
generate_exception(ctx, EXCP_RI);
4962
5849
gen_arith_imm(ctx, op, rt, rs, imm);
4963
5850
break;
4964
5851
#endif
4971
5858
/* MDMX: Not implemented. */
4972
5859
#endif
4973
5860
default: /* Invalid */
4974
MIPS_INVAL("");
5861
MIPS_INVAL("major opcode");
4975
5862
generate_exception(ctx, EXCP_RI);
4976
5863
break;
4977
5864
}
4978
5865
if (ctx->hflags & MIPS_HFLAG_BMASK) {
4979
int hflags = ctx->hflags;
5866
int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
4980
5867
/* Branches completion */
4981
5868
ctx->hflags &= ~MIPS_HFLAG_BMASK;
4982
5869
ctx->bstate = BS_BRANCH;
4983
5870
save_cpu_state(ctx, 0);
4984
switch (hflags & MIPS_HFLAG_BMASK) {
5871
switch (hflags) {
4985
5872
case MIPS_HFLAG_B:
4986
5873
/* unconditional branch */
4987
5874
MIPS_DEBUG("unconditional branch");
5008
5895
/* unconditional branch to register */
5009
5896
MIPS_DEBUG("branch to register");
5010
5897
gen_op_breg();
5898
gen_op_reset_T0();
5899
gen_op_exit_tb();
5011
5900
break;
5012
5901
default:
5013
5902
MIPS_DEBUG("unknown branch");
5016
5905
}
5017
5906
}
5018
5907
5019
int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
5020
int search_pc)
5908
static inline int
5909
gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
5910
int search_pc)
5021
5911
{
5022
DisasContext ctx, *ctxp = &ctx;
5912
DisasContext ctx;
5023
5913
target_ulong pc_start;
5024
5914
uint16_t *gen_opc_end;
5025
5915
int j, lj = -1;
5038
5928
ctx.bstate = BS_NONE;
5039
5929
/* Restore delay slot state from the tb context. */
5040
5930
ctx.hflags = tb->flags;
5041
ctx.saved_hflags = ctx.hflags;
5042
if (ctx.hflags & MIPS_HFLAG_BR) {
5043
gen_op_restore_breg_target();
5044
} else if (ctx.hflags & MIPS_HFLAG_B) {
5045
ctx.btarget = env->btarget;
5046
} else if (ctx.hflags & MIPS_HFLAG_BMASK) {
5047
/* If we are in the delay slot of a conditional branch,
5048
* restore the branch condition from env->bcond to T2
5049
*/
5050
ctx.btarget = env->btarget;
5051
gen_op_restore_bcond();
5052
}
5931
restore_cpu_state(env, &ctx);
5053
5932
#if defined(CONFIG_USER_ONLY)
5054
5933
ctx.mem_idx = 0;
5055
5934
#else
5056
5935
ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
5057
5936
#endif
5058
ctx.CP0_Status = env->CP0_Status;
5059
5937
#ifdef DEBUG_DISAS
5060
5938
if (loglevel & CPU_LOG_TB_CPU) {
5061
5939
fprintf(logfile, "------------------------------------------------\n");
5063
5941
cpu_dump_state(env, logfile, fprintf, 0);
5064
5942
}
5065
5943
#endif
5066
#if defined MIPS_DEBUG_DISAS
5944
#ifdef MIPS_DEBUG_DISAS
5067
5945
if (loglevel & CPU_LOG_TB_IN_ASM)
5068
5946
fprintf(logfile, "\ntb %p super %d cond %04x\n",
5069
5947
tb, ctx.mem_idx, ctx.hflags);
5072
5950
if (env->nb_breakpoints > 0) {
5073
5951
for(j = 0; j < env->nb_breakpoints; j++) {
5074
5952
if (env->breakpoints[j] == ctx.pc) {
5075
save_cpu_state(ctxp, 1);
5953
save_cpu_state(&ctx, 1);
5076
5954
ctx.bstate = BS_BRANCH;
5077
5955
gen_op_debug();
5078
5956
goto done_generating;
5092
5970
gen_opc_instr_start[lj] = 1;
5093
5971
}
5094
5972
ctx.opcode = ldl_code(ctx.pc);
5095
decode_opc(&ctx);
5973
decode_opc(env, &ctx);
5096
5974
ctx.pc += 4;
5097
5975
5098
5976
if (env->singlestep_enabled)
5106
5984
#endif
5107
5985
}
5108
5986
if (env->singlestep_enabled) {
5109
save_cpu_state(ctxp, ctx.bstate == BS_NONE);
5987
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
5110
5988
gen_op_debug();
5111
goto done_generating;
5112
}
5113
else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
5114
save_cpu_state(ctxp, 0);
5115
gen_goto_tb(&ctx, 0, ctx.pc);
5116
}
5117
gen_op_reset_T0();
5118
/* Generate the return instruction */
5119
gen_op_exit_tb();
5989
} else {
5990
switch (ctx.bstate) {
5991
case BS_STOP:
5992
gen_op_interrupt_restart();
5993
gen_goto_tb(&ctx, 0, ctx.pc);
5994
break;
5995
case BS_NONE:
5996
save_cpu_state(&ctx, 0);
5997
gen_goto_tb(&ctx, 0, ctx.pc);
5998
break;
5999
case BS_EXCP:
6000
gen_op_interrupt_restart();
6001
gen_op_reset_T0();
6002
gen_op_exit_tb();
6003
break;
6004
case BS_BRANCH:
6005
default:
6006
break;
6007
}
6008
}
5120
6009
done_generating:
5121
6010
*gen_opc_ptr = INDEX_op_end;
5122
6011
if (search_pc) {
5135
6024
#endif
5136
6025
if (loglevel & CPU_LOG_TB_IN_ASM) {
5137
6026
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
5138
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
6027
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
5139
6028
fprintf(logfile, "\n");
5140
6029
}
5141
6030
if (loglevel & CPU_LOG_TB_OP) {
5161
6050
return gen_intermediate_code_internal(env, tb, 1);
5162
6051
}
5163
6052
5164
#ifdef MIPS_USES_FPU
5165
5166
6053
void fpu_dump_state(CPUState *env, FILE *f,
5167
6054
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
5168
6055
int flags)
5169
6056
{
5170
6057
int i;
6058
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
5171
6059
5172
# define printfpr(fp) do { \
5173
fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \
5174
(fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \
6060
#define printfpr(fp) \
6061
do { \
6062
if (is_fpu64) \
6063
fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6064
(fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6065
(fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6066
else { \
6067
fpr_t tmp; \
6068
tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6069
tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6070
fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6071
tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6072
tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6073
} \
5175
6074
} while(0)
5176
6075
5177
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n",
5178
env->fcr0, env->fcr31,
5179
(env->CP0_Status & (1 << CP0St_FR)) != 0);
6076
6077
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6078
env->fcr0, env->fcr31, is_fpu64, env->fp_status, get_float_exception_flags(&env->fp_status));
5180
6079
fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
5181
6080
fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
5182
6081
fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
5183
for(i = 0; i < 32; i += 2) {
5184
fpu_fprintf(f, "%s: ", fregnames[i]);
5185
printfpr(FPR(env, i));
6082
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
6083
fpu_fprintf(f, "%3s: ", fregnames[i]);
6084
printfpr(&env->fpr[i]);
5186
6085
}
5187
6086
5188
6087
#undef printfpr
5191
6090
void dump_fpu (CPUState *env)
5192
6091
{
5193
6092
if (loglevel) {
5194
fprintf(logfile, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
6093
fprintf(logfile, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
5195
6094
env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5196
6095
fpu_dump_state(env, logfile, fprintf, 0);
5197
6096
}
5198
6097
}
5199
6098
5200
#endif /* MIPS_USES_FPU */
5201
5202
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6099
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5203
6100
/* Debug help: The architecture requires 32bit code to maintain proper
5204
6101
sign-extened values on 64bit machines. */
5205
6102
5212
6109
int i;
5213
6110
5214
6111
if (!SIGN_EXT_P(env->PC))
5215
cpu_fprintf(f, "BROKEN: pc=0x" TLSZ "\n", env->PC);
6112
cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC);
5216
6113
if (!SIGN_EXT_P(env->HI))
5217
cpu_fprintf(f, "BROKEN: HI=0x" TLSZ "\n", env->HI);
6114
cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI);
5218
6115
if (!SIGN_EXT_P(env->LO))
5219
cpu_fprintf(f, "BROKEN: LO=0x" TLSZ "\n", env->LO);
6116
cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO);
5220
6117
if (!SIGN_EXT_P(env->btarget))
5221
cpu_fprintf(f, "BROKEN: btarget=0x" TLSZ "\n", env->btarget);
6118
cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
5222
6119
5223
6120
for (i = 0; i < 32; i++) {
5224
6121
if (!SIGN_EXT_P(env->gpr[i]))
5225
cpu_fprintf(f, "BROKEN: %s=0x" TLSZ "\n", regnames[i], env->gpr[i]);
6122
cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i]);
5226
6123
}
5227
6124
5228
6125
if (!SIGN_EXT_P(env->CP0_EPC))
5229
cpu_fprintf(f, "BROKEN: EPC=0x" TLSZ "\n", env->CP0_EPC);
6126
cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
5230
6127
if (!SIGN_EXT_P(env->CP0_LLAddr))
5231
cpu_fprintf(f, "BROKEN: LLAddr=0x" TLSZ "\n", env->CP0_LLAddr);
6128
cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr);
5232
6129
}
5233
6130
#endif
5234
6131
5236
6133
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5237
6134
int flags)
5238
6135
{
5239
uint32_t c0_status;
5240
6136
int i;
5241
6137
5242
cpu_fprintf(f, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
6138
cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
5243
6139
env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5244
6140
for (i = 0; i < 32; i++) {
5245
6141
if ((i & 3) == 0)
5246
6142
cpu_fprintf(f, "GPR%02d:", i);
5247
cpu_fprintf(f, " %s " TLSZ, regnames[i], env->gpr[i]);
6143
cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);
5248
6144
if ((i & 3) == 3)
5249
6145
cpu_fprintf(f, "\n");
5250
6146
}
5251
6147
5252
c0_status = env->CP0_Status;
5253
if (env->hflags & MIPS_HFLAG_UM)
5254
c0_status |= (1 << CP0St_UM);
5255
if (env->hflags & MIPS_HFLAG_ERL)
5256
c0_status |= (1 << CP0St_ERL);
5257
if (env->hflags & MIPS_HFLAG_EXL)
5258
c0_status |= (1 << CP0St_EXL);
5259
5260
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TLSZ "\n",
5261
c0_status, env->CP0_Cause, env->CP0_EPC);
5262
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TLSZ "\n",
6148
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
6149
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
6150
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
5263
6151
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
5264
#ifdef MIPS_USES_FPU
5265
if (c0_status & (1 << CP0St_CU1))
6152
if (env->hflags & MIPS_HFLAG_FPU)
5266
6153
fpu_dump_state(env, f, cpu_fprintf, flags);
5267
#endif
5268
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6154
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5269
6155
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
5270
6156
#endif
5271
6157
}
5294
6180
/* If the exception was raised from a delay slot,
5295
6181
* come back to the jump. */
5296
6182
env->CP0_ErrorEPC = env->PC - 4;
5297
env->hflags &= ~MIPS_HFLAG_BMASK;
5298
6183
} else {
5299
6184
env->CP0_ErrorEPC = env->PC;
5300
6185
}
6186
#ifdef TARGET_MIPS64
6187
env->hflags = MIPS_HFLAG_64;
6188
#else
6189
env->hflags = 0;
6190
#endif
5301
6191
env->PC = (int32_t)0xBFC00000;
5302
#if defined (MIPS_USES_R4K_TLB)
5303
env->CP0_Random = MIPS_TLB_NB - 1;
5304
env->tlb_in_use = MIPS_TLB_NB;
5305
#endif
5306
6192
env->CP0_Wired = 0;
5307
6193
/* SMP not implemented */
5308
6194
env->CP0_EBase = 0x80000000;
5309
env->CP0_Config0 = MIPS_CONFIG0;
5310
env->CP0_Config1 = MIPS_CONFIG1;
5311
env->CP0_Config2 = MIPS_CONFIG2;
5312
env->CP0_Config3 = MIPS_CONFIG3;
5313
6195
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
5314
env->CP0_WatchLo = 0;
5315
env->hflags = MIPS_HFLAG_ERL;
6196
/* vectored interrupts not implemented, timer on int 7,
6197
no performance counters. */
6198
env->CP0_IntCtl = 0xe0000000;
6199
{
6200
int i;
6201
6202
for (i = 0; i < 7; i++) {
6203
env->CP0_WatchLo[i] = 0;
6204
env->CP0_WatchHi[i] = 0x80000000;
6205
}
6206
env->CP0_WatchLo[7] = 0;
6207
env->CP0_WatchHi[7] = 0;
6208
}
5316
6209
/* Count register increments in debug mode, EJTAG version 1 */
5317
6210
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
5318
env->CP0_PRid = MIPS_CPU;
5319
6211
#endif
5320
6212
env->exception_index = EXCP_NONE;
5321
6213
#if defined(CONFIG_USER_ONLY)
5322
6214
env->hflags |= MIPS_HFLAG_UM;
5323
6215
env->user_mode_only = 1;
5324
6216
#endif
5325
#ifdef MIPS_USES_FPU
5326
env->fcr0 = MIPS_FCR0;
5327
#endif
5328
/* XXX some guesswork here, values are CPU specific */
5329
env->SYNCI_Step = 16;
5330
env->CCRes = 2;
5331
6217
}
6218
6219
#include "translate_init.c"
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