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typedef struct MiscState {
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uint8_t aux1, aux2;
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uint8_t diag, mctrl, sysctrl;
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#define MISC_MAXADDR 1
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static void slavio_misc_update_irq(void *opaque)
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MiscState *s = opaque;
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if ((s->aux2 & 0x4) && (s->config & 0x8)) {
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pic_set_irq(s->irq, 1);
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MISC_DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq);
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pic_set_irq(s->irq, 0);
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MISC_DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq);
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static void slavio_misc_save(QEMUFile *f, void *opaque)
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MiscState *s = opaque;
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qemu_put_be32s(f, &s->irq);
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qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
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qemu_put_8s(f, &s->config);
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qemu_put_8s(f, &s->aux1);
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qemu_put_8s(f, &s->aux2);
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static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
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MiscState *s = opaque;
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if (version_id != 1)
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qemu_get_be32s(f, &s->irq);
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qemu_get_be32s(f, &tmp);
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qemu_get_8s(f, &s->config);
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qemu_get_8s(f, &s->aux1);
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qemu_get_8s(f, &s->aux2);
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void *slavio_misc_init(uint32_t base, int irq)
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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int slavio_misc_io_memory;
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slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
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// Slavio control
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cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
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slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
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slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
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slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
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slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
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slavio_misc_io_memory);
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// System control
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cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(base + 0x1f00000, MISC_SIZE,
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slavio_misc_io_memory);
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// Power management
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cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
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cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);