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Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816

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hw/serial.c
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    /* NOTE: this hidden state is necessary for tx irq generation as
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       it can be reset while reading iir */
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    int thr_ipending;
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    SetIRQFunc *set_irq;
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    void *irq_opaque;
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    int irq;
 
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    qemu_irq irq;
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    CharDriverState *chr;
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    int last_break_enable;
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    target_ulong base;
 
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    target_phys_addr_t base;
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    int it_shift;
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};
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        s->iir = UART_IIR_NO_INT;
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    }
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    if (s->iir != UART_IIR_NO_INT) {
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        s->set_irq(s->irq_opaque, s->irq, 1);
 
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        qemu_irq_raise(s->irq);
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    } else {
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        s->set_irq(s->irq_opaque, s->irq, 0);
 
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        qemu_irq_lower(s->irq);
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    }
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}
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}
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/* If fd is zero, it means that the serial device uses the console */
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SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
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                         int base, int irq, CharDriverState *chr)
 
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SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
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{
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    SerialState *s;
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    s = qemu_mallocz(sizeof(SerialState));
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    if (!s)
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        return NULL;
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    s->set_irq = set_irq;
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    s->irq_opaque = opaque;
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    s->irq = irq;
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    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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    s->iir = UART_IIR_NO_INT;
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}
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/* Memory mapped interface */
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static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 
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uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
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{
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    SerialState *s = opaque;
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    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
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}
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static void serial_mm_writeb (void *opaque,
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                              target_phys_addr_t addr, uint32_t value)
 
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void serial_mm_writeb (void *opaque,
 
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                       target_phys_addr_t addr, uint32_t value)
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{
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    SerialState *s = opaque;
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    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
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}
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static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 
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uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
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{
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    SerialState *s = opaque;
 
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    uint32_t val;
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    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 
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    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 
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#ifdef TARGET_WORDS_BIGENDIAN
 
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    val = bswap16(val);
 
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#endif
 
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    return val;
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}
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static void serial_mm_writew (void *opaque,
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                              target_phys_addr_t addr, uint32_t value)
 
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void serial_mm_writew (void *opaque,
 
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                       target_phys_addr_t addr, uint32_t value)
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{
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    SerialState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
 
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    value = bswap16(value);
 
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#endif
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    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
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}
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static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 
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uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
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{
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    SerialState *s = opaque;
 
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    uint32_t val;
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    return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 
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    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 
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#ifdef TARGET_WORDS_BIGENDIAN
 
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    val = bswap32(val);
 
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#endif
 
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    return val;
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}
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static void serial_mm_writel (void *opaque,
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                              target_phys_addr_t addr, uint32_t value)
 
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void serial_mm_writel (void *opaque,
 
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                       target_phys_addr_t addr, uint32_t value)
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{
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    SerialState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
 
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    value = bswap32(value);
 
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#endif
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    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
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}
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    &serial_mm_writel,
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};
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SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
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                             target_ulong base, int it_shift,
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                             int irq, CharDriverState *chr)
 
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 
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                             qemu_irq irq, CharDriverState *chr,
 
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                             int ioregister)
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{
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    SerialState *s;
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    int s_io_memory;
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    s = qemu_mallocz(sizeof(SerialState));
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    if (!s)
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        return NULL;
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    s->set_irq = set_irq;
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    s->irq_opaque = opaque;
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    s->irq = irq;
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    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
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    s->iir = UART_IIR_NO_INT;
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    register_savevm("serial", base, 2, serial_save, serial_load, s);
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    s_io_memory = cpu_register_io_memory(0, serial_mm_read,
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                                         serial_mm_write, s);
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    cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 
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    if (ioregister) {
 
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        s_io_memory = cpu_register_io_memory(0, serial_mm_read,
 
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                                             serial_mm_write, s);
 
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        cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 
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    }
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    s->chr = chr;
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    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
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                          serial_event, s);