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hw/integratorcp.c

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/* 

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 * ARM Integrator CP System emulation.

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 *

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 * Copyright (c) 2005-2006 CodeSourcery.

 

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 * Copyright (c) 2005-2007 CodeSourcery.

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 * Written by Paul Brook

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 *

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 * This code is licenced under the GPL

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    iomemtype = cpu_register_io_memory(0, integratorcm_readfn,

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                                       integratorcm_writefn, s);

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    cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype);

 

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    cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype);

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    integratorcm_do_remap(s, 1);

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    /* ??? Save/restore.  */

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}

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typedef struct icp_pic_state

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{

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  arm_pic_handler handler;

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  uint32_t base;

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  uint32_t level;

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  uint32_t irq_enabled;

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  uint32_t fiq_enabled;

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  void *parent;

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  int parent_irq;

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  int parent_fiq;

 

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  qemu_irq parent_irq;

 

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  qemu_irq parent_fiq;

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} icp_pic_state;

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static void icp_pic_update(icp_pic_state *s)

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{

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    uint32_t flags;

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    if (s->parent_irq != -1) {

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        flags = (s->level & s->irq_enabled);

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        pic_set_irq_new(s->parent, s->parent_irq, flags != 0);

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    }

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    if (s->parent_fiq != -1) {

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        flags = (s->level & s->fiq_enabled);

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        pic_set_irq_new(s->parent, s->parent_fiq, flags != 0);

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    }

 

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    flags = (s->level & s->irq_enabled);

 

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    qemu_set_irq(s->parent_irq, flags != 0);

 

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    flags = (s->level & s->fiq_enabled);

 

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    qemu_set_irq(s->parent_fiq, flags != 0);

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}

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static void icp_pic_set_irq(void *opaque, int irq, int level)

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        break;

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    case 4: /* INT_SOFTSET */

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        if (value & 1)

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            pic_set_irq_new(s, 0, 1);

 

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            icp_pic_set_irq(s, 0, 1);

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        break;

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    case 5: /* INT_SOFTCLR */

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        if (value & 1)

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            pic_set_irq_new(s, 0, 0);

 

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            icp_pic_set_irq(s, 0, 0);

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        break;

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    case 10: /* FRQ_ENABLESET */

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        s->fiq_enabled |= value;

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   icp_pic_write

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};

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static icp_pic_state *icp_pic_init(uint32_t base, void *parent,

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                                   int parent_irq, int parent_fiq)

 

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static qemu_irq *icp_pic_init(uint32_t base,

 

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                              qemu_irq parent_irq, qemu_irq parent_fiq)

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{

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    icp_pic_state *s;

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    int iomemtype;

 

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    qemu_irq *qi;

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    s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));

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    if (!s)

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        return NULL;

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    s->handler = icp_pic_set_irq;

 

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    qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);

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    s->base = base;

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    s->parent = parent;

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    s->parent_irq = parent_irq;

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    s->parent_fiq = parent_fiq;

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    iomemtype = cpu_register_io_memory(0, icp_pic_readfn,

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                                       icp_pic_writefn, s);

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    cpu_register_physical_memory(base, 0x007fffff, iomemtype);

 

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    cpu_register_physical_memory(base, 0x00800000, iomemtype);

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    /* ??? Save/restore.  */

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    return s;

 

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    return qi;

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}

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/* CP control registers.  */

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    s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));

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    iomemtype = cpu_register_io_memory(0, icp_control_readfn,

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                                       icp_control_writefn, s);

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    cpu_register_physical_memory(base, 0x007fffff, iomemtype);

 

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    cpu_register_physical_memory(base, 0x00800000, iomemtype);

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    s->base = base;

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    /* ??? Save/restore.  */

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}

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static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device,

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                     DisplayState *ds, const char **fd_filename, int snapshot,

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                     const char *kernel_filename, const char *kernel_cmdline,

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                     const char *initrd_filename, uint32_t cpuid)

 

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                     const char *initrd_filename, const char *cpu_model)

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{

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    CPUState *env;

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    uint32_t bios_offset;

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    icp_pic_state *pic;

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    void *cpu_pic;

 

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    qemu_irq *pic;

 

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    qemu_irq *cpu_pic;

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    env = cpu_init();

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    cpu_arm_set_model(env, cpuid);

 

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    if (!cpu_model)

 

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        cpu_model = "arm926";

 

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    cpu_arm_set_model(env, cpu_model);

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    bios_offset = ram_size + vga_ram_size;

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    /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */

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    /* ??? RAM shoud repeat to fill physical memory space.  */

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    integratorcm_init(ram_size >> 20, bios_offset);

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    cpu_pic = arm_pic_init_cpu(env);

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    pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);

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    icp_pic_init(0xca000000, pic, 26, -1);

 

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    pic = icp_pic_init(0x14000000, cpu_pic[ARM_PIC_CPU_IRQ],

 

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                       cpu_pic[ARM_PIC_CPU_FIQ]);

 

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    icp_pic_init(0xca000000, pic[26], NULL);

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    icp_pit_init(0x13000000, pic, 5);

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    pl011_init(0x16000000, pic, 1, serial_hds[0]);

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    pl011_init(0x17000000, pic, 2, serial_hds[1]);

 

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    pl031_init(0x15000000, pic[8]);

 

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    pl011_init(0x16000000, pic[1], serial_hds[0]);

 

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    pl011_init(0x17000000, pic[2], serial_hds[1]);

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    icp_control_init(0xcb000000);

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    pl050_init(0x18000000, pic, 3, 0);

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    pl050_init(0x19000000, pic, 4, 1);

 

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    pl050_init(0x18000000, pic[3], 0);

 

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    pl050_init(0x19000000, pic[4], 1);

 

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    pl181_init(0x1c000000, sd_bdrv, pic[23], pic[24]);

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    if (nd_table[0].vlan) {

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        if (nd_table[0].model == NULL

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            || strcmp(nd_table[0].model, "smc91c111") == 0) {

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            smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);

 

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            smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);

 

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        } else if (strcmp(nd_table[0].model, "?") == 0) {

 

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            fprintf(stderr, "qemu: Supported NICs: smc91c111\n");

 

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            exit (1);

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        } else {

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            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);

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            exit (1);

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        }

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    }

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    pl110_init(ds, 0xc0000000, pic, 22, 0);

 

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    pl110_init(ds, 0xc0000000, pic[22], 0);

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    arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,

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                    initrd_filename, 0x113);

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}

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static void integratorcp926_init(int ram_size, int vga_ram_size,

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    int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,

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    const char *kernel_filename, const char *kernel_cmdline,

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    const char *initrd_filename)

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{

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    integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,

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                      snapshot, kernel_filename, kernel_cmdline,

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                      initrd_filename, ARM_CPUID_ARM926);

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}

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static void integratorcp1026_init(int ram_size, int vga_ram_size,

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    int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,

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    const char *kernel_filename, const char *kernel_cmdline,

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    const char *initrd_filename)

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{

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    integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,

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                      snapshot, kernel_filename, kernel_cmdline,

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                      initrd_filename, ARM_CPUID_ARM1026);

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}

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QEMUMachine integratorcp926_machine = {

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    "integratorcp926",

 

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                    initrd_filename, 0x113, 0x0);

 

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}

 

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QEMUMachine integratorcp_machine = {

 

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    "integratorcp",

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    "ARM Integrator/CP (ARM926EJ-S)",

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    integratorcp926_init,

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};

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QEMUMachine integratorcp1026_machine = {

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    "integratorcp1026",

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    "ARM Integrator/CP (ARM1026EJ-S)",

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    integratorcp1026_init,

 

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    integratorcp_init,

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};

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